1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21 #include <linux/i2c.h> 22 #include <linux/pm_runtime.h> 23 24 #include <drm/drmP.h> 25 #include "framebuffer.h" 26 #include "psb_drv.h" 27 #include "psb_intel_drv.h" 28 #include "psb_intel_reg.h" 29 #include "psb_intel_display.h" 30 #include "power.h" 31 32 struct psb_intel_clock_t { 33 /* given values */ 34 int n; 35 int m1, m2; 36 int p1, p2; 37 /* derived values */ 38 int dot; 39 int vco; 40 int m; 41 int p; 42 }; 43 44 struct psb_intel_range_t { 45 int min, max; 46 }; 47 48 struct psb_intel_p2_t { 49 int dot_limit; 50 int p2_slow, p2_fast; 51 }; 52 53 #define INTEL_P2_NUM 2 54 55 struct psb_intel_limit_t { 56 struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1; 57 struct psb_intel_p2_t p2; 58 }; 59 60 #define I8XX_DOT_MIN 25000 61 #define I8XX_DOT_MAX 350000 62 #define I8XX_VCO_MIN 930000 63 #define I8XX_VCO_MAX 1400000 64 #define I8XX_N_MIN 3 65 #define I8XX_N_MAX 16 66 #define I8XX_M_MIN 96 67 #define I8XX_M_MAX 140 68 #define I8XX_M1_MIN 18 69 #define I8XX_M1_MAX 26 70 #define I8XX_M2_MIN 6 71 #define I8XX_M2_MAX 16 72 #define I8XX_P_MIN 4 73 #define I8XX_P_MAX 128 74 #define I8XX_P1_MIN 2 75 #define I8XX_P1_MAX 33 76 #define I8XX_P1_LVDS_MIN 1 77 #define I8XX_P1_LVDS_MAX 6 78 #define I8XX_P2_SLOW 4 79 #define I8XX_P2_FAST 2 80 #define I8XX_P2_LVDS_SLOW 14 81 #define I8XX_P2_LVDS_FAST 14 /* No fast option */ 82 #define I8XX_P2_SLOW_LIMIT 165000 83 84 #define I9XX_DOT_MIN 20000 85 #define I9XX_DOT_MAX 400000 86 #define I9XX_VCO_MIN 1400000 87 #define I9XX_VCO_MAX 2800000 88 #define I9XX_N_MIN 3 89 #define I9XX_N_MAX 8 90 #define I9XX_M_MIN 70 91 #define I9XX_M_MAX 120 92 #define I9XX_M1_MIN 10 93 #define I9XX_M1_MAX 20 94 #define I9XX_M2_MIN 5 95 #define I9XX_M2_MAX 9 96 #define I9XX_P_SDVO_DAC_MIN 5 97 #define I9XX_P_SDVO_DAC_MAX 80 98 #define I9XX_P_LVDS_MIN 7 99 #define I9XX_P_LVDS_MAX 98 100 #define I9XX_P1_MIN 1 101 #define I9XX_P1_MAX 8 102 #define I9XX_P2_SDVO_DAC_SLOW 10 103 #define I9XX_P2_SDVO_DAC_FAST 5 104 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 105 #define I9XX_P2_LVDS_SLOW 14 106 #define I9XX_P2_LVDS_FAST 7 107 #define I9XX_P2_LVDS_SLOW_LIMIT 112000 108 109 #define INTEL_LIMIT_I8XX_DVO_DAC 0 110 #define INTEL_LIMIT_I8XX_LVDS 1 111 #define INTEL_LIMIT_I9XX_SDVO_DAC 2 112 #define INTEL_LIMIT_I9XX_LVDS 3 113 114 static const struct psb_intel_limit_t psb_intel_limits[] = { 115 { /* INTEL_LIMIT_I8XX_DVO_DAC */ 116 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, 117 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, 118 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, 119 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, 120 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, 121 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, 122 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, 123 .p1 = {.min = I8XX_P1_MIN, .max = I8XX_P1_MAX}, 124 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, 125 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST}, 126 }, 127 { /* INTEL_LIMIT_I8XX_LVDS */ 128 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, 129 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, 130 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, 131 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, 132 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, 133 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, 134 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, 135 .p1 = {.min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX}, 136 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, 137 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST}, 138 }, 139 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 140 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 141 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, 142 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, 143 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, 144 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, 145 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, 146 .p = {.min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX}, 147 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, 148 .p2 = {.dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 149 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = 150 I9XX_P2_SDVO_DAC_FAST}, 151 }, 152 { /* INTEL_LIMIT_I9XX_LVDS */ 153 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 154 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, 155 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, 156 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, 157 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, 158 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, 159 .p = {.min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX}, 160 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, 161 /* The single-channel range is 25-112Mhz, and dual-channel 162 * is 80-224Mhz. Prefer single channel as much as possible. 163 */ 164 .p2 = {.dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 165 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST}, 166 }, 167 }; 168 169 static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc) 170 { 171 const struct psb_intel_limit_t *limit; 172 173 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 174 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 175 else 176 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 177 return limit; 178 } 179 180 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 181 182 static void i8xx_clock(int refclk, struct psb_intel_clock_t *clock) 183 { 184 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 185 clock->p = clock->p1 * clock->p2; 186 clock->vco = refclk * clock->m / (clock->n + 2); 187 clock->dot = clock->vco / clock->p; 188 } 189 190 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */ 191 192 static void i9xx_clock(int refclk, struct psb_intel_clock_t *clock) 193 { 194 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 195 clock->p = clock->p1 * clock->p2; 196 clock->vco = refclk * clock->m / (clock->n + 2); 197 clock->dot = clock->vco / clock->p; 198 } 199 200 static void psb_intel_clock(struct drm_device *dev, int refclk, 201 struct psb_intel_clock_t *clock) 202 { 203 return i9xx_clock(refclk, clock); 204 } 205 206 /** 207 * Returns whether any output on the specified pipe is of the specified type 208 */ 209 bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type) 210 { 211 struct drm_device *dev = crtc->dev; 212 struct drm_mode_config *mode_config = &dev->mode_config; 213 struct drm_connector *l_entry; 214 215 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 216 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { 217 struct psb_intel_encoder *psb_intel_encoder = 218 psb_intel_attached_encoder(l_entry); 219 if (psb_intel_encoder->type == type) 220 return true; 221 } 222 } 223 return false; 224 } 225 226 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } 227 /** 228 * Returns whether the given set of divisors are valid for a given refclk with 229 * the given connectors. 230 */ 231 232 static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc, 233 struct psb_intel_clock_t *clock) 234 { 235 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); 236 237 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 238 INTELPllInvalid("p1 out of range\n"); 239 if (clock->p < limit->p.min || limit->p.max < clock->p) 240 INTELPllInvalid("p out of range\n"); 241 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 242 INTELPllInvalid("m2 out of range\n"); 243 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 244 INTELPllInvalid("m1 out of range\n"); 245 if (clock->m1 <= clock->m2) 246 INTELPllInvalid("m1 <= m2\n"); 247 if (clock->m < limit->m.min || limit->m.max < clock->m) 248 INTELPllInvalid("m out of range\n"); 249 if (clock->n < limit->n.min || limit->n.max < clock->n) 250 INTELPllInvalid("n out of range\n"); 251 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 252 INTELPllInvalid("vco out of range\n"); 253 /* XXX: We may need to be checking "Dot clock" 254 * depending on the multiplier, connector, etc., 255 * rather than just a single range. 256 */ 257 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 258 INTELPllInvalid("dot out of range\n"); 259 260 return true; 261 } 262 263 /** 264 * Returns a set of divisors for the desired target clock with the given 265 * refclk, or FALSE. The returned values represent the clock equation: 266 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 267 */ 268 static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target, 269 int refclk, 270 struct psb_intel_clock_t *best_clock) 271 { 272 struct drm_device *dev = crtc->dev; 273 struct psb_intel_clock_t clock; 274 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); 275 int err = target; 276 277 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 278 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { 279 /* 280 * For LVDS, if the panel is on, just rely on its current 281 * settings for dual-channel. We haven't figured out how to 282 * reliably set up different single/dual channel state, if we 283 * even can. 284 */ 285 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 286 LVDS_CLKB_POWER_UP) 287 clock.p2 = limit->p2.p2_fast; 288 else 289 clock.p2 = limit->p2.p2_slow; 290 } else { 291 if (target < limit->p2.dot_limit) 292 clock.p2 = limit->p2.p2_slow; 293 else 294 clock.p2 = limit->p2.p2_fast; 295 } 296 297 memset(best_clock, 0, sizeof(*best_clock)); 298 299 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 300 clock.m1++) { 301 for (clock.m2 = limit->m2.min; 302 clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; 303 clock.m2++) { 304 for (clock.n = limit->n.min; 305 clock.n <= limit->n.max; clock.n++) { 306 for (clock.p1 = limit->p1.min; 307 clock.p1 <= limit->p1.max; 308 clock.p1++) { 309 int this_err; 310 311 psb_intel_clock(dev, refclk, &clock); 312 313 if (!psb_intel_PLL_is_valid 314 (crtc, &clock)) 315 continue; 316 317 this_err = abs(clock.dot - target); 318 if (this_err < err) { 319 *best_clock = clock; 320 err = this_err; 321 } 322 } 323 } 324 } 325 } 326 327 return err != target; 328 } 329 330 void psb_intel_wait_for_vblank(struct drm_device *dev) 331 { 332 /* Wait for 20ms, i.e. one cycle at 50hz. */ 333 mdelay(20); 334 } 335 336 static int psb_intel_pipe_set_base(struct drm_crtc *crtc, 337 int x, int y, struct drm_framebuffer *old_fb) 338 { 339 struct drm_device *dev = crtc->dev; 340 struct drm_psb_private *dev_priv = dev->dev_private; 341 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 342 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); 343 int pipe = psb_intel_crtc->pipe; 344 const struct psb_offset *map = &dev_priv->regmap[pipe]; 345 unsigned long start, offset; 346 u32 dspcntr; 347 int ret = 0; 348 349 if (!gma_power_begin(dev, true)) 350 return 0; 351 352 /* no fb bound */ 353 if (!crtc->fb) { 354 dev_dbg(dev->dev, "No FB bound\n"); 355 goto psb_intel_pipe_cleaner; 356 } 357 358 /* We are displaying this buffer, make sure it is actually loaded 359 into the GTT */ 360 ret = psb_gtt_pin(psbfb->gtt); 361 if (ret < 0) 362 goto psb_intel_pipe_set_base_exit; 363 start = psbfb->gtt->offset; 364 365 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); 366 367 REG_WRITE(map->stride, crtc->fb->pitches[0]); 368 369 dspcntr = REG_READ(map->cntr); 370 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 371 372 switch (crtc->fb->bits_per_pixel) { 373 case 8: 374 dspcntr |= DISPPLANE_8BPP; 375 break; 376 case 16: 377 if (crtc->fb->depth == 15) 378 dspcntr |= DISPPLANE_15_16BPP; 379 else 380 dspcntr |= DISPPLANE_16BPP; 381 break; 382 case 24: 383 case 32: 384 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 385 break; 386 default: 387 dev_err(dev->dev, "Unknown color depth\n"); 388 ret = -EINVAL; 389 psb_gtt_unpin(psbfb->gtt); 390 goto psb_intel_pipe_set_base_exit; 391 } 392 REG_WRITE(map->cntr, dspcntr); 393 394 REG_WRITE(map->base, start + offset); 395 REG_READ(map->base); 396 397 psb_intel_pipe_cleaner: 398 /* If there was a previous display we can now unpin it */ 399 if (old_fb) 400 psb_gtt_unpin(to_psb_fb(old_fb)->gtt); 401 402 psb_intel_pipe_set_base_exit: 403 gma_power_end(dev); 404 return ret; 405 } 406 407 /** 408 * Sets the power management mode of the pipe and plane. 409 * 410 * This code should probably grow support for turning the cursor off and back 411 * on appropriately at the same time as we're turning the pipe off/on. 412 */ 413 static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) 414 { 415 struct drm_device *dev = crtc->dev; 416 struct drm_psb_private *dev_priv = dev->dev_private; 417 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 418 int pipe = psb_intel_crtc->pipe; 419 const struct psb_offset *map = &dev_priv->regmap[pipe]; 420 u32 temp; 421 422 /* XXX: When our outputs are all unaware of DPMS modes other than off 423 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 424 */ 425 switch (mode) { 426 case DRM_MODE_DPMS_ON: 427 case DRM_MODE_DPMS_STANDBY: 428 case DRM_MODE_DPMS_SUSPEND: 429 /* Enable the DPLL */ 430 temp = REG_READ(map->dpll); 431 if ((temp & DPLL_VCO_ENABLE) == 0) { 432 REG_WRITE(map->dpll, temp); 433 REG_READ(map->dpll); 434 /* Wait for the clocks to stabilize. */ 435 udelay(150); 436 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 437 REG_READ(map->dpll); 438 /* Wait for the clocks to stabilize. */ 439 udelay(150); 440 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 441 REG_READ(map->dpll); 442 /* Wait for the clocks to stabilize. */ 443 udelay(150); 444 } 445 446 /* Enable the pipe */ 447 temp = REG_READ(map->conf); 448 if ((temp & PIPEACONF_ENABLE) == 0) 449 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); 450 451 /* Enable the plane */ 452 temp = REG_READ(map->cntr); 453 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 454 REG_WRITE(map->cntr, 455 temp | DISPLAY_PLANE_ENABLE); 456 /* Flush the plane changes */ 457 REG_WRITE(map->base, REG_READ(map->base)); 458 } 459 460 psb_intel_crtc_load_lut(crtc); 461 462 /* Give the overlay scaler a chance to enable 463 * if it's on this pipe */ 464 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 465 break; 466 case DRM_MODE_DPMS_OFF: 467 /* Give the overlay scaler a chance to disable 468 * if it's on this pipe */ 469 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 470 471 /* Disable the VGA plane that we never use */ 472 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 473 474 /* Disable display plane */ 475 temp = REG_READ(map->cntr); 476 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 477 REG_WRITE(map->cntr, 478 temp & ~DISPLAY_PLANE_ENABLE); 479 /* Flush the plane changes */ 480 REG_WRITE(map->base, REG_READ(map->base)); 481 REG_READ(map->base); 482 } 483 484 /* Next, disable display pipes */ 485 temp = REG_READ(map->conf); 486 if ((temp & PIPEACONF_ENABLE) != 0) { 487 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); 488 REG_READ(map->conf); 489 } 490 491 /* Wait for vblank for the disable to take effect. */ 492 psb_intel_wait_for_vblank(dev); 493 494 temp = REG_READ(map->dpll); 495 if ((temp & DPLL_VCO_ENABLE) != 0) { 496 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); 497 REG_READ(map->dpll); 498 } 499 500 /* Wait for the clocks to turn off. */ 501 udelay(150); 502 break; 503 } 504 505 /*Set FIFO Watermarks*/ 506 REG_WRITE(DSPARB, 0x3F3E); 507 } 508 509 static void psb_intel_crtc_prepare(struct drm_crtc *crtc) 510 { 511 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 512 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 513 } 514 515 static void psb_intel_crtc_commit(struct drm_crtc *crtc) 516 { 517 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 518 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 519 } 520 521 void psb_intel_encoder_prepare(struct drm_encoder *encoder) 522 { 523 struct drm_encoder_helper_funcs *encoder_funcs = 524 encoder->helper_private; 525 /* lvds has its own version of prepare see psb_intel_lvds_prepare */ 526 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 527 } 528 529 void psb_intel_encoder_commit(struct drm_encoder *encoder) 530 { 531 struct drm_encoder_helper_funcs *encoder_funcs = 532 encoder->helper_private; 533 /* lvds has its own version of commit see psb_intel_lvds_commit */ 534 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 535 } 536 537 void psb_intel_encoder_destroy(struct drm_encoder *encoder) 538 { 539 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); 540 541 drm_encoder_cleanup(encoder); 542 kfree(intel_encoder); 543 } 544 545 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, 546 struct drm_display_mode *mode, 547 struct drm_display_mode *adjusted_mode) 548 { 549 return true; 550 } 551 552 553 /** 554 * Return the pipe currently connected to the panel fitter, 555 * or -1 if the panel fitter is not present or not in use 556 */ 557 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 558 { 559 u32 pfit_control; 560 561 pfit_control = REG_READ(PFIT_CONTROL); 562 563 /* See if the panel fitter is in use */ 564 if ((pfit_control & PFIT_ENABLE) == 0) 565 return -1; 566 /* Must be on PIPE 1 for PSB */ 567 return 1; 568 } 569 570 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 571 struct drm_display_mode *mode, 572 struct drm_display_mode *adjusted_mode, 573 int x, int y, 574 struct drm_framebuffer *old_fb) 575 { 576 struct drm_device *dev = crtc->dev; 577 struct drm_psb_private *dev_priv = dev->dev_private; 578 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 579 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 580 int pipe = psb_intel_crtc->pipe; 581 const struct psb_offset *map = &dev_priv->regmap[pipe]; 582 int refclk; 583 struct psb_intel_clock_t clock; 584 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 585 bool ok, is_sdvo = false; 586 bool is_lvds = false, is_tv = false; 587 struct drm_mode_config *mode_config = &dev->mode_config; 588 struct drm_connector *connector; 589 590 /* No scan out no play */ 591 if (crtc->fb == NULL) { 592 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 593 return 0; 594 } 595 596 list_for_each_entry(connector, &mode_config->connector_list, head) { 597 struct psb_intel_encoder *psb_intel_encoder = 598 psb_intel_attached_encoder(connector); 599 600 if (!connector->encoder 601 || connector->encoder->crtc != crtc) 602 continue; 603 604 switch (psb_intel_encoder->type) { 605 case INTEL_OUTPUT_LVDS: 606 is_lvds = true; 607 break; 608 case INTEL_OUTPUT_SDVO: 609 is_sdvo = true; 610 break; 611 case INTEL_OUTPUT_TVOUT: 612 is_tv = true; 613 break; 614 } 615 } 616 617 refclk = 96000; 618 619 ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, 620 &clock); 621 if (!ok) { 622 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); 623 return 0; 624 } 625 626 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 627 628 dpll = DPLL_VGA_MODE_DIS; 629 if (is_lvds) { 630 dpll |= DPLLB_MODE_LVDS; 631 dpll |= DPLL_DVO_HIGH_SPEED; 632 } else 633 dpll |= DPLLB_MODE_DAC_SERIAL; 634 if (is_sdvo) { 635 int sdvo_pixel_multiply = 636 adjusted_mode->clock / mode->clock; 637 dpll |= DPLL_DVO_HIGH_SPEED; 638 dpll |= 639 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 640 } 641 642 /* compute bitmask from p1 value */ 643 dpll |= (1 << (clock.p1 - 1)) << 16; 644 switch (clock.p2) { 645 case 5: 646 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 647 break; 648 case 7: 649 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 650 break; 651 case 10: 652 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 653 break; 654 case 14: 655 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 656 break; 657 } 658 659 if (is_tv) { 660 /* XXX: just matching BIOS for now */ 661 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 662 dpll |= 3; 663 } 664 dpll |= PLL_REF_INPUT_DREFCLK; 665 666 /* setup pipeconf */ 667 pipeconf = REG_READ(map->conf); 668 669 /* Set up the display plane register */ 670 dspcntr = DISPPLANE_GAMMA_ENABLE; 671 672 if (pipe == 0) 673 dspcntr |= DISPPLANE_SEL_PIPE_A; 674 else 675 dspcntr |= DISPPLANE_SEL_PIPE_B; 676 677 dspcntr |= DISPLAY_PLANE_ENABLE; 678 pipeconf |= PIPEACONF_ENABLE; 679 dpll |= DPLL_VCO_ENABLE; 680 681 682 /* Disable the panel fitter if it was on our pipe */ 683 if (psb_intel_panel_fitter_pipe(dev) == pipe) 684 REG_WRITE(PFIT_CONTROL, 0); 685 686 drm_mode_debug_printmodeline(mode); 687 688 if (dpll & DPLL_VCO_ENABLE) { 689 REG_WRITE(map->fp0, fp); 690 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 691 REG_READ(map->dpll); 692 udelay(150); 693 } 694 695 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 696 * This is an exception to the general rule that mode_set doesn't turn 697 * things on. 698 */ 699 if (is_lvds) { 700 u32 lvds = REG_READ(LVDS); 701 702 lvds &= ~LVDS_PIPEB_SELECT; 703 if (pipe == 1) 704 lvds |= LVDS_PIPEB_SELECT; 705 706 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 707 /* Set the B0-B3 data pairs corresponding to 708 * whether we're going to 709 * set the DPLLs for dual-channel mode or not. 710 */ 711 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 712 if (clock.p2 == 7) 713 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 714 715 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 716 * appropriately here, but we need to look more 717 * thoroughly into how panels behave in the two modes. 718 */ 719 720 REG_WRITE(LVDS, lvds); 721 REG_READ(LVDS); 722 } 723 724 REG_WRITE(map->fp0, fp); 725 REG_WRITE(map->dpll, dpll); 726 REG_READ(map->dpll); 727 /* Wait for the clocks to stabilize. */ 728 udelay(150); 729 730 /* write it again -- the BIOS does, after all */ 731 REG_WRITE(map->dpll, dpll); 732 733 REG_READ(map->dpll); 734 /* Wait for the clocks to stabilize. */ 735 udelay(150); 736 737 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 738 ((adjusted_mode->crtc_htotal - 1) << 16)); 739 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 740 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 741 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 742 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 743 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 744 ((adjusted_mode->crtc_vtotal - 1) << 16)); 745 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 746 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 747 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 748 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 749 /* pipesrc and dspsize control the size that is scaled from, 750 * which should always be the user's requested size. 751 */ 752 REG_WRITE(map->size, 753 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 754 REG_WRITE(map->pos, 0); 755 REG_WRITE(map->src, 756 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 757 REG_WRITE(map->conf, pipeconf); 758 REG_READ(map->conf); 759 760 psb_intel_wait_for_vblank(dev); 761 762 REG_WRITE(map->cntr, dspcntr); 763 764 /* Flush the plane changes */ 765 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 766 767 psb_intel_wait_for_vblank(dev); 768 769 return 0; 770 } 771 772 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 773 void psb_intel_crtc_load_lut(struct drm_crtc *crtc) 774 { 775 struct drm_device *dev = crtc->dev; 776 struct drm_psb_private *dev_priv = dev->dev_private; 777 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 778 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; 779 int palreg = map->palette; 780 int i; 781 782 /* The clocks have to be on to load the palette. */ 783 if (!crtc->enabled) 784 return; 785 786 switch (psb_intel_crtc->pipe) { 787 case 0: 788 case 1: 789 break; 790 default: 791 dev_err(dev->dev, "Illegal Pipe Number.\n"); 792 return; 793 } 794 795 if (gma_power_begin(dev, false)) { 796 for (i = 0; i < 256; i++) { 797 REG_WRITE(palreg + 4 * i, 798 ((psb_intel_crtc->lut_r[i] + 799 psb_intel_crtc->lut_adj[i]) << 16) | 800 ((psb_intel_crtc->lut_g[i] + 801 psb_intel_crtc->lut_adj[i]) << 8) | 802 (psb_intel_crtc->lut_b[i] + 803 psb_intel_crtc->lut_adj[i])); 804 } 805 gma_power_end(dev); 806 } else { 807 for (i = 0; i < 256; i++) { 808 dev_priv->regs.pipe[0].palette[i] = 809 ((psb_intel_crtc->lut_r[i] + 810 psb_intel_crtc->lut_adj[i]) << 16) | 811 ((psb_intel_crtc->lut_g[i] + 812 psb_intel_crtc->lut_adj[i]) << 8) | 813 (psb_intel_crtc->lut_b[i] + 814 psb_intel_crtc->lut_adj[i]); 815 } 816 817 } 818 } 819 820 /** 821 * Save HW states of giving crtc 822 */ 823 static void psb_intel_crtc_save(struct drm_crtc *crtc) 824 { 825 struct drm_device *dev = crtc->dev; 826 struct drm_psb_private *dev_priv = dev->dev_private; 827 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 828 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 829 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; 830 uint32_t paletteReg; 831 int i; 832 833 if (!crtc_state) { 834 dev_err(dev->dev, "No CRTC state found\n"); 835 return; 836 } 837 838 crtc_state->saveDSPCNTR = REG_READ(map->cntr); 839 crtc_state->savePIPECONF = REG_READ(map->conf); 840 crtc_state->savePIPESRC = REG_READ(map->src); 841 crtc_state->saveFP0 = REG_READ(map->fp0); 842 crtc_state->saveFP1 = REG_READ(map->fp1); 843 crtc_state->saveDPLL = REG_READ(map->dpll); 844 crtc_state->saveHTOTAL = REG_READ(map->htotal); 845 crtc_state->saveHBLANK = REG_READ(map->hblank); 846 crtc_state->saveHSYNC = REG_READ(map->hsync); 847 crtc_state->saveVTOTAL = REG_READ(map->vtotal); 848 crtc_state->saveVBLANK = REG_READ(map->vblank); 849 crtc_state->saveVSYNC = REG_READ(map->vsync); 850 crtc_state->saveDSPSTRIDE = REG_READ(map->stride); 851 852 /*NOTE: DSPSIZE DSPPOS only for psb*/ 853 crtc_state->saveDSPSIZE = REG_READ(map->size); 854 crtc_state->saveDSPPOS = REG_READ(map->pos); 855 856 crtc_state->saveDSPBASE = REG_READ(map->base); 857 858 paletteReg = map->palette; 859 for (i = 0; i < 256; ++i) 860 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); 861 } 862 863 /** 864 * Restore HW states of giving crtc 865 */ 866 static void psb_intel_crtc_restore(struct drm_crtc *crtc) 867 { 868 struct drm_device *dev = crtc->dev; 869 struct drm_psb_private *dev_priv = dev->dev_private; 870 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 871 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 872 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; 873 uint32_t paletteReg; 874 int i; 875 876 if (!crtc_state) { 877 dev_err(dev->dev, "No crtc state\n"); 878 return; 879 } 880 881 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { 882 REG_WRITE(map->dpll, 883 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); 884 REG_READ(map->dpll); 885 udelay(150); 886 } 887 888 REG_WRITE(map->fp0, crtc_state->saveFP0); 889 REG_READ(map->fp0); 890 891 REG_WRITE(map->fp1, crtc_state->saveFP1); 892 REG_READ(map->fp1); 893 894 REG_WRITE(map->dpll, crtc_state->saveDPLL); 895 REG_READ(map->dpll); 896 udelay(150); 897 898 REG_WRITE(map->htotal, crtc_state->saveHTOTAL); 899 REG_WRITE(map->hblank, crtc_state->saveHBLANK); 900 REG_WRITE(map->hsync, crtc_state->saveHSYNC); 901 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); 902 REG_WRITE(map->vblank, crtc_state->saveVBLANK); 903 REG_WRITE(map->vsync, crtc_state->saveVSYNC); 904 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); 905 906 REG_WRITE(map->size, crtc_state->saveDSPSIZE); 907 REG_WRITE(map->pos, crtc_state->saveDSPPOS); 908 909 REG_WRITE(map->src, crtc_state->savePIPESRC); 910 REG_WRITE(map->base, crtc_state->saveDSPBASE); 911 REG_WRITE(map->conf, crtc_state->savePIPECONF); 912 913 psb_intel_wait_for_vblank(dev); 914 915 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); 916 REG_WRITE(map->base, crtc_state->saveDSPBASE); 917 918 psb_intel_wait_for_vblank(dev); 919 920 paletteReg = map->palette; 921 for (i = 0; i < 256; ++i) 922 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); 923 } 924 925 static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc, 926 struct drm_file *file_priv, 927 uint32_t handle, 928 uint32_t width, uint32_t height) 929 { 930 struct drm_device *dev = crtc->dev; 931 struct drm_psb_private *dev_priv = dev->dev_private; 932 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 933 int pipe = psb_intel_crtc->pipe; 934 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; 935 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; 936 uint32_t temp; 937 size_t addr = 0; 938 struct gtt_range *gt; 939 struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt; 940 struct drm_gem_object *obj; 941 void *tmp_dst, *tmp_src; 942 int ret, i, cursor_pages; 943 944 /* if we want to turn of the cursor ignore width and height */ 945 if (!handle) { 946 /* turn off the cursor */ 947 temp = CURSOR_MODE_DISABLE; 948 949 if (gma_power_begin(dev, false)) { 950 REG_WRITE(control, temp); 951 REG_WRITE(base, 0); 952 gma_power_end(dev); 953 } 954 955 /* Unpin the old GEM object */ 956 if (psb_intel_crtc->cursor_obj) { 957 gt = container_of(psb_intel_crtc->cursor_obj, 958 struct gtt_range, gem); 959 psb_gtt_unpin(gt); 960 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 961 psb_intel_crtc->cursor_obj = NULL; 962 } 963 964 return 0; 965 } 966 967 /* Currently we only support 64x64 cursors */ 968 if (width != 64 || height != 64) { 969 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); 970 return -EINVAL; 971 } 972 973 obj = drm_gem_object_lookup(dev, file_priv, handle); 974 if (!obj) 975 return -ENOENT; 976 977 if (obj->size < width * height * 4) { 978 dev_dbg(dev->dev, "buffer is to small\n"); 979 return -ENOMEM; 980 } 981 982 gt = container_of(obj, struct gtt_range, gem); 983 984 /* Pin the memory into the GTT */ 985 ret = psb_gtt_pin(gt); 986 if (ret) { 987 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); 988 return ret; 989 } 990 991 if (dev_priv->ops->cursor_needs_phys) { 992 if (cursor_gt == NULL) { 993 dev_err(dev->dev, "No hardware cursor mem available"); 994 return -ENOMEM; 995 } 996 997 /* Prevent overflow */ 998 if (gt->npage > 4) 999 cursor_pages = 4; 1000 else 1001 cursor_pages = gt->npage; 1002 1003 /* Copy the cursor to cursor mem */ 1004 tmp_dst = dev_priv->vram_addr + cursor_gt->offset; 1005 for (i = 0; i < cursor_pages; i++) { 1006 tmp_src = kmap(gt->pages[i]); 1007 memcpy(tmp_dst, tmp_src, PAGE_SIZE); 1008 kunmap(gt->pages[i]); 1009 tmp_dst += PAGE_SIZE; 1010 } 1011 1012 addr = psb_intel_crtc->cursor_addr; 1013 } else { 1014 addr = gt->offset; /* Or resource.start ??? */ 1015 psb_intel_crtc->cursor_addr = addr; 1016 } 1017 1018 temp = 0; 1019 /* set the pipe for the cursor */ 1020 temp |= (pipe << 28); 1021 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 1022 1023 if (gma_power_begin(dev, false)) { 1024 REG_WRITE(control, temp); 1025 REG_WRITE(base, addr); 1026 gma_power_end(dev); 1027 } 1028 1029 /* unpin the old bo */ 1030 if (psb_intel_crtc->cursor_obj) { 1031 gt = container_of(psb_intel_crtc->cursor_obj, 1032 struct gtt_range, gem); 1033 psb_gtt_unpin(gt); 1034 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1035 psb_intel_crtc->cursor_obj = obj; 1036 } 1037 return 0; 1038 } 1039 1040 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1041 { 1042 struct drm_device *dev = crtc->dev; 1043 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1044 int pipe = psb_intel_crtc->pipe; 1045 uint32_t temp = 0; 1046 uint32_t addr; 1047 1048 1049 if (x < 0) { 1050 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 1051 x = -x; 1052 } 1053 if (y < 0) { 1054 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 1055 y = -y; 1056 } 1057 1058 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 1059 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 1060 1061 addr = psb_intel_crtc->cursor_addr; 1062 1063 if (gma_power_begin(dev, false)) { 1064 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 1065 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); 1066 gma_power_end(dev); 1067 } 1068 return 0; 1069 } 1070 1071 void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, 1072 u16 *green, u16 *blue, uint32_t type, uint32_t size) 1073 { 1074 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1075 int i; 1076 1077 if (size != 256) 1078 return; 1079 1080 for (i = 0; i < 256; i++) { 1081 psb_intel_crtc->lut_r[i] = red[i] >> 8; 1082 psb_intel_crtc->lut_g[i] = green[i] >> 8; 1083 psb_intel_crtc->lut_b[i] = blue[i] >> 8; 1084 } 1085 1086 psb_intel_crtc_load_lut(crtc); 1087 } 1088 1089 static int psb_crtc_set_config(struct drm_mode_set *set) 1090 { 1091 int ret; 1092 struct drm_device *dev = set->crtc->dev; 1093 struct drm_psb_private *dev_priv = dev->dev_private; 1094 1095 if (!dev_priv->rpm_enabled) 1096 return drm_crtc_helper_set_config(set); 1097 1098 pm_runtime_forbid(&dev->pdev->dev); 1099 ret = drm_crtc_helper_set_config(set); 1100 pm_runtime_allow(&dev->pdev->dev); 1101 return ret; 1102 } 1103 1104 /* Returns the clock of the currently programmed mode of the given pipe. */ 1105 static int psb_intel_crtc_clock_get(struct drm_device *dev, 1106 struct drm_crtc *crtc) 1107 { 1108 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1109 struct drm_psb_private *dev_priv = dev->dev_private; 1110 int pipe = psb_intel_crtc->pipe; 1111 const struct psb_offset *map = &dev_priv->regmap[pipe]; 1112 u32 dpll; 1113 u32 fp; 1114 struct psb_intel_clock_t clock; 1115 bool is_lvds; 1116 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 1117 1118 if (gma_power_begin(dev, false)) { 1119 dpll = REG_READ(map->dpll); 1120 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1121 fp = REG_READ(map->fp0); 1122 else 1123 fp = REG_READ(map->fp1); 1124 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 1125 gma_power_end(dev); 1126 } else { 1127 dpll = p->dpll; 1128 1129 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1130 fp = p->fp0; 1131 else 1132 fp = p->fp1; 1133 1134 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 1135 LVDS_PORT_EN); 1136 } 1137 1138 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1139 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 1140 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 1141 1142 if (is_lvds) { 1143 clock.p1 = 1144 ffs((dpll & 1145 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 1146 DPLL_FPA01_P1_POST_DIV_SHIFT); 1147 clock.p2 = 14; 1148 1149 if ((dpll & PLL_REF_INPUT_MASK) == 1150 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 1151 /* XXX: might not be 66MHz */ 1152 i8xx_clock(66000, &clock); 1153 } else 1154 i8xx_clock(48000, &clock); 1155 } else { 1156 if (dpll & PLL_P1_DIVIDE_BY_TWO) 1157 clock.p1 = 2; 1158 else { 1159 clock.p1 = 1160 ((dpll & 1161 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 1162 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 1163 } 1164 if (dpll & PLL_P2_DIVIDE_BY_4) 1165 clock.p2 = 4; 1166 else 1167 clock.p2 = 2; 1168 1169 i8xx_clock(48000, &clock); 1170 } 1171 1172 /* XXX: It would be nice to validate the clocks, but we can't reuse 1173 * i830PllIsValid() because it relies on the xf86_config connector 1174 * configuration being accurate, which it isn't necessarily. 1175 */ 1176 1177 return clock.dot; 1178 } 1179 1180 /** Returns the currently programmed mode of the given pipe. */ 1181 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 1182 struct drm_crtc *crtc) 1183 { 1184 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1185 int pipe = psb_intel_crtc->pipe; 1186 struct drm_display_mode *mode; 1187 int htot; 1188 int hsync; 1189 int vtot; 1190 int vsync; 1191 struct drm_psb_private *dev_priv = dev->dev_private; 1192 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 1193 const struct psb_offset *map = &dev_priv->regmap[pipe]; 1194 1195 if (gma_power_begin(dev, false)) { 1196 htot = REG_READ(map->htotal); 1197 hsync = REG_READ(map->hsync); 1198 vtot = REG_READ(map->vtotal); 1199 vsync = REG_READ(map->vsync); 1200 gma_power_end(dev); 1201 } else { 1202 htot = p->htotal; 1203 hsync = p->hsync; 1204 vtot = p->vtotal; 1205 vsync = p->vsync; 1206 } 1207 1208 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1209 if (!mode) 1210 return NULL; 1211 1212 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 1213 mode->hdisplay = (htot & 0xffff) + 1; 1214 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 1215 mode->hsync_start = (hsync & 0xffff) + 1; 1216 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 1217 mode->vdisplay = (vtot & 0xffff) + 1; 1218 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 1219 mode->vsync_start = (vsync & 0xffff) + 1; 1220 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 1221 1222 drm_mode_set_name(mode); 1223 drm_mode_set_crtcinfo(mode, 0); 1224 1225 return mode; 1226 } 1227 1228 void psb_intel_crtc_destroy(struct drm_crtc *crtc) 1229 { 1230 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1231 struct gtt_range *gt; 1232 1233 /* Unpin the old GEM object */ 1234 if (psb_intel_crtc->cursor_obj) { 1235 gt = container_of(psb_intel_crtc->cursor_obj, 1236 struct gtt_range, gem); 1237 psb_gtt_unpin(gt); 1238 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1239 psb_intel_crtc->cursor_obj = NULL; 1240 } 1241 1242 if (psb_intel_crtc->cursor_gt != NULL) 1243 psb_gtt_free_range(crtc->dev, psb_intel_crtc->cursor_gt); 1244 kfree(psb_intel_crtc->crtc_state); 1245 drm_crtc_cleanup(crtc); 1246 kfree(psb_intel_crtc); 1247 } 1248 1249 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 1250 .dpms = psb_intel_crtc_dpms, 1251 .mode_fixup = psb_intel_crtc_mode_fixup, 1252 .mode_set = psb_intel_crtc_mode_set, 1253 .mode_set_base = psb_intel_pipe_set_base, 1254 .prepare = psb_intel_crtc_prepare, 1255 .commit = psb_intel_crtc_commit, 1256 }; 1257 1258 const struct drm_crtc_funcs psb_intel_crtc_funcs = { 1259 .save = psb_intel_crtc_save, 1260 .restore = psb_intel_crtc_restore, 1261 .cursor_set = psb_intel_crtc_cursor_set, 1262 .cursor_move = psb_intel_crtc_cursor_move, 1263 .gamma_set = psb_intel_crtc_gamma_set, 1264 .set_config = psb_crtc_set_config, 1265 .destroy = psb_intel_crtc_destroy, 1266 }; 1267 1268 /* 1269 * Set the default value of cursor control and base register 1270 * to zero. This is a workaround for h/w defect on Oaktrail 1271 */ 1272 static void psb_intel_cursor_init(struct drm_device *dev, 1273 struct psb_intel_crtc *psb_intel_crtc) 1274 { 1275 struct drm_psb_private *dev_priv = dev->dev_private; 1276 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 1277 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 1278 struct gtt_range *cursor_gt; 1279 1280 if (dev_priv->ops->cursor_needs_phys) { 1281 /* Allocate 4 pages of stolen mem for a hardware cursor. That 1282 * is enough for the 64 x 64 ARGB cursors we support. 1283 */ 1284 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1); 1285 if (!cursor_gt) { 1286 psb_intel_crtc->cursor_gt = NULL; 1287 goto out; 1288 } 1289 psb_intel_crtc->cursor_gt = cursor_gt; 1290 psb_intel_crtc->cursor_addr = dev_priv->stolen_base + 1291 cursor_gt->offset; 1292 } else { 1293 psb_intel_crtc->cursor_gt = NULL; 1294 } 1295 1296 out: 1297 REG_WRITE(control[psb_intel_crtc->pipe], 0); 1298 REG_WRITE(base[psb_intel_crtc->pipe], 0); 1299 } 1300 1301 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 1302 struct psb_intel_mode_device *mode_dev) 1303 { 1304 struct drm_psb_private *dev_priv = dev->dev_private; 1305 struct psb_intel_crtc *psb_intel_crtc; 1306 int i; 1307 uint16_t *r_base, *g_base, *b_base; 1308 1309 /* We allocate a extra array of drm_connector pointers 1310 * for fbdev after the crtc */ 1311 psb_intel_crtc = 1312 kzalloc(sizeof(struct psb_intel_crtc) + 1313 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 1314 GFP_KERNEL); 1315 if (psb_intel_crtc == NULL) 1316 return; 1317 1318 psb_intel_crtc->crtc_state = 1319 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 1320 if (!psb_intel_crtc->crtc_state) { 1321 dev_err(dev->dev, "Crtc state error: No memory\n"); 1322 kfree(psb_intel_crtc); 1323 return; 1324 } 1325 1326 /* Set the CRTC operations from the chip specific data */ 1327 drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs); 1328 1329 drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256); 1330 psb_intel_crtc->pipe = pipe; 1331 psb_intel_crtc->plane = pipe; 1332 1333 r_base = psb_intel_crtc->base.gamma_store; 1334 g_base = r_base + 256; 1335 b_base = g_base + 256; 1336 for (i = 0; i < 256; i++) { 1337 psb_intel_crtc->lut_r[i] = i; 1338 psb_intel_crtc->lut_g[i] = i; 1339 psb_intel_crtc->lut_b[i] = i; 1340 r_base[i] = i << 8; 1341 g_base[i] = i << 8; 1342 b_base[i] = i << 8; 1343 1344 psb_intel_crtc->lut_adj[i] = 0; 1345 } 1346 1347 psb_intel_crtc->mode_dev = mode_dev; 1348 psb_intel_crtc->cursor_addr = 0; 1349 1350 drm_crtc_helper_add(&psb_intel_crtc->base, 1351 dev_priv->ops->crtc_helper); 1352 1353 /* Setup the array of drm_connector pointer array */ 1354 psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base; 1355 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 1356 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL); 1357 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] = 1358 &psb_intel_crtc->base; 1359 dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] = 1360 &psb_intel_crtc->base; 1361 psb_intel_crtc->mode_set.connectors = 1362 (struct drm_connector **) (psb_intel_crtc + 1); 1363 psb_intel_crtc->mode_set.num_connectors = 0; 1364 psb_intel_cursor_init(dev, psb_intel_crtc); 1365 } 1366 1367 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 1368 struct drm_file *file_priv) 1369 { 1370 struct drm_psb_private *dev_priv = dev->dev_private; 1371 struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data; 1372 struct drm_mode_object *drmmode_obj; 1373 struct psb_intel_crtc *crtc; 1374 1375 if (!dev_priv) { 1376 dev_err(dev->dev, "called with no initialization\n"); 1377 return -EINVAL; 1378 } 1379 1380 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 1381 DRM_MODE_OBJECT_CRTC); 1382 1383 if (!drmmode_obj) { 1384 dev_err(dev->dev, "no such CRTC id\n"); 1385 return -EINVAL; 1386 } 1387 1388 crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj)); 1389 pipe_from_crtc_id->pipe = crtc->pipe; 1390 1391 return 0; 1392 } 1393 1394 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 1395 { 1396 struct drm_crtc *crtc = NULL; 1397 1398 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1399 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1400 if (psb_intel_crtc->pipe == pipe) 1401 break; 1402 } 1403 return crtc; 1404 } 1405 1406 int psb_intel_connector_clones(struct drm_device *dev, int type_mask) 1407 { 1408 int index_mask = 0; 1409 struct drm_connector *connector; 1410 int entry = 0; 1411 1412 list_for_each_entry(connector, &dev->mode_config.connector_list, 1413 head) { 1414 struct psb_intel_encoder *psb_intel_encoder = 1415 psb_intel_attached_encoder(connector); 1416 if (type_mask & (1 << psb_intel_encoder->type)) 1417 index_mask |= (1 << entry); 1418 entry++; 1419 } 1420 return index_mask; 1421 } 1422 1423 /* current intel driver doesn't take advantage of encoders 1424 always give back the encoder for the connector 1425 */ 1426 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector) 1427 { 1428 struct psb_intel_encoder *psb_intel_encoder = 1429 psb_intel_attached_encoder(connector); 1430 1431 return &psb_intel_encoder->base; 1432 } 1433 1434 void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector, 1435 struct psb_intel_encoder *encoder) 1436 { 1437 connector->encoder = encoder; 1438 drm_mode_connector_attach_encoder(&connector->base, 1439 &encoder->base); 1440 } 1441