1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21 #include <linux/i2c.h> 22 #include <linux/pm_runtime.h> 23 24 #include <drm/drmP.h> 25 #include "framebuffer.h" 26 #include "psb_drv.h" 27 #include "psb_intel_drv.h" 28 #include "psb_intel_reg.h" 29 #include "psb_intel_display.h" 30 #include "power.h" 31 32 struct psb_intel_clock_t { 33 /* given values */ 34 int n; 35 int m1, m2; 36 int p1, p2; 37 /* derived values */ 38 int dot; 39 int vco; 40 int m; 41 int p; 42 }; 43 44 struct psb_intel_range_t { 45 int min, max; 46 }; 47 48 struct psb_intel_p2_t { 49 int dot_limit; 50 int p2_slow, p2_fast; 51 }; 52 53 struct psb_intel_limit_t { 54 struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1; 55 struct psb_intel_p2_t p2; 56 }; 57 58 #define INTEL_LIMIT_I9XX_SDVO_DAC 0 59 #define INTEL_LIMIT_I9XX_LVDS 1 60 61 static const struct psb_intel_limit_t psb_intel_limits[] = { 62 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 63 .dot = {.min = 20000, .max = 400000}, 64 .vco = {.min = 1400000, .max = 2800000}, 65 .n = {.min = 1, .max = 6}, 66 .m = {.min = 70, .max = 120}, 67 .m1 = {.min = 8, .max = 18}, 68 .m2 = {.min = 3, .max = 7}, 69 .p = {.min = 5, .max = 80}, 70 .p1 = {.min = 1, .max = 8}, 71 .p2 = {.dot_limit = 200000, 72 .p2_slow = 10, .p2_fast = 5}, 73 }, 74 { /* INTEL_LIMIT_I9XX_LVDS */ 75 .dot = {.min = 20000, .max = 400000}, 76 .vco = {.min = 1400000, .max = 2800000}, 77 .n = {.min = 1, .max = 6}, 78 .m = {.min = 70, .max = 120}, 79 .m1 = {.min = 8, .max = 18}, 80 .m2 = {.min = 3, .max = 7}, 81 .p = {.min = 7, .max = 98}, 82 .p1 = {.min = 1, .max = 8}, 83 /* The single-channel range is 25-112Mhz, and dual-channel 84 * is 80-224Mhz. Prefer single channel as much as possible. 85 */ 86 .p2 = {.dot_limit = 112000, 87 .p2_slow = 14, .p2_fast = 7}, 88 }, 89 }; 90 91 static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc) 92 { 93 const struct psb_intel_limit_t *limit; 94 95 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 96 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 97 else 98 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 99 return limit; 100 } 101 102 static void psb_intel_clock(int refclk, struct psb_intel_clock_t *clock) 103 { 104 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 105 clock->p = clock->p1 * clock->p2; 106 clock->vco = refclk * clock->m / (clock->n + 2); 107 clock->dot = clock->vco / clock->p; 108 } 109 110 /** 111 * Returns whether any output on the specified pipe is of the specified type 112 */ 113 bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type) 114 { 115 struct drm_device *dev = crtc->dev; 116 struct drm_mode_config *mode_config = &dev->mode_config; 117 struct drm_connector *l_entry; 118 119 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 120 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { 121 struct psb_intel_encoder *psb_intel_encoder = 122 psb_intel_attached_encoder(l_entry); 123 if (psb_intel_encoder->type == type) 124 return true; 125 } 126 } 127 return false; 128 } 129 130 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } 131 /** 132 * Returns whether the given set of divisors are valid for a given refclk with 133 * the given connectors. 134 */ 135 136 static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc, 137 struct psb_intel_clock_t *clock) 138 { 139 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); 140 141 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 142 INTELPllInvalid("p1 out of range\n"); 143 if (clock->p < limit->p.min || limit->p.max < clock->p) 144 INTELPllInvalid("p out of range\n"); 145 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 146 INTELPllInvalid("m2 out of range\n"); 147 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 148 INTELPllInvalid("m1 out of range\n"); 149 if (clock->m1 <= clock->m2) 150 INTELPllInvalid("m1 <= m2\n"); 151 if (clock->m < limit->m.min || limit->m.max < clock->m) 152 INTELPllInvalid("m out of range\n"); 153 if (clock->n < limit->n.min || limit->n.max < clock->n) 154 INTELPllInvalid("n out of range\n"); 155 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 156 INTELPllInvalid("vco out of range\n"); 157 /* XXX: We may need to be checking "Dot clock" 158 * depending on the multiplier, connector, etc., 159 * rather than just a single range. 160 */ 161 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 162 INTELPllInvalid("dot out of range\n"); 163 164 return true; 165 } 166 167 /** 168 * Returns a set of divisors for the desired target clock with the given 169 * refclk, or FALSE. The returned values represent the clock equation: 170 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 171 */ 172 static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target, 173 int refclk, 174 struct psb_intel_clock_t *best_clock) 175 { 176 struct drm_device *dev = crtc->dev; 177 struct psb_intel_clock_t clock; 178 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc); 179 int err = target; 180 181 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 182 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { 183 /* 184 * For LVDS, if the panel is on, just rely on its current 185 * settings for dual-channel. We haven't figured out how to 186 * reliably set up different single/dual channel state, if we 187 * even can. 188 */ 189 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 190 LVDS_CLKB_POWER_UP) 191 clock.p2 = limit->p2.p2_fast; 192 else 193 clock.p2 = limit->p2.p2_slow; 194 } else { 195 if (target < limit->p2.dot_limit) 196 clock.p2 = limit->p2.p2_slow; 197 else 198 clock.p2 = limit->p2.p2_fast; 199 } 200 201 memset(best_clock, 0, sizeof(*best_clock)); 202 203 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 204 clock.m1++) { 205 for (clock.m2 = limit->m2.min; 206 clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; 207 clock.m2++) { 208 for (clock.n = limit->n.min; 209 clock.n <= limit->n.max; clock.n++) { 210 for (clock.p1 = limit->p1.min; 211 clock.p1 <= limit->p1.max; 212 clock.p1++) { 213 int this_err; 214 215 psb_intel_clock(refclk, &clock); 216 217 if (!psb_intel_PLL_is_valid 218 (crtc, &clock)) 219 continue; 220 221 this_err = abs(clock.dot - target); 222 if (this_err < err) { 223 *best_clock = clock; 224 err = this_err; 225 } 226 } 227 } 228 } 229 } 230 231 return err != target; 232 } 233 234 void psb_intel_wait_for_vblank(struct drm_device *dev) 235 { 236 /* Wait for 20ms, i.e. one cycle at 50hz. */ 237 mdelay(20); 238 } 239 240 static int psb_intel_pipe_set_base(struct drm_crtc *crtc, 241 int x, int y, struct drm_framebuffer *old_fb) 242 { 243 struct drm_device *dev = crtc->dev; 244 struct drm_psb_private *dev_priv = dev->dev_private; 245 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 246 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); 247 int pipe = psb_intel_crtc->pipe; 248 const struct psb_offset *map = &dev_priv->regmap[pipe]; 249 unsigned long start, offset; 250 u32 dspcntr; 251 int ret = 0; 252 253 if (!gma_power_begin(dev, true)) 254 return 0; 255 256 /* no fb bound */ 257 if (!crtc->fb) { 258 dev_dbg(dev->dev, "No FB bound\n"); 259 goto psb_intel_pipe_cleaner; 260 } 261 262 /* We are displaying this buffer, make sure it is actually loaded 263 into the GTT */ 264 ret = psb_gtt_pin(psbfb->gtt); 265 if (ret < 0) 266 goto psb_intel_pipe_set_base_exit; 267 start = psbfb->gtt->offset; 268 269 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8); 270 271 REG_WRITE(map->stride, crtc->fb->pitches[0]); 272 273 dspcntr = REG_READ(map->cntr); 274 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 275 276 switch (crtc->fb->bits_per_pixel) { 277 case 8: 278 dspcntr |= DISPPLANE_8BPP; 279 break; 280 case 16: 281 if (crtc->fb->depth == 15) 282 dspcntr |= DISPPLANE_15_16BPP; 283 else 284 dspcntr |= DISPPLANE_16BPP; 285 break; 286 case 24: 287 case 32: 288 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 289 break; 290 default: 291 dev_err(dev->dev, "Unknown color depth\n"); 292 ret = -EINVAL; 293 psb_gtt_unpin(psbfb->gtt); 294 goto psb_intel_pipe_set_base_exit; 295 } 296 REG_WRITE(map->cntr, dspcntr); 297 298 REG_WRITE(map->base, start + offset); 299 REG_READ(map->base); 300 301 psb_intel_pipe_cleaner: 302 /* If there was a previous display we can now unpin it */ 303 if (old_fb) 304 psb_gtt_unpin(to_psb_fb(old_fb)->gtt); 305 306 psb_intel_pipe_set_base_exit: 307 gma_power_end(dev); 308 return ret; 309 } 310 311 /** 312 * Sets the power management mode of the pipe and plane. 313 * 314 * This code should probably grow support for turning the cursor off and back 315 * on appropriately at the same time as we're turning the pipe off/on. 316 */ 317 static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode) 318 { 319 struct drm_device *dev = crtc->dev; 320 struct drm_psb_private *dev_priv = dev->dev_private; 321 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 322 int pipe = psb_intel_crtc->pipe; 323 const struct psb_offset *map = &dev_priv->regmap[pipe]; 324 u32 temp; 325 326 /* XXX: When our outputs are all unaware of DPMS modes other than off 327 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 328 */ 329 switch (mode) { 330 case DRM_MODE_DPMS_ON: 331 case DRM_MODE_DPMS_STANDBY: 332 case DRM_MODE_DPMS_SUSPEND: 333 /* Enable the DPLL */ 334 temp = REG_READ(map->dpll); 335 if ((temp & DPLL_VCO_ENABLE) == 0) { 336 REG_WRITE(map->dpll, temp); 337 REG_READ(map->dpll); 338 /* Wait for the clocks to stabilize. */ 339 udelay(150); 340 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 341 REG_READ(map->dpll); 342 /* Wait for the clocks to stabilize. */ 343 udelay(150); 344 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 345 REG_READ(map->dpll); 346 /* Wait for the clocks to stabilize. */ 347 udelay(150); 348 } 349 350 /* Enable the pipe */ 351 temp = REG_READ(map->conf); 352 if ((temp & PIPEACONF_ENABLE) == 0) 353 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); 354 355 /* Enable the plane */ 356 temp = REG_READ(map->cntr); 357 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 358 REG_WRITE(map->cntr, 359 temp | DISPLAY_PLANE_ENABLE); 360 /* Flush the plane changes */ 361 REG_WRITE(map->base, REG_READ(map->base)); 362 } 363 364 psb_intel_crtc_load_lut(crtc); 365 366 /* Give the overlay scaler a chance to enable 367 * if it's on this pipe */ 368 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 369 break; 370 case DRM_MODE_DPMS_OFF: 371 /* Give the overlay scaler a chance to disable 372 * if it's on this pipe */ 373 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 374 375 /* Disable the VGA plane that we never use */ 376 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 377 378 /* Disable display plane */ 379 temp = REG_READ(map->cntr); 380 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 381 REG_WRITE(map->cntr, 382 temp & ~DISPLAY_PLANE_ENABLE); 383 /* Flush the plane changes */ 384 REG_WRITE(map->base, REG_READ(map->base)); 385 REG_READ(map->base); 386 } 387 388 /* Next, disable display pipes */ 389 temp = REG_READ(map->conf); 390 if ((temp & PIPEACONF_ENABLE) != 0) { 391 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); 392 REG_READ(map->conf); 393 } 394 395 /* Wait for vblank for the disable to take effect. */ 396 psb_intel_wait_for_vblank(dev); 397 398 temp = REG_READ(map->dpll); 399 if ((temp & DPLL_VCO_ENABLE) != 0) { 400 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); 401 REG_READ(map->dpll); 402 } 403 404 /* Wait for the clocks to turn off. */ 405 udelay(150); 406 break; 407 } 408 409 /*Set FIFO Watermarks*/ 410 REG_WRITE(DSPARB, 0x3F3E); 411 } 412 413 static void psb_intel_crtc_prepare(struct drm_crtc *crtc) 414 { 415 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 416 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 417 } 418 419 static void psb_intel_crtc_commit(struct drm_crtc *crtc) 420 { 421 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 422 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 423 } 424 425 void psb_intel_encoder_prepare(struct drm_encoder *encoder) 426 { 427 struct drm_encoder_helper_funcs *encoder_funcs = 428 encoder->helper_private; 429 /* lvds has its own version of prepare see psb_intel_lvds_prepare */ 430 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 431 } 432 433 void psb_intel_encoder_commit(struct drm_encoder *encoder) 434 { 435 struct drm_encoder_helper_funcs *encoder_funcs = 436 encoder->helper_private; 437 /* lvds has its own version of commit see psb_intel_lvds_commit */ 438 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 439 } 440 441 void psb_intel_encoder_destroy(struct drm_encoder *encoder) 442 { 443 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder); 444 445 drm_encoder_cleanup(encoder); 446 kfree(intel_encoder); 447 } 448 449 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc, 450 const struct drm_display_mode *mode, 451 struct drm_display_mode *adjusted_mode) 452 { 453 return true; 454 } 455 456 457 /** 458 * Return the pipe currently connected to the panel fitter, 459 * or -1 if the panel fitter is not present or not in use 460 */ 461 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 462 { 463 u32 pfit_control; 464 465 pfit_control = REG_READ(PFIT_CONTROL); 466 467 /* See if the panel fitter is in use */ 468 if ((pfit_control & PFIT_ENABLE) == 0) 469 return -1; 470 /* Must be on PIPE 1 for PSB */ 471 return 1; 472 } 473 474 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 475 struct drm_display_mode *mode, 476 struct drm_display_mode *adjusted_mode, 477 int x, int y, 478 struct drm_framebuffer *old_fb) 479 { 480 struct drm_device *dev = crtc->dev; 481 struct drm_psb_private *dev_priv = dev->dev_private; 482 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 483 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 484 int pipe = psb_intel_crtc->pipe; 485 const struct psb_offset *map = &dev_priv->regmap[pipe]; 486 int refclk; 487 struct psb_intel_clock_t clock; 488 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 489 bool ok, is_sdvo = false; 490 bool is_lvds = false, is_tv = false; 491 struct drm_mode_config *mode_config = &dev->mode_config; 492 struct drm_connector *connector; 493 494 /* No scan out no play */ 495 if (crtc->fb == NULL) { 496 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 497 return 0; 498 } 499 500 list_for_each_entry(connector, &mode_config->connector_list, head) { 501 struct psb_intel_encoder *psb_intel_encoder = 502 psb_intel_attached_encoder(connector); 503 504 if (!connector->encoder 505 || connector->encoder->crtc != crtc) 506 continue; 507 508 switch (psb_intel_encoder->type) { 509 case INTEL_OUTPUT_LVDS: 510 is_lvds = true; 511 break; 512 case INTEL_OUTPUT_SDVO: 513 is_sdvo = true; 514 break; 515 case INTEL_OUTPUT_TVOUT: 516 is_tv = true; 517 break; 518 } 519 } 520 521 refclk = 96000; 522 523 ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, 524 &clock); 525 if (!ok) { 526 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n"); 527 return 0; 528 } 529 530 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 531 532 dpll = DPLL_VGA_MODE_DIS; 533 if (is_lvds) { 534 dpll |= DPLLB_MODE_LVDS; 535 dpll |= DPLL_DVO_HIGH_SPEED; 536 } else 537 dpll |= DPLLB_MODE_DAC_SERIAL; 538 if (is_sdvo) { 539 int sdvo_pixel_multiply = 540 adjusted_mode->clock / mode->clock; 541 dpll |= DPLL_DVO_HIGH_SPEED; 542 dpll |= 543 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 544 } 545 546 /* compute bitmask from p1 value */ 547 dpll |= (1 << (clock.p1 - 1)) << 16; 548 switch (clock.p2) { 549 case 5: 550 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 551 break; 552 case 7: 553 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 554 break; 555 case 10: 556 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 557 break; 558 case 14: 559 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 560 break; 561 } 562 563 if (is_tv) { 564 /* XXX: just matching BIOS for now */ 565 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 566 dpll |= 3; 567 } 568 dpll |= PLL_REF_INPUT_DREFCLK; 569 570 /* setup pipeconf */ 571 pipeconf = REG_READ(map->conf); 572 573 /* Set up the display plane register */ 574 dspcntr = DISPPLANE_GAMMA_ENABLE; 575 576 if (pipe == 0) 577 dspcntr |= DISPPLANE_SEL_PIPE_A; 578 else 579 dspcntr |= DISPPLANE_SEL_PIPE_B; 580 581 dspcntr |= DISPLAY_PLANE_ENABLE; 582 pipeconf |= PIPEACONF_ENABLE; 583 dpll |= DPLL_VCO_ENABLE; 584 585 586 /* Disable the panel fitter if it was on our pipe */ 587 if (psb_intel_panel_fitter_pipe(dev) == pipe) 588 REG_WRITE(PFIT_CONTROL, 0); 589 590 drm_mode_debug_printmodeline(mode); 591 592 if (dpll & DPLL_VCO_ENABLE) { 593 REG_WRITE(map->fp0, fp); 594 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 595 REG_READ(map->dpll); 596 udelay(150); 597 } 598 599 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 600 * This is an exception to the general rule that mode_set doesn't turn 601 * things on. 602 */ 603 if (is_lvds) { 604 u32 lvds = REG_READ(LVDS); 605 606 lvds &= ~LVDS_PIPEB_SELECT; 607 if (pipe == 1) 608 lvds |= LVDS_PIPEB_SELECT; 609 610 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 611 /* Set the B0-B3 data pairs corresponding to 612 * whether we're going to 613 * set the DPLLs for dual-channel mode or not. 614 */ 615 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 616 if (clock.p2 == 7) 617 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 618 619 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 620 * appropriately here, but we need to look more 621 * thoroughly into how panels behave in the two modes. 622 */ 623 624 REG_WRITE(LVDS, lvds); 625 REG_READ(LVDS); 626 } 627 628 REG_WRITE(map->fp0, fp); 629 REG_WRITE(map->dpll, dpll); 630 REG_READ(map->dpll); 631 /* Wait for the clocks to stabilize. */ 632 udelay(150); 633 634 /* write it again -- the BIOS does, after all */ 635 REG_WRITE(map->dpll, dpll); 636 637 REG_READ(map->dpll); 638 /* Wait for the clocks to stabilize. */ 639 udelay(150); 640 641 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 642 ((adjusted_mode->crtc_htotal - 1) << 16)); 643 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 644 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 645 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 646 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 647 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 648 ((adjusted_mode->crtc_vtotal - 1) << 16)); 649 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 650 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 651 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 652 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 653 /* pipesrc and dspsize control the size that is scaled from, 654 * which should always be the user's requested size. 655 */ 656 REG_WRITE(map->size, 657 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 658 REG_WRITE(map->pos, 0); 659 REG_WRITE(map->src, 660 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 661 REG_WRITE(map->conf, pipeconf); 662 REG_READ(map->conf); 663 664 psb_intel_wait_for_vblank(dev); 665 666 REG_WRITE(map->cntr, dspcntr); 667 668 /* Flush the plane changes */ 669 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 670 671 psb_intel_wait_for_vblank(dev); 672 673 return 0; 674 } 675 676 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 677 void psb_intel_crtc_load_lut(struct drm_crtc *crtc) 678 { 679 struct drm_device *dev = crtc->dev; 680 struct drm_psb_private *dev_priv = dev->dev_private; 681 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 682 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; 683 int palreg = map->palette; 684 int i; 685 686 /* The clocks have to be on to load the palette. */ 687 if (!crtc->enabled) 688 return; 689 690 switch (psb_intel_crtc->pipe) { 691 case 0: 692 case 1: 693 break; 694 default: 695 dev_err(dev->dev, "Illegal Pipe Number.\n"); 696 return; 697 } 698 699 if (gma_power_begin(dev, false)) { 700 for (i = 0; i < 256; i++) { 701 REG_WRITE(palreg + 4 * i, 702 ((psb_intel_crtc->lut_r[i] + 703 psb_intel_crtc->lut_adj[i]) << 16) | 704 ((psb_intel_crtc->lut_g[i] + 705 psb_intel_crtc->lut_adj[i]) << 8) | 706 (psb_intel_crtc->lut_b[i] + 707 psb_intel_crtc->lut_adj[i])); 708 } 709 gma_power_end(dev); 710 } else { 711 for (i = 0; i < 256; i++) { 712 dev_priv->regs.pipe[0].palette[i] = 713 ((psb_intel_crtc->lut_r[i] + 714 psb_intel_crtc->lut_adj[i]) << 16) | 715 ((psb_intel_crtc->lut_g[i] + 716 psb_intel_crtc->lut_adj[i]) << 8) | 717 (psb_intel_crtc->lut_b[i] + 718 psb_intel_crtc->lut_adj[i]); 719 } 720 721 } 722 } 723 724 /** 725 * Save HW states of giving crtc 726 */ 727 static void psb_intel_crtc_save(struct drm_crtc *crtc) 728 { 729 struct drm_device *dev = crtc->dev; 730 struct drm_psb_private *dev_priv = dev->dev_private; 731 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 732 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 733 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; 734 uint32_t paletteReg; 735 int i; 736 737 if (!crtc_state) { 738 dev_err(dev->dev, "No CRTC state found\n"); 739 return; 740 } 741 742 crtc_state->saveDSPCNTR = REG_READ(map->cntr); 743 crtc_state->savePIPECONF = REG_READ(map->conf); 744 crtc_state->savePIPESRC = REG_READ(map->src); 745 crtc_state->saveFP0 = REG_READ(map->fp0); 746 crtc_state->saveFP1 = REG_READ(map->fp1); 747 crtc_state->saveDPLL = REG_READ(map->dpll); 748 crtc_state->saveHTOTAL = REG_READ(map->htotal); 749 crtc_state->saveHBLANK = REG_READ(map->hblank); 750 crtc_state->saveHSYNC = REG_READ(map->hsync); 751 crtc_state->saveVTOTAL = REG_READ(map->vtotal); 752 crtc_state->saveVBLANK = REG_READ(map->vblank); 753 crtc_state->saveVSYNC = REG_READ(map->vsync); 754 crtc_state->saveDSPSTRIDE = REG_READ(map->stride); 755 756 /*NOTE: DSPSIZE DSPPOS only for psb*/ 757 crtc_state->saveDSPSIZE = REG_READ(map->size); 758 crtc_state->saveDSPPOS = REG_READ(map->pos); 759 760 crtc_state->saveDSPBASE = REG_READ(map->base); 761 762 paletteReg = map->palette; 763 for (i = 0; i < 256; ++i) 764 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2)); 765 } 766 767 /** 768 * Restore HW states of giving crtc 769 */ 770 static void psb_intel_crtc_restore(struct drm_crtc *crtc) 771 { 772 struct drm_device *dev = crtc->dev; 773 struct drm_psb_private *dev_priv = dev->dev_private; 774 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 775 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state; 776 const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe]; 777 uint32_t paletteReg; 778 int i; 779 780 if (!crtc_state) { 781 dev_err(dev->dev, "No crtc state\n"); 782 return; 783 } 784 785 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { 786 REG_WRITE(map->dpll, 787 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); 788 REG_READ(map->dpll); 789 udelay(150); 790 } 791 792 REG_WRITE(map->fp0, crtc_state->saveFP0); 793 REG_READ(map->fp0); 794 795 REG_WRITE(map->fp1, crtc_state->saveFP1); 796 REG_READ(map->fp1); 797 798 REG_WRITE(map->dpll, crtc_state->saveDPLL); 799 REG_READ(map->dpll); 800 udelay(150); 801 802 REG_WRITE(map->htotal, crtc_state->saveHTOTAL); 803 REG_WRITE(map->hblank, crtc_state->saveHBLANK); 804 REG_WRITE(map->hsync, crtc_state->saveHSYNC); 805 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); 806 REG_WRITE(map->vblank, crtc_state->saveVBLANK); 807 REG_WRITE(map->vsync, crtc_state->saveVSYNC); 808 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); 809 810 REG_WRITE(map->size, crtc_state->saveDSPSIZE); 811 REG_WRITE(map->pos, crtc_state->saveDSPPOS); 812 813 REG_WRITE(map->src, crtc_state->savePIPESRC); 814 REG_WRITE(map->base, crtc_state->saveDSPBASE); 815 REG_WRITE(map->conf, crtc_state->savePIPECONF); 816 817 psb_intel_wait_for_vblank(dev); 818 819 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); 820 REG_WRITE(map->base, crtc_state->saveDSPBASE); 821 822 psb_intel_wait_for_vblank(dev); 823 824 paletteReg = map->palette; 825 for (i = 0; i < 256; ++i) 826 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]); 827 } 828 829 static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc, 830 struct drm_file *file_priv, 831 uint32_t handle, 832 uint32_t width, uint32_t height) 833 { 834 struct drm_device *dev = crtc->dev; 835 struct drm_psb_private *dev_priv = dev->dev_private; 836 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 837 int pipe = psb_intel_crtc->pipe; 838 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; 839 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; 840 uint32_t temp; 841 size_t addr = 0; 842 struct gtt_range *gt; 843 struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt; 844 struct drm_gem_object *obj; 845 void *tmp_dst, *tmp_src; 846 int ret = 0, i, cursor_pages; 847 848 /* if we want to turn of the cursor ignore width and height */ 849 if (!handle) { 850 /* turn off the cursor */ 851 temp = CURSOR_MODE_DISABLE; 852 853 if (gma_power_begin(dev, false)) { 854 REG_WRITE(control, temp); 855 REG_WRITE(base, 0); 856 gma_power_end(dev); 857 } 858 859 /* Unpin the old GEM object */ 860 if (psb_intel_crtc->cursor_obj) { 861 gt = container_of(psb_intel_crtc->cursor_obj, 862 struct gtt_range, gem); 863 psb_gtt_unpin(gt); 864 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 865 psb_intel_crtc->cursor_obj = NULL; 866 } 867 868 return 0; 869 } 870 871 /* Currently we only support 64x64 cursors */ 872 if (width != 64 || height != 64) { 873 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n"); 874 return -EINVAL; 875 } 876 877 obj = drm_gem_object_lookup(dev, file_priv, handle); 878 if (!obj) 879 return -ENOENT; 880 881 if (obj->size < width * height * 4) { 882 dev_dbg(dev->dev, "buffer is to small\n"); 883 ret = -ENOMEM; 884 goto unref_cursor; 885 } 886 887 gt = container_of(obj, struct gtt_range, gem); 888 889 /* Pin the memory into the GTT */ 890 ret = psb_gtt_pin(gt); 891 if (ret) { 892 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); 893 goto unref_cursor; 894 } 895 896 if (dev_priv->ops->cursor_needs_phys) { 897 if (cursor_gt == NULL) { 898 dev_err(dev->dev, "No hardware cursor mem available"); 899 ret = -ENOMEM; 900 goto unref_cursor; 901 } 902 903 /* Prevent overflow */ 904 if (gt->npage > 4) 905 cursor_pages = 4; 906 else 907 cursor_pages = gt->npage; 908 909 /* Copy the cursor to cursor mem */ 910 tmp_dst = dev_priv->vram_addr + cursor_gt->offset; 911 for (i = 0; i < cursor_pages; i++) { 912 tmp_src = kmap(gt->pages[i]); 913 memcpy(tmp_dst, tmp_src, PAGE_SIZE); 914 kunmap(gt->pages[i]); 915 tmp_dst += PAGE_SIZE; 916 } 917 918 addr = psb_intel_crtc->cursor_addr; 919 } else { 920 addr = gt->offset; /* Or resource.start ??? */ 921 psb_intel_crtc->cursor_addr = addr; 922 } 923 924 temp = 0; 925 /* set the pipe for the cursor */ 926 temp |= (pipe << 28); 927 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 928 929 if (gma_power_begin(dev, false)) { 930 REG_WRITE(control, temp); 931 REG_WRITE(base, addr); 932 gma_power_end(dev); 933 } 934 935 /* unpin the old bo */ 936 if (psb_intel_crtc->cursor_obj) { 937 gt = container_of(psb_intel_crtc->cursor_obj, 938 struct gtt_range, gem); 939 psb_gtt_unpin(gt); 940 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 941 } 942 943 psb_intel_crtc->cursor_obj = obj; 944 return ret; 945 946 unref_cursor: 947 drm_gem_object_unreference(obj); 948 return ret; 949 } 950 951 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 952 { 953 struct drm_device *dev = crtc->dev; 954 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 955 int pipe = psb_intel_crtc->pipe; 956 uint32_t temp = 0; 957 uint32_t addr; 958 959 960 if (x < 0) { 961 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 962 x = -x; 963 } 964 if (y < 0) { 965 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 966 y = -y; 967 } 968 969 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 970 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 971 972 addr = psb_intel_crtc->cursor_addr; 973 974 if (gma_power_begin(dev, false)) { 975 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 976 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); 977 gma_power_end(dev); 978 } 979 return 0; 980 } 981 982 static void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, 983 u16 *green, u16 *blue, uint32_t type, uint32_t size) 984 { 985 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 986 int i; 987 988 if (size != 256) 989 return; 990 991 for (i = 0; i < 256; i++) { 992 psb_intel_crtc->lut_r[i] = red[i] >> 8; 993 psb_intel_crtc->lut_g[i] = green[i] >> 8; 994 psb_intel_crtc->lut_b[i] = blue[i] >> 8; 995 } 996 997 psb_intel_crtc_load_lut(crtc); 998 } 999 1000 static int psb_crtc_set_config(struct drm_mode_set *set) 1001 { 1002 int ret; 1003 struct drm_device *dev = set->crtc->dev; 1004 struct drm_psb_private *dev_priv = dev->dev_private; 1005 1006 if (!dev_priv->rpm_enabled) 1007 return drm_crtc_helper_set_config(set); 1008 1009 pm_runtime_forbid(&dev->pdev->dev); 1010 ret = drm_crtc_helper_set_config(set); 1011 pm_runtime_allow(&dev->pdev->dev); 1012 return ret; 1013 } 1014 1015 /* Returns the clock of the currently programmed mode of the given pipe. */ 1016 static int psb_intel_crtc_clock_get(struct drm_device *dev, 1017 struct drm_crtc *crtc) 1018 { 1019 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1020 struct drm_psb_private *dev_priv = dev->dev_private; 1021 int pipe = psb_intel_crtc->pipe; 1022 const struct psb_offset *map = &dev_priv->regmap[pipe]; 1023 u32 dpll; 1024 u32 fp; 1025 struct psb_intel_clock_t clock; 1026 bool is_lvds; 1027 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 1028 1029 if (gma_power_begin(dev, false)) { 1030 dpll = REG_READ(map->dpll); 1031 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1032 fp = REG_READ(map->fp0); 1033 else 1034 fp = REG_READ(map->fp1); 1035 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 1036 gma_power_end(dev); 1037 } else { 1038 dpll = p->dpll; 1039 1040 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1041 fp = p->fp0; 1042 else 1043 fp = p->fp1; 1044 1045 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 1046 LVDS_PORT_EN); 1047 } 1048 1049 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 1050 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 1051 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 1052 1053 if (is_lvds) { 1054 clock.p1 = 1055 ffs((dpll & 1056 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 1057 DPLL_FPA01_P1_POST_DIV_SHIFT); 1058 clock.p2 = 14; 1059 1060 if ((dpll & PLL_REF_INPUT_MASK) == 1061 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 1062 /* XXX: might not be 66MHz */ 1063 psb_intel_clock(66000, &clock); 1064 } else 1065 psb_intel_clock(48000, &clock); 1066 } else { 1067 if (dpll & PLL_P1_DIVIDE_BY_TWO) 1068 clock.p1 = 2; 1069 else { 1070 clock.p1 = 1071 ((dpll & 1072 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 1073 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 1074 } 1075 if (dpll & PLL_P2_DIVIDE_BY_4) 1076 clock.p2 = 4; 1077 else 1078 clock.p2 = 2; 1079 1080 psb_intel_clock(48000, &clock); 1081 } 1082 1083 /* XXX: It would be nice to validate the clocks, but we can't reuse 1084 * i830PllIsValid() because it relies on the xf86_config connector 1085 * configuration being accurate, which it isn't necessarily. 1086 */ 1087 1088 return clock.dot; 1089 } 1090 1091 /** Returns the currently programmed mode of the given pipe. */ 1092 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 1093 struct drm_crtc *crtc) 1094 { 1095 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1096 int pipe = psb_intel_crtc->pipe; 1097 struct drm_display_mode *mode; 1098 int htot; 1099 int hsync; 1100 int vtot; 1101 int vsync; 1102 struct drm_psb_private *dev_priv = dev->dev_private; 1103 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 1104 const struct psb_offset *map = &dev_priv->regmap[pipe]; 1105 1106 if (gma_power_begin(dev, false)) { 1107 htot = REG_READ(map->htotal); 1108 hsync = REG_READ(map->hsync); 1109 vtot = REG_READ(map->vtotal); 1110 vsync = REG_READ(map->vsync); 1111 gma_power_end(dev); 1112 } else { 1113 htot = p->htotal; 1114 hsync = p->hsync; 1115 vtot = p->vtotal; 1116 vsync = p->vsync; 1117 } 1118 1119 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1120 if (!mode) 1121 return NULL; 1122 1123 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 1124 mode->hdisplay = (htot & 0xffff) + 1; 1125 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 1126 mode->hsync_start = (hsync & 0xffff) + 1; 1127 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 1128 mode->vdisplay = (vtot & 0xffff) + 1; 1129 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 1130 mode->vsync_start = (vsync & 0xffff) + 1; 1131 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 1132 1133 drm_mode_set_name(mode); 1134 drm_mode_set_crtcinfo(mode, 0); 1135 1136 return mode; 1137 } 1138 1139 static void psb_intel_crtc_destroy(struct drm_crtc *crtc) 1140 { 1141 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1142 struct gtt_range *gt; 1143 1144 /* Unpin the old GEM object */ 1145 if (psb_intel_crtc->cursor_obj) { 1146 gt = container_of(psb_intel_crtc->cursor_obj, 1147 struct gtt_range, gem); 1148 psb_gtt_unpin(gt); 1149 drm_gem_object_unreference(psb_intel_crtc->cursor_obj); 1150 psb_intel_crtc->cursor_obj = NULL; 1151 } 1152 1153 if (psb_intel_crtc->cursor_gt != NULL) 1154 psb_gtt_free_range(crtc->dev, psb_intel_crtc->cursor_gt); 1155 kfree(psb_intel_crtc->crtc_state); 1156 drm_crtc_cleanup(crtc); 1157 kfree(psb_intel_crtc); 1158 } 1159 1160 static void psb_intel_crtc_disable(struct drm_crtc *crtc) 1161 { 1162 struct gtt_range *gt; 1163 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 1164 1165 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 1166 1167 if (crtc->fb) { 1168 gt = to_psb_fb(crtc->fb)->gtt; 1169 psb_gtt_unpin(gt); 1170 } 1171 } 1172 1173 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 1174 .dpms = psb_intel_crtc_dpms, 1175 .mode_fixup = psb_intel_crtc_mode_fixup, 1176 .mode_set = psb_intel_crtc_mode_set, 1177 .mode_set_base = psb_intel_pipe_set_base, 1178 .prepare = psb_intel_crtc_prepare, 1179 .commit = psb_intel_crtc_commit, 1180 .disable = psb_intel_crtc_disable, 1181 }; 1182 1183 const struct drm_crtc_funcs psb_intel_crtc_funcs = { 1184 .save = psb_intel_crtc_save, 1185 .restore = psb_intel_crtc_restore, 1186 .cursor_set = psb_intel_crtc_cursor_set, 1187 .cursor_move = psb_intel_crtc_cursor_move, 1188 .gamma_set = psb_intel_crtc_gamma_set, 1189 .set_config = psb_crtc_set_config, 1190 .destroy = psb_intel_crtc_destroy, 1191 }; 1192 1193 /* 1194 * Set the default value of cursor control and base register 1195 * to zero. This is a workaround for h/w defect on Oaktrail 1196 */ 1197 static void psb_intel_cursor_init(struct drm_device *dev, 1198 struct psb_intel_crtc *psb_intel_crtc) 1199 { 1200 struct drm_psb_private *dev_priv = dev->dev_private; 1201 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 1202 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 1203 struct gtt_range *cursor_gt; 1204 1205 if (dev_priv->ops->cursor_needs_phys) { 1206 /* Allocate 4 pages of stolen mem for a hardware cursor. That 1207 * is enough for the 64 x 64 ARGB cursors we support. 1208 */ 1209 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1); 1210 if (!cursor_gt) { 1211 psb_intel_crtc->cursor_gt = NULL; 1212 goto out; 1213 } 1214 psb_intel_crtc->cursor_gt = cursor_gt; 1215 psb_intel_crtc->cursor_addr = dev_priv->stolen_base + 1216 cursor_gt->offset; 1217 } else { 1218 psb_intel_crtc->cursor_gt = NULL; 1219 } 1220 1221 out: 1222 REG_WRITE(control[psb_intel_crtc->pipe], 0); 1223 REG_WRITE(base[psb_intel_crtc->pipe], 0); 1224 } 1225 1226 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 1227 struct psb_intel_mode_device *mode_dev) 1228 { 1229 struct drm_psb_private *dev_priv = dev->dev_private; 1230 struct psb_intel_crtc *psb_intel_crtc; 1231 int i; 1232 uint16_t *r_base, *g_base, *b_base; 1233 1234 /* We allocate a extra array of drm_connector pointers 1235 * for fbdev after the crtc */ 1236 psb_intel_crtc = 1237 kzalloc(sizeof(struct psb_intel_crtc) + 1238 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 1239 GFP_KERNEL); 1240 if (psb_intel_crtc == NULL) 1241 return; 1242 1243 psb_intel_crtc->crtc_state = 1244 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 1245 if (!psb_intel_crtc->crtc_state) { 1246 dev_err(dev->dev, "Crtc state error: No memory\n"); 1247 kfree(psb_intel_crtc); 1248 return; 1249 } 1250 1251 /* Set the CRTC operations from the chip specific data */ 1252 drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs); 1253 1254 drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256); 1255 psb_intel_crtc->pipe = pipe; 1256 psb_intel_crtc->plane = pipe; 1257 1258 r_base = psb_intel_crtc->base.gamma_store; 1259 g_base = r_base + 256; 1260 b_base = g_base + 256; 1261 for (i = 0; i < 256; i++) { 1262 psb_intel_crtc->lut_r[i] = i; 1263 psb_intel_crtc->lut_g[i] = i; 1264 psb_intel_crtc->lut_b[i] = i; 1265 r_base[i] = i << 8; 1266 g_base[i] = i << 8; 1267 b_base[i] = i << 8; 1268 1269 psb_intel_crtc->lut_adj[i] = 0; 1270 } 1271 1272 psb_intel_crtc->mode_dev = mode_dev; 1273 psb_intel_crtc->cursor_addr = 0; 1274 1275 drm_crtc_helper_add(&psb_intel_crtc->base, 1276 dev_priv->ops->crtc_helper); 1277 1278 /* Setup the array of drm_connector pointer array */ 1279 psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base; 1280 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 1281 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL); 1282 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] = 1283 &psb_intel_crtc->base; 1284 dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] = 1285 &psb_intel_crtc->base; 1286 psb_intel_crtc->mode_set.connectors = 1287 (struct drm_connector **) (psb_intel_crtc + 1); 1288 psb_intel_crtc->mode_set.num_connectors = 0; 1289 psb_intel_cursor_init(dev, psb_intel_crtc); 1290 1291 /* Set to true so that the pipe is forced off on initial config. */ 1292 psb_intel_crtc->active = true; 1293 } 1294 1295 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 1296 struct drm_file *file_priv) 1297 { 1298 struct drm_psb_private *dev_priv = dev->dev_private; 1299 struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data; 1300 struct drm_mode_object *drmmode_obj; 1301 struct psb_intel_crtc *crtc; 1302 1303 if (!dev_priv) { 1304 dev_err(dev->dev, "called with no initialization\n"); 1305 return -EINVAL; 1306 } 1307 1308 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 1309 DRM_MODE_OBJECT_CRTC); 1310 1311 if (!drmmode_obj) { 1312 dev_err(dev->dev, "no such CRTC id\n"); 1313 return -EINVAL; 1314 } 1315 1316 crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj)); 1317 pipe_from_crtc_id->pipe = crtc->pipe; 1318 1319 return 0; 1320 } 1321 1322 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 1323 { 1324 struct drm_crtc *crtc = NULL; 1325 1326 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1327 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 1328 if (psb_intel_crtc->pipe == pipe) 1329 break; 1330 } 1331 return crtc; 1332 } 1333 1334 int psb_intel_connector_clones(struct drm_device *dev, int type_mask) 1335 { 1336 int index_mask = 0; 1337 struct drm_connector *connector; 1338 int entry = 0; 1339 1340 list_for_each_entry(connector, &dev->mode_config.connector_list, 1341 head) { 1342 struct psb_intel_encoder *psb_intel_encoder = 1343 psb_intel_attached_encoder(connector); 1344 if (type_mask & (1 << psb_intel_encoder->type)) 1345 index_mask |= (1 << entry); 1346 entry++; 1347 } 1348 return index_mask; 1349 } 1350 1351 /* current intel driver doesn't take advantage of encoders 1352 always give back the encoder for the connector 1353 */ 1354 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector) 1355 { 1356 struct psb_intel_encoder *psb_intel_encoder = 1357 psb_intel_attached_encoder(connector); 1358 1359 return &psb_intel_encoder->base; 1360 } 1361 1362 void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector, 1363 struct psb_intel_encoder *encoder) 1364 { 1365 connector->encoder = encoder; 1366 drm_mode_connector_attach_encoder(&connector->base, 1367 &encoder->base); 1368 } 1369