1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2006-2011 Intel Corporation 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 12 #include <drm/drm_plane_helper.h> 13 14 #include "framebuffer.h" 15 #include "gem.h" 16 #include "gma_display.h" 17 #include "power.h" 18 #include "psb_drv.h" 19 #include "psb_intel_drv.h" 20 #include "psb_intel_reg.h" 21 22 #define INTEL_LIMIT_I9XX_SDVO_DAC 0 23 #define INTEL_LIMIT_I9XX_LVDS 1 24 25 static const struct gma_limit_t psb_intel_limits[] = { 26 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 27 .dot = {.min = 20000, .max = 400000}, 28 .vco = {.min = 1400000, .max = 2800000}, 29 .n = {.min = 1, .max = 6}, 30 .m = {.min = 70, .max = 120}, 31 .m1 = {.min = 8, .max = 18}, 32 .m2 = {.min = 3, .max = 7}, 33 .p = {.min = 5, .max = 80}, 34 .p1 = {.min = 1, .max = 8}, 35 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5}, 36 .find_pll = gma_find_best_pll, 37 }, 38 { /* INTEL_LIMIT_I9XX_LVDS */ 39 .dot = {.min = 20000, .max = 400000}, 40 .vco = {.min = 1400000, .max = 2800000}, 41 .n = {.min = 1, .max = 6}, 42 .m = {.min = 70, .max = 120}, 43 .m1 = {.min = 8, .max = 18}, 44 .m2 = {.min = 3, .max = 7}, 45 .p = {.min = 7, .max = 98}, 46 .p1 = {.min = 1, .max = 8}, 47 /* The single-channel range is 25-112Mhz, and dual-channel 48 * is 80-224Mhz. Prefer single channel as much as possible. 49 */ 50 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, 51 .find_pll = gma_find_best_pll, 52 }, 53 }; 54 55 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc, 56 int refclk) 57 { 58 const struct gma_limit_t *limit; 59 60 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 61 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 62 else 63 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 64 return limit; 65 } 66 67 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) 68 { 69 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 70 clock->p = clock->p1 * clock->p2; 71 clock->vco = refclk * clock->m / (clock->n + 2); 72 clock->dot = clock->vco / clock->p; 73 } 74 75 /* 76 * Return the pipe currently connected to the panel fitter, 77 * or -1 if the panel fitter is not present or not in use 78 */ 79 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 80 { 81 u32 pfit_control; 82 83 pfit_control = REG_READ(PFIT_CONTROL); 84 85 /* See if the panel fitter is in use */ 86 if ((pfit_control & PFIT_ENABLE) == 0) 87 return -1; 88 /* Must be on PIPE 1 for PSB */ 89 return 1; 90 } 91 92 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 93 struct drm_display_mode *mode, 94 struct drm_display_mode *adjusted_mode, 95 int x, int y, 96 struct drm_framebuffer *old_fb) 97 { 98 struct drm_device *dev = crtc->dev; 99 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 100 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 101 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 102 int pipe = gma_crtc->pipe; 103 const struct psb_offset *map = &dev_priv->regmap[pipe]; 104 int refclk; 105 struct gma_clock_t clock; 106 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 107 bool ok, is_sdvo = false; 108 bool is_lvds = false, is_tv = false; 109 struct drm_mode_config *mode_config = &dev->mode_config; 110 struct drm_connector *connector; 111 const struct gma_limit_t *limit; 112 113 /* No scan out no play */ 114 if (crtc->primary->fb == NULL) { 115 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 116 return 0; 117 } 118 119 list_for_each_entry(connector, &mode_config->connector_list, head) { 120 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 121 122 if (!connector->encoder 123 || connector->encoder->crtc != crtc) 124 continue; 125 126 switch (gma_encoder->type) { 127 case INTEL_OUTPUT_LVDS: 128 is_lvds = true; 129 break; 130 case INTEL_OUTPUT_SDVO: 131 is_sdvo = true; 132 break; 133 case INTEL_OUTPUT_TVOUT: 134 is_tv = true; 135 break; 136 } 137 } 138 139 refclk = 96000; 140 141 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 142 143 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 144 &clock); 145 if (!ok) { 146 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 147 adjusted_mode->clock, clock.dot); 148 return 0; 149 } 150 151 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 152 153 dpll = DPLL_VGA_MODE_DIS; 154 if (is_lvds) { 155 dpll |= DPLLB_MODE_LVDS; 156 dpll |= DPLL_DVO_HIGH_SPEED; 157 } else 158 dpll |= DPLLB_MODE_DAC_SERIAL; 159 if (is_sdvo) { 160 int sdvo_pixel_multiply = 161 adjusted_mode->clock / mode->clock; 162 dpll |= DPLL_DVO_HIGH_SPEED; 163 dpll |= 164 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 165 } 166 167 /* compute bitmask from p1 value */ 168 dpll |= (1 << (clock.p1 - 1)) << 16; 169 switch (clock.p2) { 170 case 5: 171 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 172 break; 173 case 7: 174 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 175 break; 176 case 10: 177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 178 break; 179 case 14: 180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 181 break; 182 } 183 184 if (is_tv) { 185 /* XXX: just matching BIOS for now */ 186 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 187 dpll |= 3; 188 } 189 dpll |= PLL_REF_INPUT_DREFCLK; 190 191 /* setup pipeconf */ 192 pipeconf = REG_READ(map->conf); 193 194 /* Set up the display plane register */ 195 dspcntr = DISPPLANE_GAMMA_ENABLE; 196 197 if (pipe == 0) 198 dspcntr |= DISPPLANE_SEL_PIPE_A; 199 else 200 dspcntr |= DISPPLANE_SEL_PIPE_B; 201 202 dspcntr |= DISPLAY_PLANE_ENABLE; 203 pipeconf |= PIPEACONF_ENABLE; 204 dpll |= DPLL_VCO_ENABLE; 205 206 207 /* Disable the panel fitter if it was on our pipe */ 208 if (psb_intel_panel_fitter_pipe(dev) == pipe) 209 REG_WRITE(PFIT_CONTROL, 0); 210 211 drm_mode_debug_printmodeline(mode); 212 213 if (dpll & DPLL_VCO_ENABLE) { 214 REG_WRITE(map->fp0, fp); 215 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 216 REG_READ(map->dpll); 217 udelay(150); 218 } 219 220 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 221 * This is an exception to the general rule that mode_set doesn't turn 222 * things on. 223 */ 224 if (is_lvds) { 225 u32 lvds = REG_READ(LVDS); 226 227 lvds &= ~LVDS_PIPEB_SELECT; 228 if (pipe == 1) 229 lvds |= LVDS_PIPEB_SELECT; 230 231 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 232 /* Set the B0-B3 data pairs corresponding to 233 * whether we're going to 234 * set the DPLLs for dual-channel mode or not. 235 */ 236 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 237 if (clock.p2 == 7) 238 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 239 240 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 241 * appropriately here, but we need to look more 242 * thoroughly into how panels behave in the two modes. 243 */ 244 245 REG_WRITE(LVDS, lvds); 246 REG_READ(LVDS); 247 } 248 249 REG_WRITE(map->fp0, fp); 250 REG_WRITE(map->dpll, dpll); 251 REG_READ(map->dpll); 252 /* Wait for the clocks to stabilize. */ 253 udelay(150); 254 255 /* write it again -- the BIOS does, after all */ 256 REG_WRITE(map->dpll, dpll); 257 258 REG_READ(map->dpll); 259 /* Wait for the clocks to stabilize. */ 260 udelay(150); 261 262 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 263 ((adjusted_mode->crtc_htotal - 1) << 16)); 264 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 265 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 266 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 267 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 268 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 269 ((adjusted_mode->crtc_vtotal - 1) << 16)); 270 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 271 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 272 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 273 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 274 /* pipesrc and dspsize control the size that is scaled from, 275 * which should always be the user's requested size. 276 */ 277 REG_WRITE(map->size, 278 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 279 REG_WRITE(map->pos, 0); 280 REG_WRITE(map->src, 281 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 282 REG_WRITE(map->conf, pipeconf); 283 REG_READ(map->conf); 284 285 gma_wait_for_vblank(dev); 286 287 REG_WRITE(map->cntr, dspcntr); 288 289 /* Flush the plane changes */ 290 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 291 292 gma_wait_for_vblank(dev); 293 294 return 0; 295 } 296 297 /* Returns the clock of the currently programmed mode of the given pipe. */ 298 static int psb_intel_crtc_clock_get(struct drm_device *dev, 299 struct drm_crtc *crtc) 300 { 301 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 302 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 303 int pipe = gma_crtc->pipe; 304 const struct psb_offset *map = &dev_priv->regmap[pipe]; 305 u32 dpll; 306 u32 fp; 307 struct gma_clock_t clock; 308 bool is_lvds; 309 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 310 311 if (gma_power_begin(dev, false)) { 312 dpll = REG_READ(map->dpll); 313 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 314 fp = REG_READ(map->fp0); 315 else 316 fp = REG_READ(map->fp1); 317 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 318 gma_power_end(dev); 319 } else { 320 dpll = p->dpll; 321 322 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 323 fp = p->fp0; 324 else 325 fp = p->fp1; 326 327 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 328 LVDS_PORT_EN); 329 } 330 331 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 332 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 333 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 334 335 if (is_lvds) { 336 clock.p1 = 337 ffs((dpll & 338 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 339 DPLL_FPA01_P1_POST_DIV_SHIFT); 340 clock.p2 = 14; 341 342 if ((dpll & PLL_REF_INPUT_MASK) == 343 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 344 /* XXX: might not be 66MHz */ 345 psb_intel_clock(66000, &clock); 346 } else 347 psb_intel_clock(48000, &clock); 348 } else { 349 if (dpll & PLL_P1_DIVIDE_BY_TWO) 350 clock.p1 = 2; 351 else { 352 clock.p1 = 353 ((dpll & 354 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 355 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 356 } 357 if (dpll & PLL_P2_DIVIDE_BY_4) 358 clock.p2 = 4; 359 else 360 clock.p2 = 2; 361 362 psb_intel_clock(48000, &clock); 363 } 364 365 /* XXX: It would be nice to validate the clocks, but we can't reuse 366 * i830PllIsValid() because it relies on the xf86_config connector 367 * configuration being accurate, which it isn't necessarily. 368 */ 369 370 return clock.dot; 371 } 372 373 /** Returns the currently programmed mode of the given pipe. */ 374 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 375 struct drm_crtc *crtc) 376 { 377 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 378 int pipe = gma_crtc->pipe; 379 struct drm_display_mode *mode; 380 int htot; 381 int hsync; 382 int vtot; 383 int vsync; 384 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 385 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 386 const struct psb_offset *map = &dev_priv->regmap[pipe]; 387 388 if (gma_power_begin(dev, false)) { 389 htot = REG_READ(map->htotal); 390 hsync = REG_READ(map->hsync); 391 vtot = REG_READ(map->vtotal); 392 vsync = REG_READ(map->vsync); 393 gma_power_end(dev); 394 } else { 395 htot = p->htotal; 396 hsync = p->hsync; 397 vtot = p->vtotal; 398 vsync = p->vsync; 399 } 400 401 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 402 if (!mode) 403 return NULL; 404 405 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 406 mode->hdisplay = (htot & 0xffff) + 1; 407 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 408 mode->hsync_start = (hsync & 0xffff) + 1; 409 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 410 mode->vdisplay = (vtot & 0xffff) + 1; 411 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 412 mode->vsync_start = (vsync & 0xffff) + 1; 413 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 414 415 drm_mode_set_name(mode); 416 drm_mode_set_crtcinfo(mode, 0); 417 418 return mode; 419 } 420 421 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 422 .dpms = gma_crtc_dpms, 423 .mode_set = psb_intel_crtc_mode_set, 424 .mode_set_base = gma_pipe_set_base, 425 .prepare = gma_crtc_prepare, 426 .commit = gma_crtc_commit, 427 .disable = gma_crtc_disable, 428 }; 429 430 const struct drm_crtc_funcs gma_intel_crtc_funcs = { 431 .cursor_set = gma_crtc_cursor_set, 432 .cursor_move = gma_crtc_cursor_move, 433 .gamma_set = gma_crtc_gamma_set, 434 .set_config = gma_crtc_set_config, 435 .destroy = gma_crtc_destroy, 436 .page_flip = gma_crtc_page_flip, 437 .enable_vblank = psb_enable_vblank, 438 .disable_vblank = psb_disable_vblank, 439 .get_vblank_counter = psb_get_vblank_counter, 440 }; 441 442 const struct gma_clock_funcs psb_clock_funcs = { 443 .clock = psb_intel_clock, 444 .limit = psb_intel_limit, 445 .pll_is_valid = gma_pll_is_valid, 446 }; 447 448 /* 449 * Set the default value of cursor control and base register 450 * to zero. This is a workaround for h/w defect on Oaktrail 451 */ 452 static void psb_intel_cursor_init(struct drm_device *dev, 453 struct gma_crtc *gma_crtc) 454 { 455 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 456 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 457 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 458 struct psb_gem_object *cursor_pobj; 459 460 if (dev_priv->ops->cursor_needs_phys) { 461 /* Allocate 4 pages of stolen mem for a hardware cursor. That 462 * is enough for the 64 x 64 ARGB cursors we support. 463 */ 464 cursor_pobj = psb_gem_create(dev, 4 * PAGE_SIZE, "cursor", true, PAGE_SIZE); 465 if (IS_ERR(cursor_pobj)) { 466 gma_crtc->cursor_pobj = NULL; 467 goto out; 468 } 469 gma_crtc->cursor_pobj = cursor_pobj; 470 gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset; 471 } else { 472 gma_crtc->cursor_pobj = NULL; 473 } 474 475 out: 476 REG_WRITE(control[gma_crtc->pipe], 0); 477 REG_WRITE(base[gma_crtc->pipe], 0); 478 } 479 480 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 481 struct psb_intel_mode_device *mode_dev) 482 { 483 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 484 struct gma_crtc *gma_crtc; 485 int i; 486 487 /* We allocate a extra array of drm_connector pointers 488 * for fbdev after the crtc */ 489 gma_crtc = kzalloc(sizeof(struct gma_crtc) + 490 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 491 GFP_KERNEL); 492 if (gma_crtc == NULL) 493 return; 494 495 gma_crtc->crtc_state = 496 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 497 if (!gma_crtc->crtc_state) { 498 dev_err(dev->dev, "Crtc state error: No memory\n"); 499 kfree(gma_crtc); 500 return; 501 } 502 503 /* Set the CRTC operations from the chip specific data */ 504 drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs); 505 506 /* Set the CRTC clock functions from chip specific data */ 507 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; 508 509 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); 510 gma_crtc->pipe = pipe; 511 gma_crtc->plane = pipe; 512 513 for (i = 0; i < 256; i++) 514 gma_crtc->lut_adj[i] = 0; 515 516 gma_crtc->mode_dev = mode_dev; 517 gma_crtc->cursor_addr = 0; 518 519 drm_crtc_helper_add(&gma_crtc->base, 520 dev_priv->ops->crtc_helper); 521 522 /* Setup the array of drm_connector pointer array */ 523 gma_crtc->mode_set.crtc = &gma_crtc->base; 524 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 525 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); 526 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; 527 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; 528 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); 529 gma_crtc->mode_set.num_connectors = 0; 530 psb_intel_cursor_init(dev, gma_crtc); 531 532 /* Set to true so that the pipe is forced off on initial config. */ 533 gma_crtc->active = true; 534 } 535 536 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 537 { 538 struct drm_crtc *crtc = NULL; 539 540 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 541 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 542 if (gma_crtc->pipe == pipe) 543 break; 544 } 545 return crtc; 546 } 547 548 int gma_connector_clones(struct drm_device *dev, int type_mask) 549 { 550 int index_mask = 0; 551 struct drm_connector *connector; 552 int entry = 0; 553 554 list_for_each_entry(connector, &dev->mode_config.connector_list, 555 head) { 556 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 557 if (type_mask & (1 << gma_encoder->type)) 558 index_mask |= (1 << entry); 559 entry++; 560 } 561 return index_mask; 562 } 563