1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21 #include <linux/delay.h> 22 #include <linux/i2c.h> 23 24 #include <drm/drm_plane_helper.h> 25 26 #include "framebuffer.h" 27 #include "gma_display.h" 28 #include "power.h" 29 #include "psb_drv.h" 30 #include "psb_intel_drv.h" 31 #include "psb_intel_reg.h" 32 33 #define INTEL_LIMIT_I9XX_SDVO_DAC 0 34 #define INTEL_LIMIT_I9XX_LVDS 1 35 36 static const struct gma_limit_t psb_intel_limits[] = { 37 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 38 .dot = {.min = 20000, .max = 400000}, 39 .vco = {.min = 1400000, .max = 2800000}, 40 .n = {.min = 1, .max = 6}, 41 .m = {.min = 70, .max = 120}, 42 .m1 = {.min = 8, .max = 18}, 43 .m2 = {.min = 3, .max = 7}, 44 .p = {.min = 5, .max = 80}, 45 .p1 = {.min = 1, .max = 8}, 46 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5}, 47 .find_pll = gma_find_best_pll, 48 }, 49 { /* INTEL_LIMIT_I9XX_LVDS */ 50 .dot = {.min = 20000, .max = 400000}, 51 .vco = {.min = 1400000, .max = 2800000}, 52 .n = {.min = 1, .max = 6}, 53 .m = {.min = 70, .max = 120}, 54 .m1 = {.min = 8, .max = 18}, 55 .m2 = {.min = 3, .max = 7}, 56 .p = {.min = 7, .max = 98}, 57 .p1 = {.min = 1, .max = 8}, 58 /* The single-channel range is 25-112Mhz, and dual-channel 59 * is 80-224Mhz. Prefer single channel as much as possible. 60 */ 61 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, 62 .find_pll = gma_find_best_pll, 63 }, 64 }; 65 66 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc, 67 int refclk) 68 { 69 const struct gma_limit_t *limit; 70 71 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 72 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 73 else 74 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 75 return limit; 76 } 77 78 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) 79 { 80 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 81 clock->p = clock->p1 * clock->p2; 82 clock->vco = refclk * clock->m / (clock->n + 2); 83 clock->dot = clock->vco / clock->p; 84 } 85 86 /** 87 * Return the pipe currently connected to the panel fitter, 88 * or -1 if the panel fitter is not present or not in use 89 */ 90 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 91 { 92 u32 pfit_control; 93 94 pfit_control = REG_READ(PFIT_CONTROL); 95 96 /* See if the panel fitter is in use */ 97 if ((pfit_control & PFIT_ENABLE) == 0) 98 return -1; 99 /* Must be on PIPE 1 for PSB */ 100 return 1; 101 } 102 103 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 104 struct drm_display_mode *mode, 105 struct drm_display_mode *adjusted_mode, 106 int x, int y, 107 struct drm_framebuffer *old_fb) 108 { 109 struct drm_device *dev = crtc->dev; 110 struct drm_psb_private *dev_priv = dev->dev_private; 111 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 112 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 113 int pipe = gma_crtc->pipe; 114 const struct psb_offset *map = &dev_priv->regmap[pipe]; 115 int refclk; 116 struct gma_clock_t clock; 117 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 118 bool ok, is_sdvo = false; 119 bool is_lvds = false, is_tv = false; 120 struct drm_mode_config *mode_config = &dev->mode_config; 121 struct drm_connector *connector; 122 const struct gma_limit_t *limit; 123 124 /* No scan out no play */ 125 if (crtc->primary->fb == NULL) { 126 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 127 return 0; 128 } 129 130 list_for_each_entry(connector, &mode_config->connector_list, head) { 131 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 132 133 if (!connector->encoder 134 || connector->encoder->crtc != crtc) 135 continue; 136 137 switch (gma_encoder->type) { 138 case INTEL_OUTPUT_LVDS: 139 is_lvds = true; 140 break; 141 case INTEL_OUTPUT_SDVO: 142 is_sdvo = true; 143 break; 144 case INTEL_OUTPUT_TVOUT: 145 is_tv = true; 146 break; 147 } 148 } 149 150 refclk = 96000; 151 152 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 153 154 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 155 &clock); 156 if (!ok) { 157 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 158 adjusted_mode->clock, clock.dot); 159 return 0; 160 } 161 162 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 163 164 dpll = DPLL_VGA_MODE_DIS; 165 if (is_lvds) { 166 dpll |= DPLLB_MODE_LVDS; 167 dpll |= DPLL_DVO_HIGH_SPEED; 168 } else 169 dpll |= DPLLB_MODE_DAC_SERIAL; 170 if (is_sdvo) { 171 int sdvo_pixel_multiply = 172 adjusted_mode->clock / mode->clock; 173 dpll |= DPLL_DVO_HIGH_SPEED; 174 dpll |= 175 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 176 } 177 178 /* compute bitmask from p1 value */ 179 dpll |= (1 << (clock.p1 - 1)) << 16; 180 switch (clock.p2) { 181 case 5: 182 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 183 break; 184 case 7: 185 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 186 break; 187 case 10: 188 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 189 break; 190 case 14: 191 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 192 break; 193 } 194 195 if (is_tv) { 196 /* XXX: just matching BIOS for now */ 197 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 198 dpll |= 3; 199 } 200 dpll |= PLL_REF_INPUT_DREFCLK; 201 202 /* setup pipeconf */ 203 pipeconf = REG_READ(map->conf); 204 205 /* Set up the display plane register */ 206 dspcntr = DISPPLANE_GAMMA_ENABLE; 207 208 if (pipe == 0) 209 dspcntr |= DISPPLANE_SEL_PIPE_A; 210 else 211 dspcntr |= DISPPLANE_SEL_PIPE_B; 212 213 dspcntr |= DISPLAY_PLANE_ENABLE; 214 pipeconf |= PIPEACONF_ENABLE; 215 dpll |= DPLL_VCO_ENABLE; 216 217 218 /* Disable the panel fitter if it was on our pipe */ 219 if (psb_intel_panel_fitter_pipe(dev) == pipe) 220 REG_WRITE(PFIT_CONTROL, 0); 221 222 drm_mode_debug_printmodeline(mode); 223 224 if (dpll & DPLL_VCO_ENABLE) { 225 REG_WRITE(map->fp0, fp); 226 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 227 REG_READ(map->dpll); 228 udelay(150); 229 } 230 231 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 232 * This is an exception to the general rule that mode_set doesn't turn 233 * things on. 234 */ 235 if (is_lvds) { 236 u32 lvds = REG_READ(LVDS); 237 238 lvds &= ~LVDS_PIPEB_SELECT; 239 if (pipe == 1) 240 lvds |= LVDS_PIPEB_SELECT; 241 242 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 243 /* Set the B0-B3 data pairs corresponding to 244 * whether we're going to 245 * set the DPLLs for dual-channel mode or not. 246 */ 247 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 248 if (clock.p2 == 7) 249 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 250 251 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 252 * appropriately here, but we need to look more 253 * thoroughly into how panels behave in the two modes. 254 */ 255 256 REG_WRITE(LVDS, lvds); 257 REG_READ(LVDS); 258 } 259 260 REG_WRITE(map->fp0, fp); 261 REG_WRITE(map->dpll, dpll); 262 REG_READ(map->dpll); 263 /* Wait for the clocks to stabilize. */ 264 udelay(150); 265 266 /* write it again -- the BIOS does, after all */ 267 REG_WRITE(map->dpll, dpll); 268 269 REG_READ(map->dpll); 270 /* Wait for the clocks to stabilize. */ 271 udelay(150); 272 273 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 274 ((adjusted_mode->crtc_htotal - 1) << 16)); 275 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 276 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 277 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 278 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 279 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 280 ((adjusted_mode->crtc_vtotal - 1) << 16)); 281 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 282 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 283 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 284 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 285 /* pipesrc and dspsize control the size that is scaled from, 286 * which should always be the user's requested size. 287 */ 288 REG_WRITE(map->size, 289 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 290 REG_WRITE(map->pos, 0); 291 REG_WRITE(map->src, 292 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 293 REG_WRITE(map->conf, pipeconf); 294 REG_READ(map->conf); 295 296 gma_wait_for_vblank(dev); 297 298 REG_WRITE(map->cntr, dspcntr); 299 300 /* Flush the plane changes */ 301 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 302 303 gma_wait_for_vblank(dev); 304 305 return 0; 306 } 307 308 /* Returns the clock of the currently programmed mode of the given pipe. */ 309 static int psb_intel_crtc_clock_get(struct drm_device *dev, 310 struct drm_crtc *crtc) 311 { 312 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 313 struct drm_psb_private *dev_priv = dev->dev_private; 314 int pipe = gma_crtc->pipe; 315 const struct psb_offset *map = &dev_priv->regmap[pipe]; 316 u32 dpll; 317 u32 fp; 318 struct gma_clock_t clock; 319 bool is_lvds; 320 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 321 322 if (gma_power_begin(dev, false)) { 323 dpll = REG_READ(map->dpll); 324 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 325 fp = REG_READ(map->fp0); 326 else 327 fp = REG_READ(map->fp1); 328 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 329 gma_power_end(dev); 330 } else { 331 dpll = p->dpll; 332 333 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 334 fp = p->fp0; 335 else 336 fp = p->fp1; 337 338 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 339 LVDS_PORT_EN); 340 } 341 342 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 343 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 344 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 345 346 if (is_lvds) { 347 clock.p1 = 348 ffs((dpll & 349 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 350 DPLL_FPA01_P1_POST_DIV_SHIFT); 351 clock.p2 = 14; 352 353 if ((dpll & PLL_REF_INPUT_MASK) == 354 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 355 /* XXX: might not be 66MHz */ 356 psb_intel_clock(66000, &clock); 357 } else 358 psb_intel_clock(48000, &clock); 359 } else { 360 if (dpll & PLL_P1_DIVIDE_BY_TWO) 361 clock.p1 = 2; 362 else { 363 clock.p1 = 364 ((dpll & 365 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 366 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 367 } 368 if (dpll & PLL_P2_DIVIDE_BY_4) 369 clock.p2 = 4; 370 else 371 clock.p2 = 2; 372 373 psb_intel_clock(48000, &clock); 374 } 375 376 /* XXX: It would be nice to validate the clocks, but we can't reuse 377 * i830PllIsValid() because it relies on the xf86_config connector 378 * configuration being accurate, which it isn't necessarily. 379 */ 380 381 return clock.dot; 382 } 383 384 /** Returns the currently programmed mode of the given pipe. */ 385 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 386 struct drm_crtc *crtc) 387 { 388 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 389 int pipe = gma_crtc->pipe; 390 struct drm_display_mode *mode; 391 int htot; 392 int hsync; 393 int vtot; 394 int vsync; 395 struct drm_psb_private *dev_priv = dev->dev_private; 396 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 397 const struct psb_offset *map = &dev_priv->regmap[pipe]; 398 399 if (gma_power_begin(dev, false)) { 400 htot = REG_READ(map->htotal); 401 hsync = REG_READ(map->hsync); 402 vtot = REG_READ(map->vtotal); 403 vsync = REG_READ(map->vsync); 404 gma_power_end(dev); 405 } else { 406 htot = p->htotal; 407 hsync = p->hsync; 408 vtot = p->vtotal; 409 vsync = p->vsync; 410 } 411 412 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 413 if (!mode) 414 return NULL; 415 416 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 417 mode->hdisplay = (htot & 0xffff) + 1; 418 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 419 mode->hsync_start = (hsync & 0xffff) + 1; 420 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 421 mode->vdisplay = (vtot & 0xffff) + 1; 422 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 423 mode->vsync_start = (vsync & 0xffff) + 1; 424 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 425 426 drm_mode_set_name(mode); 427 drm_mode_set_crtcinfo(mode, 0); 428 429 return mode; 430 } 431 432 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 433 .dpms = gma_crtc_dpms, 434 .mode_set = psb_intel_crtc_mode_set, 435 .mode_set_base = gma_pipe_set_base, 436 .prepare = gma_crtc_prepare, 437 .commit = gma_crtc_commit, 438 .disable = gma_crtc_disable, 439 }; 440 441 const struct drm_crtc_funcs psb_intel_crtc_funcs = { 442 .cursor_set = gma_crtc_cursor_set, 443 .cursor_move = gma_crtc_cursor_move, 444 .gamma_set = gma_crtc_gamma_set, 445 .set_config = gma_crtc_set_config, 446 .destroy = gma_crtc_destroy, 447 }; 448 449 const struct gma_clock_funcs psb_clock_funcs = { 450 .clock = psb_intel_clock, 451 .limit = psb_intel_limit, 452 .pll_is_valid = gma_pll_is_valid, 453 }; 454 455 /* 456 * Set the default value of cursor control and base register 457 * to zero. This is a workaround for h/w defect on Oaktrail 458 */ 459 static void psb_intel_cursor_init(struct drm_device *dev, 460 struct gma_crtc *gma_crtc) 461 { 462 struct drm_psb_private *dev_priv = dev->dev_private; 463 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 464 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 465 struct gtt_range *cursor_gt; 466 467 if (dev_priv->ops->cursor_needs_phys) { 468 /* Allocate 4 pages of stolen mem for a hardware cursor. That 469 * is enough for the 64 x 64 ARGB cursors we support. 470 */ 471 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1, 472 PAGE_SIZE); 473 if (!cursor_gt) { 474 gma_crtc->cursor_gt = NULL; 475 goto out; 476 } 477 gma_crtc->cursor_gt = cursor_gt; 478 gma_crtc->cursor_addr = dev_priv->stolen_base + 479 cursor_gt->offset; 480 } else { 481 gma_crtc->cursor_gt = NULL; 482 } 483 484 out: 485 REG_WRITE(control[gma_crtc->pipe], 0); 486 REG_WRITE(base[gma_crtc->pipe], 0); 487 } 488 489 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 490 struct psb_intel_mode_device *mode_dev) 491 { 492 struct drm_psb_private *dev_priv = dev->dev_private; 493 struct gma_crtc *gma_crtc; 494 int i; 495 496 /* We allocate a extra array of drm_connector pointers 497 * for fbdev after the crtc */ 498 gma_crtc = kzalloc(sizeof(struct gma_crtc) + 499 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 500 GFP_KERNEL); 501 if (gma_crtc == NULL) 502 return; 503 504 gma_crtc->crtc_state = 505 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 506 if (!gma_crtc->crtc_state) { 507 dev_err(dev->dev, "Crtc state error: No memory\n"); 508 kfree(gma_crtc); 509 return; 510 } 511 512 /* Set the CRTC operations from the chip specific data */ 513 drm_crtc_init(dev, &gma_crtc->base, dev_priv->ops->crtc_funcs); 514 515 /* Set the CRTC clock functions from chip specific data */ 516 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; 517 518 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); 519 gma_crtc->pipe = pipe; 520 gma_crtc->plane = pipe; 521 522 for (i = 0; i < 256; i++) 523 gma_crtc->lut_adj[i] = 0; 524 525 gma_crtc->mode_dev = mode_dev; 526 gma_crtc->cursor_addr = 0; 527 528 drm_crtc_helper_add(&gma_crtc->base, 529 dev_priv->ops->crtc_helper); 530 531 /* Setup the array of drm_connector pointer array */ 532 gma_crtc->mode_set.crtc = &gma_crtc->base; 533 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 534 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); 535 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; 536 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; 537 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); 538 gma_crtc->mode_set.num_connectors = 0; 539 psb_intel_cursor_init(dev, gma_crtc); 540 541 /* Set to true so that the pipe is forced off on initial config. */ 542 gma_crtc->active = true; 543 } 544 545 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 546 { 547 struct drm_crtc *crtc = NULL; 548 549 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 550 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 551 if (gma_crtc->pipe == pipe) 552 break; 553 } 554 return crtc; 555 } 556 557 int gma_connector_clones(struct drm_device *dev, int type_mask) 558 { 559 int index_mask = 0; 560 struct drm_connector *connector; 561 int entry = 0; 562 563 list_for_each_entry(connector, &dev->mode_config.connector_list, 564 head) { 565 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 566 if (type_mask & (1 << gma_encoder->type)) 567 index_mask |= (1 << entry); 568 entry++; 569 } 570 return index_mask; 571 } 572