1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2006-2011 Intel Corporation 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 12 #include <drm/drm_plane_helper.h> 13 14 #include "framebuffer.h" 15 #include "gem.h" 16 #include "gma_display.h" 17 #include "power.h" 18 #include "psb_drv.h" 19 #include "psb_intel_drv.h" 20 #include "psb_intel_reg.h" 21 22 #define INTEL_LIMIT_I9XX_SDVO_DAC 0 23 #define INTEL_LIMIT_I9XX_LVDS 1 24 25 static const struct gma_limit_t psb_intel_limits[] = { 26 { /* INTEL_LIMIT_I9XX_SDVO_DAC */ 27 .dot = {.min = 20000, .max = 400000}, 28 .vco = {.min = 1400000, .max = 2800000}, 29 .n = {.min = 1, .max = 6}, 30 .m = {.min = 70, .max = 120}, 31 .m1 = {.min = 8, .max = 18}, 32 .m2 = {.min = 3, .max = 7}, 33 .p = {.min = 5, .max = 80}, 34 .p1 = {.min = 1, .max = 8}, 35 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5}, 36 .find_pll = gma_find_best_pll, 37 }, 38 { /* INTEL_LIMIT_I9XX_LVDS */ 39 .dot = {.min = 20000, .max = 400000}, 40 .vco = {.min = 1400000, .max = 2800000}, 41 .n = {.min = 1, .max = 6}, 42 .m = {.min = 70, .max = 120}, 43 .m1 = {.min = 8, .max = 18}, 44 .m2 = {.min = 3, .max = 7}, 45 .p = {.min = 7, .max = 98}, 46 .p1 = {.min = 1, .max = 8}, 47 /* The single-channel range is 25-112Mhz, and dual-channel 48 * is 80-224Mhz. Prefer single channel as much as possible. 49 */ 50 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7}, 51 .find_pll = gma_find_best_pll, 52 }, 53 }; 54 55 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc, 56 int refclk) 57 { 58 const struct gma_limit_t *limit; 59 60 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 61 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS]; 62 else 63 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; 64 return limit; 65 } 66 67 static void psb_intel_clock(int refclk, struct gma_clock_t *clock) 68 { 69 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 70 clock->p = clock->p1 * clock->p2; 71 clock->vco = refclk * clock->m / (clock->n + 2); 72 clock->dot = clock->vco / clock->p; 73 } 74 75 /* 76 * Return the pipe currently connected to the panel fitter, 77 * or -1 if the panel fitter is not present or not in use 78 */ 79 static int psb_intel_panel_fitter_pipe(struct drm_device *dev) 80 { 81 u32 pfit_control; 82 83 pfit_control = REG_READ(PFIT_CONTROL); 84 85 /* See if the panel fitter is in use */ 86 if ((pfit_control & PFIT_ENABLE) == 0) 87 return -1; 88 /* Must be on PIPE 1 for PSB */ 89 return 1; 90 } 91 92 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc, 93 struct drm_display_mode *mode, 94 struct drm_display_mode *adjusted_mode, 95 int x, int y, 96 struct drm_framebuffer *old_fb) 97 { 98 struct drm_device *dev = crtc->dev; 99 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 100 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 101 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 102 int pipe = gma_crtc->pipe; 103 const struct psb_offset *map = &dev_priv->regmap[pipe]; 104 int refclk; 105 struct gma_clock_t clock; 106 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 107 bool ok, is_sdvo = false; 108 bool is_lvds = false, is_tv = false; 109 struct drm_connector_list_iter conn_iter; 110 struct drm_connector *connector; 111 const struct gma_limit_t *limit; 112 113 /* No scan out no play */ 114 if (crtc->primary->fb == NULL) { 115 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 116 return 0; 117 } 118 119 drm_connector_list_iter_begin(dev, &conn_iter); 120 drm_for_each_connector_iter(connector, &conn_iter) { 121 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 122 123 if (!connector->encoder 124 || connector->encoder->crtc != crtc) 125 continue; 126 127 switch (gma_encoder->type) { 128 case INTEL_OUTPUT_LVDS: 129 is_lvds = true; 130 break; 131 case INTEL_OUTPUT_SDVO: 132 is_sdvo = true; 133 break; 134 case INTEL_OUTPUT_TVOUT: 135 is_tv = true; 136 break; 137 } 138 139 break; 140 } 141 drm_connector_list_iter_end(&conn_iter); 142 143 refclk = 96000; 144 145 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 146 147 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 148 &clock); 149 if (!ok) { 150 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 151 adjusted_mode->clock, clock.dot); 152 return 0; 153 } 154 155 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 156 157 dpll = DPLL_VGA_MODE_DIS; 158 if (is_lvds) { 159 dpll |= DPLLB_MODE_LVDS; 160 dpll |= DPLL_DVO_HIGH_SPEED; 161 } else 162 dpll |= DPLLB_MODE_DAC_SERIAL; 163 if (is_sdvo) { 164 int sdvo_pixel_multiply = 165 adjusted_mode->clock / mode->clock; 166 dpll |= DPLL_DVO_HIGH_SPEED; 167 dpll |= 168 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 169 } 170 171 /* compute bitmask from p1 value */ 172 dpll |= (1 << (clock.p1 - 1)) << 16; 173 switch (clock.p2) { 174 case 5: 175 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 176 break; 177 case 7: 178 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 179 break; 180 case 10: 181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 182 break; 183 case 14: 184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 185 break; 186 } 187 188 if (is_tv) { 189 /* XXX: just matching BIOS for now */ 190 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 191 dpll |= 3; 192 } 193 dpll |= PLL_REF_INPUT_DREFCLK; 194 195 /* setup pipeconf */ 196 pipeconf = REG_READ(map->conf); 197 198 /* Set up the display plane register */ 199 dspcntr = DISPPLANE_GAMMA_ENABLE; 200 201 if (pipe == 0) 202 dspcntr |= DISPPLANE_SEL_PIPE_A; 203 else 204 dspcntr |= DISPPLANE_SEL_PIPE_B; 205 206 dspcntr |= DISPLAY_PLANE_ENABLE; 207 pipeconf |= PIPEACONF_ENABLE; 208 dpll |= DPLL_VCO_ENABLE; 209 210 211 /* Disable the panel fitter if it was on our pipe */ 212 if (psb_intel_panel_fitter_pipe(dev) == pipe) 213 REG_WRITE(PFIT_CONTROL, 0); 214 215 drm_mode_debug_printmodeline(mode); 216 217 if (dpll & DPLL_VCO_ENABLE) { 218 REG_WRITE(map->fp0, fp); 219 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); 220 REG_READ(map->dpll); 221 udelay(150); 222 } 223 224 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 225 * This is an exception to the general rule that mode_set doesn't turn 226 * things on. 227 */ 228 if (is_lvds) { 229 u32 lvds = REG_READ(LVDS); 230 231 lvds &= ~LVDS_PIPEB_SELECT; 232 if (pipe == 1) 233 lvds |= LVDS_PIPEB_SELECT; 234 235 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 236 /* Set the B0-B3 data pairs corresponding to 237 * whether we're going to 238 * set the DPLLs for dual-channel mode or not. 239 */ 240 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 241 if (clock.p2 == 7) 242 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 243 244 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 245 * appropriately here, but we need to look more 246 * thoroughly into how panels behave in the two modes. 247 */ 248 249 REG_WRITE(LVDS, lvds); 250 REG_READ(LVDS); 251 } 252 253 REG_WRITE(map->fp0, fp); 254 REG_WRITE(map->dpll, dpll); 255 REG_READ(map->dpll); 256 /* Wait for the clocks to stabilize. */ 257 udelay(150); 258 259 /* write it again -- the BIOS does, after all */ 260 REG_WRITE(map->dpll, dpll); 261 262 REG_READ(map->dpll); 263 /* Wait for the clocks to stabilize. */ 264 udelay(150); 265 266 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 267 ((adjusted_mode->crtc_htotal - 1) << 16)); 268 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 269 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 270 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 271 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 272 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 273 ((adjusted_mode->crtc_vtotal - 1) << 16)); 274 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 275 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 276 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 277 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 278 /* pipesrc and dspsize control the size that is scaled from, 279 * which should always be the user's requested size. 280 */ 281 REG_WRITE(map->size, 282 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 283 REG_WRITE(map->pos, 0); 284 REG_WRITE(map->src, 285 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 286 REG_WRITE(map->conf, pipeconf); 287 REG_READ(map->conf); 288 289 gma_wait_for_vblank(dev); 290 291 REG_WRITE(map->cntr, dspcntr); 292 293 /* Flush the plane changes */ 294 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 295 296 gma_wait_for_vblank(dev); 297 298 return 0; 299 } 300 301 /* Returns the clock of the currently programmed mode of the given pipe. */ 302 static int psb_intel_crtc_clock_get(struct drm_device *dev, 303 struct drm_crtc *crtc) 304 { 305 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 306 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 307 int pipe = gma_crtc->pipe; 308 const struct psb_offset *map = &dev_priv->regmap[pipe]; 309 u32 dpll; 310 u32 fp; 311 struct gma_clock_t clock; 312 bool is_lvds; 313 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 314 315 if (gma_power_begin(dev, false)) { 316 dpll = REG_READ(map->dpll); 317 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 318 fp = REG_READ(map->fp0); 319 else 320 fp = REG_READ(map->fp1); 321 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 322 gma_power_end(dev); 323 } else { 324 dpll = p->dpll; 325 326 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 327 fp = p->fp0; 328 else 329 fp = p->fp1; 330 331 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 332 LVDS_PORT_EN); 333 } 334 335 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 336 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 337 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 338 339 if (is_lvds) { 340 clock.p1 = 341 ffs((dpll & 342 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 343 DPLL_FPA01_P1_POST_DIV_SHIFT); 344 clock.p2 = 14; 345 346 if ((dpll & PLL_REF_INPUT_MASK) == 347 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 348 /* XXX: might not be 66MHz */ 349 psb_intel_clock(66000, &clock); 350 } else 351 psb_intel_clock(48000, &clock); 352 } else { 353 if (dpll & PLL_P1_DIVIDE_BY_TWO) 354 clock.p1 = 2; 355 else { 356 clock.p1 = 357 ((dpll & 358 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 359 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 360 } 361 if (dpll & PLL_P2_DIVIDE_BY_4) 362 clock.p2 = 4; 363 else 364 clock.p2 = 2; 365 366 psb_intel_clock(48000, &clock); 367 } 368 369 /* XXX: It would be nice to validate the clocks, but we can't reuse 370 * i830PllIsValid() because it relies on the xf86_config connector 371 * configuration being accurate, which it isn't necessarily. 372 */ 373 374 return clock.dot; 375 } 376 377 /** Returns the currently programmed mode of the given pipe. */ 378 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev, 379 struct drm_crtc *crtc) 380 { 381 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 382 int pipe = gma_crtc->pipe; 383 struct drm_display_mode *mode; 384 int htot; 385 int hsync; 386 int vtot; 387 int vsync; 388 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 389 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 390 const struct psb_offset *map = &dev_priv->regmap[pipe]; 391 392 if (gma_power_begin(dev, false)) { 393 htot = REG_READ(map->htotal); 394 hsync = REG_READ(map->hsync); 395 vtot = REG_READ(map->vtotal); 396 vsync = REG_READ(map->vsync); 397 gma_power_end(dev); 398 } else { 399 htot = p->htotal; 400 hsync = p->hsync; 401 vtot = p->vtotal; 402 vsync = p->vsync; 403 } 404 405 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 406 if (!mode) 407 return NULL; 408 409 mode->clock = psb_intel_crtc_clock_get(dev, crtc); 410 mode->hdisplay = (htot & 0xffff) + 1; 411 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 412 mode->hsync_start = (hsync & 0xffff) + 1; 413 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 414 mode->vdisplay = (vtot & 0xffff) + 1; 415 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 416 mode->vsync_start = (vsync & 0xffff) + 1; 417 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 418 419 drm_mode_set_name(mode); 420 drm_mode_set_crtcinfo(mode, 0); 421 422 return mode; 423 } 424 425 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = { 426 .dpms = gma_crtc_dpms, 427 .mode_set = psb_intel_crtc_mode_set, 428 .mode_set_base = gma_pipe_set_base, 429 .prepare = gma_crtc_prepare, 430 .commit = gma_crtc_commit, 431 .disable = gma_crtc_disable, 432 }; 433 434 const struct gma_clock_funcs psb_clock_funcs = { 435 .clock = psb_intel_clock, 436 .limit = psb_intel_limit, 437 .pll_is_valid = gma_pll_is_valid, 438 }; 439 440 /* 441 * Set the default value of cursor control and base register 442 * to zero. This is a workaround for h/w defect on Oaktrail 443 */ 444 static void psb_intel_cursor_init(struct drm_device *dev, 445 struct gma_crtc *gma_crtc) 446 { 447 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 448 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR }; 449 u32 base[3] = { CURABASE, CURBBASE, CURCBASE }; 450 struct psb_gem_object *cursor_pobj; 451 452 if (dev_priv->ops->cursor_needs_phys) { 453 /* Allocate 4 pages of stolen mem for a hardware cursor. That 454 * is enough for the 64 x 64 ARGB cursors we support. 455 */ 456 cursor_pobj = psb_gem_create(dev, 4 * PAGE_SIZE, "cursor", true, PAGE_SIZE); 457 if (IS_ERR(cursor_pobj)) { 458 gma_crtc->cursor_pobj = NULL; 459 goto out; 460 } 461 gma_crtc->cursor_pobj = cursor_pobj; 462 gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset; 463 } else { 464 gma_crtc->cursor_pobj = NULL; 465 } 466 467 out: 468 REG_WRITE(control[gma_crtc->pipe], 0); 469 REG_WRITE(base[gma_crtc->pipe], 0); 470 } 471 472 void psb_intel_crtc_init(struct drm_device *dev, int pipe, 473 struct psb_intel_mode_device *mode_dev) 474 { 475 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 476 struct gma_crtc *gma_crtc; 477 int i; 478 479 /* We allocate a extra array of drm_connector pointers 480 * for fbdev after the crtc */ 481 gma_crtc = kzalloc(sizeof(struct gma_crtc) + 482 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 483 GFP_KERNEL); 484 if (gma_crtc == NULL) 485 return; 486 487 gma_crtc->crtc_state = 488 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL); 489 if (!gma_crtc->crtc_state) { 490 dev_err(dev->dev, "Crtc state error: No memory\n"); 491 kfree(gma_crtc); 492 return; 493 } 494 495 drm_crtc_init(dev, &gma_crtc->base, &gma_crtc_funcs); 496 497 /* Set the CRTC clock functions from chip specific data */ 498 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs; 499 500 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256); 501 gma_crtc->pipe = pipe; 502 gma_crtc->plane = pipe; 503 504 for (i = 0; i < 256; i++) 505 gma_crtc->lut_adj[i] = 0; 506 507 gma_crtc->mode_dev = mode_dev; 508 gma_crtc->cursor_addr = 0; 509 510 drm_crtc_helper_add(&gma_crtc->base, 511 dev_priv->ops->crtc_helper); 512 513 /* Setup the array of drm_connector pointer array */ 514 gma_crtc->mode_set.crtc = &gma_crtc->base; 515 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 516 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL); 517 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base; 518 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base; 519 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1); 520 gma_crtc->mode_set.num_connectors = 0; 521 psb_intel_cursor_init(dev, gma_crtc); 522 523 /* Set to true so that the pipe is forced off on initial config. */ 524 gma_crtc->active = true; 525 } 526 527 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) 528 { 529 struct drm_crtc *crtc; 530 531 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 532 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 533 534 if (gma_crtc->pipe == pipe) 535 return crtc; 536 } 537 return NULL; 538 } 539 540 int gma_connector_clones(struct drm_device *dev, int type_mask) 541 { 542 struct drm_connector_list_iter conn_iter; 543 struct drm_connector *connector; 544 int index_mask = 0; 545 int entry = 0; 546 547 drm_connector_list_iter_begin(dev, &conn_iter); 548 drm_for_each_connector_iter(connector, &conn_iter) { 549 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 550 if (type_mask & (1 << gma_encoder->type)) 551 index_mask |= (1 << entry); 552 entry++; 553 } 554 drm_connector_list_iter_end(&conn_iter); 555 556 return index_mask; 557 } 558