1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 #ifndef _PSB_DRV_H_ 9 #define _PSB_DRV_H_ 10 11 #include <linux/kref.h> 12 #include <linux/mm_types.h> 13 14 #include <drm/drm_device.h> 15 16 #include "gma_display.h" 17 #include "gtt.h" 18 #include "intel_bios.h" 19 #include "mmu.h" 20 #include "oaktrail.h" 21 #include "opregion.h" 22 #include "power.h" 23 #include "psb_intel_drv.h" 24 #include "psb_reg.h" 25 26 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others" 27 28 #define DRIVER_NAME "gma500" 29 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650" 30 #define DRIVER_DATE "20140314" 31 32 #define DRIVER_MAJOR 1 33 #define DRIVER_MINOR 0 34 #define DRIVER_PATCHLEVEL 0 35 36 /* Append new drm mode definition here, align with libdrm definition */ 37 #define DRM_MODE_SCALE_NO_SCALE 2 38 39 enum { 40 CHIP_PSB_8108 = 0, /* Poulsbo */ 41 CHIP_PSB_8109 = 1, /* Poulsbo */ 42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */ 43 CHIP_MFLD_0130 = 3, /* Medfield */ 44 }; 45 46 #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108) 47 #define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100) 48 #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130) 49 #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0) 50 51 /* Hardware offsets */ 52 #define PSB_VDC_OFFSET 0x00000000 53 #define PSB_VDC_SIZE 0x000080000 54 #define MRST_MMIO_SIZE 0x0000C0000 55 #define MDFLD_MMIO_SIZE 0x000100000 56 #define PSB_SGX_SIZE 0x8000 57 #define PSB_SGX_OFFSET 0x00040000 58 #define MRST_SGX_OFFSET 0x00080000 59 60 /* PCI resource identifiers */ 61 #define PSB_MMIO_RESOURCE 0 62 #define PSB_AUX_RESOURCE 0 63 #define PSB_GATT_RESOURCE 2 64 #define PSB_GTT_RESOURCE 3 65 66 /* PCI configuration */ 67 #define PSB_GMCH_CTRL 0x52 68 #define PSB_BSM 0x5C 69 #define _PSB_GMCH_ENABLED 0x4 70 #define PSB_PGETBL_CTL 0x2020 71 #define _PSB_PGETBL_ENABLED 0x00000001 72 #define PSB_SGX_2D_SLAVE_PORT 0x4000 73 #define PSB_LPC_GBA 0x44 74 75 /* TODO: To get rid of */ 76 #define PSB_TT_PRIV0_LIMIT (256*1024*1024) 77 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) 78 79 /* SGX side MMU definitions (these can probably go) */ 80 81 /* Flags for external memory type field */ 82 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ 83 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ 84 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ 85 86 /* PTE's and PDE's */ 87 #define PSB_PDE_MASK 0x003FFFFF 88 #define PSB_PDE_SHIFT 22 89 #define PSB_PTE_SHIFT 12 90 91 /* Cache control */ 92 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ 93 #define PSB_PTE_WO 0x0002 /* Write only */ 94 #define PSB_PTE_RO 0x0004 /* Read only */ 95 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ 96 97 /* VDC registers and bits */ 98 #define PSB_MSVDX_CLOCKGATING 0x2064 99 #define PSB_TOPAZ_CLOCKGATING 0x2068 100 #define PSB_HWSTAM 0x2098 101 #define PSB_INSTPM 0x20C0 102 #define PSB_INT_IDENTITY_R 0x20A4 103 #define _PSB_IRQ_ASLE (1<<0) 104 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2) 105 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) 106 #define _PSB_DPST_PIPEB_FLAG (1<<4) 107 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4) 108 #define _PSB_VSYNC_PIPEB_FLAG (1<<5) 109 #define _PSB_DPST_PIPEA_FLAG (1<<6) 110 #define _PSB_PIPEA_EVENT_FLAG (1<<6) 111 #define _PSB_VSYNC_PIPEA_FLAG (1<<7) 112 #define _MDFLD_MIPIA_FLAG (1<<16) 113 #define _MDFLD_MIPIC_FLAG (1<<17) 114 #define _PSB_IRQ_DISP_HOTSYNC (1<<17) 115 #define _PSB_IRQ_SGX_FLAG (1<<18) 116 #define _PSB_IRQ_MSVDX_FLAG (1<<19) 117 #define _LNC_IRQ_TOPAZ_FLAG (1<<20) 118 119 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ 120 _PSB_VSYNC_PIPEB_FLAG) 121 122 /* This flag includes all the display IRQ bits excepts the vblank irqs. */ 123 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \ 124 _MDFLD_PIPEB_EVENT_FLAG | \ 125 _PSB_PIPEA_EVENT_FLAG | \ 126 _PSB_VSYNC_PIPEA_FLAG | \ 127 _MDFLD_MIPIA_FLAG | \ 128 _MDFLD_MIPIC_FLAG) 129 #define PSB_INT_IDENTITY_R 0x20A4 130 #define PSB_INT_MASK_R 0x20A8 131 #define PSB_INT_ENABLE_R 0x20A0 132 133 #define _PSB_MMU_ER_MASK 0x0001FF00 134 #define _PSB_MMU_ER_HOST (1 << 16) 135 #define GPIOA 0x5010 136 #define GPIOB 0x5014 137 #define GPIOC 0x5018 138 #define GPIOD 0x501c 139 #define GPIOE 0x5020 140 #define GPIOF 0x5024 141 #define GPIOG 0x5028 142 #define GPIOH 0x502c 143 #define GPIO_CLOCK_DIR_MASK (1 << 0) 144 #define GPIO_CLOCK_DIR_IN (0 << 1) 145 #define GPIO_CLOCK_DIR_OUT (1 << 1) 146 #define GPIO_CLOCK_VAL_MASK (1 << 2) 147 #define GPIO_CLOCK_VAL_OUT (1 << 3) 148 #define GPIO_CLOCK_VAL_IN (1 << 4) 149 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 150 #define GPIO_DATA_DIR_MASK (1 << 8) 151 #define GPIO_DATA_DIR_IN (0 << 9) 152 #define GPIO_DATA_DIR_OUT (1 << 9) 153 #define GPIO_DATA_VAL_MASK (1 << 10) 154 #define GPIO_DATA_VAL_OUT (1 << 11) 155 #define GPIO_DATA_VAL_IN (1 << 12) 156 #define GPIO_DATA_PULLUP_DISABLE (1 << 13) 157 158 #define VCLK_DIVISOR_VGA0 0x6000 159 #define VCLK_DIVISOR_VGA1 0x6004 160 #define VCLK_POST_DIV 0x6010 161 162 #define PSB_COMM_2D (PSB_ENGINE_2D << 4) 163 #define PSB_COMM_3D (PSB_ENGINE_3D << 4) 164 #define PSB_COMM_TA (PSB_ENGINE_TA << 4) 165 #define PSB_COMM_HP (PSB_ENGINE_HP << 4) 166 #define PSB_COMM_USER_IRQ (1024 >> 2) 167 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) 168 #define PSB_COMM_FW (2048 >> 2) 169 170 #define PSB_UIRQ_VISTEST 1 171 #define PSB_UIRQ_OOM_REPLY 2 172 #define PSB_UIRQ_FIRE_TA_REPLY 3 173 #define PSB_UIRQ_FIRE_RASTER_REPLY 4 174 175 #define PSB_2D_SIZE (256*1024*1024) 176 #define PSB_MAX_RELOC_PAGES 1024 177 178 #define PSB_LOW_REG_OFFS 0x0204 179 #define PSB_HIGH_REG_OFFS 0x0600 180 181 #define PSB_NUM_VBLANKS 2 182 183 184 #define PSB_2D_SIZE (256*1024*1024) 185 #define PSB_MAX_RELOC_PAGES 1024 186 187 #define PSB_LOW_REG_OFFS 0x0204 188 #define PSB_HIGH_REG_OFFS 0x0600 189 190 #define PSB_NUM_VBLANKS 2 191 #define PSB_WATCHDOG_DELAY (HZ * 2) 192 #define PSB_LID_DELAY (HZ / 10) 193 194 #define MDFLD_PNW_B0 0x04 195 #define MDFLD_PNW_C0 0x08 196 197 #define MDFLD_DSR_2D_3D_0 (1 << 0) 198 #define MDFLD_DSR_2D_3D_2 (1 << 1) 199 #define MDFLD_DSR_CURSOR_0 (1 << 2) 200 #define MDFLD_DSR_CURSOR_2 (1 << 3) 201 #define MDFLD_DSR_OVERLAY_0 (1 << 4) 202 #define MDFLD_DSR_OVERLAY_2 (1 << 5) 203 #define MDFLD_DSR_MIPI_CONTROL (1 << 6) 204 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4)) 205 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5)) 206 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2) 207 208 #define MDFLD_DSR_RR 45 209 #define MDFLD_DPU_ENABLE (1 << 31) 210 #define MDFLD_DSR_FULLSCREEN (1 << 30) 211 #define MDFLD_DSR_DELAY (HZ / MDFLD_DSR_RR) 212 213 #define PSB_PWR_STATE_ON 1 214 #define PSB_PWR_STATE_OFF 2 215 216 #define PSB_PMPOLICY_NOPM 0 217 #define PSB_PMPOLICY_CLOCKGATING 1 218 #define PSB_PMPOLICY_POWERDOWN 2 219 220 #define PSB_PMSTATE_POWERUP 0 221 #define PSB_PMSTATE_CLOCKGATED 1 222 #define PSB_PMSTATE_POWERDOWN 2 223 #define PSB_PCIx_MSI_ADDR_LOC 0x94 224 #define PSB_PCIx_MSI_DATA_LOC 0x98 225 226 /* Medfield crystal settings */ 227 #define KSEL_CRYSTAL_19 1 228 #define KSEL_BYPASS_19 5 229 #define KSEL_BYPASS_25 6 230 #define KSEL_BYPASS_83_100 7 231 232 struct drm_fb_helper; 233 234 struct opregion_header; 235 struct opregion_acpi; 236 struct opregion_swsci; 237 struct opregion_asle; 238 239 struct psb_intel_opregion { 240 struct opregion_header *header; 241 struct opregion_acpi *acpi; 242 struct opregion_swsci *swsci; 243 struct opregion_asle *asle; 244 void *vbt; 245 u32 __iomem *lid_state; 246 struct work_struct asle_work; 247 }; 248 249 struct sdvo_device_mapping { 250 u8 initialized; 251 u8 dvo_port; 252 u8 slave_addr; 253 u8 dvo_wiring; 254 u8 i2c_pin; 255 u8 i2c_speed; 256 u8 ddc_pin; 257 }; 258 259 struct intel_gmbus { 260 struct i2c_adapter adapter; 261 struct i2c_adapter *force_bit; 262 u32 reg0; 263 }; 264 265 /* Register offset maps */ 266 struct psb_offset { 267 u32 fp0; 268 u32 fp1; 269 u32 cntr; 270 u32 conf; 271 u32 src; 272 u32 dpll; 273 u32 dpll_md; 274 u32 htotal; 275 u32 hblank; 276 u32 hsync; 277 u32 vtotal; 278 u32 vblank; 279 u32 vsync; 280 u32 stride; 281 u32 size; 282 u32 pos; 283 u32 surf; 284 u32 addr; 285 u32 base; 286 u32 status; 287 u32 linoff; 288 u32 tileoff; 289 u32 palette; 290 }; 291 292 /* 293 * Register save state. This is used to hold the context when the 294 * device is powered off. In the case of Oaktrail this can (but does not 295 * yet) include screen blank. Operations occuring during the save 296 * update the register cache instead. 297 */ 298 299 /* Common status for pipes */ 300 struct psb_pipe { 301 u32 fp0; 302 u32 fp1; 303 u32 cntr; 304 u32 conf; 305 u32 src; 306 u32 dpll; 307 u32 dpll_md; 308 u32 htotal; 309 u32 hblank; 310 u32 hsync; 311 u32 vtotal; 312 u32 vblank; 313 u32 vsync; 314 u32 stride; 315 u32 size; 316 u32 pos; 317 u32 base; 318 u32 surf; 319 u32 addr; 320 u32 status; 321 u32 linoff; 322 u32 tileoff; 323 u32 palette[256]; 324 }; 325 326 struct psb_state { 327 uint32_t saveVCLK_DIVISOR_VGA0; 328 uint32_t saveVCLK_DIVISOR_VGA1; 329 uint32_t saveVCLK_POST_DIV; 330 uint32_t saveVGACNTRL; 331 uint32_t saveADPA; 332 uint32_t saveLVDS; 333 uint32_t saveDVOA; 334 uint32_t saveDVOB; 335 uint32_t saveDVOC; 336 uint32_t savePP_ON; 337 uint32_t savePP_OFF; 338 uint32_t savePP_CONTROL; 339 uint32_t savePP_CYCLE; 340 uint32_t savePFIT_CONTROL; 341 uint32_t saveCLOCKGATING; 342 uint32_t saveDSPARB; 343 uint32_t savePFIT_AUTO_RATIOS; 344 uint32_t savePFIT_PGM_RATIOS; 345 uint32_t savePP_ON_DELAYS; 346 uint32_t savePP_OFF_DELAYS; 347 uint32_t savePP_DIVISOR; 348 uint32_t saveBCLRPAT_A; 349 uint32_t saveBCLRPAT_B; 350 uint32_t savePERF_MODE; 351 uint32_t saveDSPFW1; 352 uint32_t saveDSPFW2; 353 uint32_t saveDSPFW3; 354 uint32_t saveDSPFW4; 355 uint32_t saveDSPFW5; 356 uint32_t saveDSPFW6; 357 uint32_t saveCHICKENBIT; 358 uint32_t saveDSPACURSOR_CTRL; 359 uint32_t saveDSPBCURSOR_CTRL; 360 uint32_t saveDSPACURSOR_BASE; 361 uint32_t saveDSPBCURSOR_BASE; 362 uint32_t saveDSPACURSOR_POS; 363 uint32_t saveDSPBCURSOR_POS; 364 uint32_t saveOV_OVADD; 365 uint32_t saveOV_OGAMC0; 366 uint32_t saveOV_OGAMC1; 367 uint32_t saveOV_OGAMC2; 368 uint32_t saveOV_OGAMC3; 369 uint32_t saveOV_OGAMC4; 370 uint32_t saveOV_OGAMC5; 371 uint32_t saveOVC_OVADD; 372 uint32_t saveOVC_OGAMC0; 373 uint32_t saveOVC_OGAMC1; 374 uint32_t saveOVC_OGAMC2; 375 uint32_t saveOVC_OGAMC3; 376 uint32_t saveOVC_OGAMC4; 377 uint32_t saveOVC_OGAMC5; 378 379 /* DPST register save */ 380 uint32_t saveHISTOGRAM_INT_CONTROL_REG; 381 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; 382 uint32_t savePWM_CONTROL_LOGIC; 383 }; 384 385 struct medfield_state { 386 uint32_t saveMIPI; 387 uint32_t saveMIPI_C; 388 389 uint32_t savePFIT_CONTROL; 390 uint32_t savePFIT_PGM_RATIOS; 391 uint32_t saveHDMIPHYMISCCTL; 392 uint32_t saveHDMIB_CONTROL; 393 }; 394 395 struct cdv_state { 396 uint32_t saveDSPCLK_GATE_D; 397 uint32_t saveRAMCLK_GATE_D; 398 uint32_t saveDSPARB; 399 uint32_t saveDSPFW[6]; 400 uint32_t saveADPA; 401 uint32_t savePP_CONTROL; 402 uint32_t savePFIT_PGM_RATIOS; 403 uint32_t saveLVDS; 404 uint32_t savePFIT_CONTROL; 405 uint32_t savePP_ON_DELAYS; 406 uint32_t savePP_OFF_DELAYS; 407 uint32_t savePP_CYCLE; 408 uint32_t saveVGACNTRL; 409 uint32_t saveIER; 410 uint32_t saveIMR; 411 u8 saveLBB; 412 }; 413 414 struct psb_save_area { 415 struct psb_pipe pipe[3]; 416 uint32_t saveBSM; 417 uint32_t saveVBT; 418 union { 419 struct psb_state psb; 420 struct medfield_state mdfld; 421 struct cdv_state cdv; 422 }; 423 uint32_t saveBLC_PWM_CTL2; 424 uint32_t saveBLC_PWM_CTL; 425 }; 426 427 struct psb_ops; 428 429 #define PSB_NUM_PIPE 3 430 431 struct drm_psb_private { 432 struct drm_device *dev; 433 struct pci_dev *aux_pdev; /* Currently only used by mrst */ 434 struct pci_dev *lpc_pdev; /* Currently only used by mrst */ 435 const struct psb_ops *ops; 436 const struct psb_offset *regmap; 437 438 struct child_device_config *child_dev; 439 int child_dev_num; 440 441 struct psb_gtt gtt; 442 443 /* GTT Memory manager */ 444 struct psb_gtt_mm *gtt_mm; 445 struct page *scratch_page; 446 u32 __iomem *gtt_map; 447 uint32_t stolen_base; 448 u8 __iomem *vram_addr; 449 unsigned long vram_stolen_size; 450 int gtt_initialized; 451 u16 gmch_ctrl; /* Saved GTT setup */ 452 u32 pge_ctl; 453 454 struct mutex gtt_mutex; 455 struct resource *gtt_mem; /* Our PCI resource */ 456 457 struct mutex mmap_mutex; 458 459 struct psb_mmu_driver *mmu; 460 struct psb_mmu_pd *pf_pd; 461 462 /* Register base */ 463 uint8_t __iomem *sgx_reg; 464 uint8_t __iomem *vdc_reg; 465 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */ 466 uint16_t lpc_gpio_base; 467 uint32_t gatt_free_offset; 468 469 /* Fencing / irq */ 470 uint32_t vdc_irq_mask; 471 uint32_t pipestat[PSB_NUM_PIPE]; 472 473 spinlock_t irqmask_lock; 474 475 /* Power */ 476 bool suspended; 477 bool display_power; 478 int display_count; 479 480 /* Modesetting */ 481 struct psb_intel_mode_device mode_dev; 482 bool modeset; /* true if we have done the mode_device setup */ 483 484 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; 485 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; 486 uint32_t num_pipe; 487 488 /* OSPM info (Power management base) (TODO: can go ?) */ 489 uint32_t ospm_base; 490 491 /* Sizes info */ 492 u32 fuse_reg_value; 493 u32 video_device_fuse; 494 495 /* PCI revision ID for B0:D2:F0 */ 496 uint8_t platform_rev_id; 497 498 /* gmbus */ 499 struct intel_gmbus *gmbus; 500 uint8_t __iomem *gmbus_reg; 501 502 /* Used by SDVO */ 503 int crt_ddc_pin; 504 /* FIXME: The mappings should be parsed from bios but for now we can 505 pretend there are no mappings available */ 506 struct sdvo_device_mapping sdvo_mappings[2]; 507 u32 hotplug_supported_mask; 508 struct drm_property *broadcast_rgb_property; 509 struct drm_property *force_audio_property; 510 511 /* LVDS info */ 512 int backlight_duty_cycle; /* restore backlight to this value */ 513 bool panel_wants_dither; 514 struct drm_display_mode *panel_fixed_mode; 515 struct drm_display_mode *lfp_lvds_vbt_mode; 516 struct drm_display_mode *sdvo_lvds_vbt_mode; 517 518 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ 519 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */ 520 521 /* Feature bits from the VBIOS */ 522 unsigned int int_tv_support:1; 523 unsigned int lvds_dither:1; 524 unsigned int lvds_vbt:1; 525 unsigned int int_crt_support:1; 526 unsigned int lvds_use_ssc:1; 527 int lvds_ssc_freq; 528 bool is_lvds_on; 529 bool is_mipi_on; 530 bool lvds_enabled_in_vbt; 531 u32 mipi_ctrl_display; 532 533 unsigned int core_freq; 534 uint32_t iLVDS_enable; 535 536 /* Runtime PM state */ 537 int rpm_enabled; 538 539 /* MID specific */ 540 bool has_gct; 541 struct oaktrail_gct_data gct_data; 542 543 /* Oaktrail HDMI state */ 544 struct oaktrail_hdmi_dev *hdmi_priv; 545 546 /* Register state */ 547 struct psb_save_area regs; 548 549 /* MSI reg save */ 550 uint32_t msi_addr; 551 uint32_t msi_data; 552 553 /* Hotplug handling */ 554 struct work_struct hotplug_work; 555 556 /* LID-Switch */ 557 spinlock_t lid_lock; 558 struct timer_list lid_timer; 559 struct psb_intel_opregion opregion; 560 u32 lid_last_state; 561 562 /* Watchdog */ 563 uint32_t apm_reg; 564 uint16_t apm_base; 565 566 /* 567 * Used for modifying backlight from 568 * xrandr -- consider removing and using HAL instead 569 */ 570 struct backlight_device *backlight_device; 571 struct drm_property *backlight_property; 572 bool backlight_enabled; 573 int backlight_level; 574 uint32_t blc_adj1; 575 uint32_t blc_adj2; 576 577 struct drm_fb_helper *fb_helper; 578 579 /* 2D acceleration */ 580 spinlock_t lock_2d; 581 582 /* Panel brightness */ 583 int brightness; 584 int brightness_adjusted; 585 586 bool dsr_enable; 587 u32 dsr_fb_update; 588 bool dpi_panel_on[3]; 589 void *dsi_configs[2]; 590 u32 bpp; 591 u32 bpp2; 592 593 u32 pipeconf[3]; 594 u32 dspcntr[3]; 595 596 int mdfld_panel_id; 597 598 bool dplla_96mhz; /* DPLL data from the VBT */ 599 600 struct { 601 int rate; 602 int lanes; 603 int preemphasis; 604 int vswing; 605 606 bool initialized; 607 bool support; 608 int bpp; 609 struct edp_power_seq pps; 610 } edp; 611 uint8_t panel_type; 612 }; 613 614 615 /* Operations for each board type */ 616 struct psb_ops { 617 const char *name; 618 unsigned int accel_2d:1; 619 int pipes; /* Number of output pipes */ 620 int crtcs; /* Number of CRTCs */ 621 int sgx_offset; /* Base offset of SGX device */ 622 int hdmi_mask; /* Mask of HDMI CRTCs */ 623 int lvds_mask; /* Mask of LVDS CRTCs */ 624 int sdvo_mask; /* Mask of SDVO CRTCs */ 625 int cursor_needs_phys; /* If cursor base reg need physical address */ 626 627 /* Sub functions */ 628 struct drm_crtc_helper_funcs const *crtc_helper; 629 struct drm_crtc_funcs const *crtc_funcs; 630 const struct gma_clock_funcs *clock_funcs; 631 632 /* Setup hooks */ 633 int (*chip_setup)(struct drm_device *dev); 634 void (*chip_teardown)(struct drm_device *dev); 635 /* Optional helper caller after modeset */ 636 void (*errata)(struct drm_device *dev); 637 638 /* Display management hooks */ 639 int (*output_init)(struct drm_device *dev); 640 int (*hotplug)(struct drm_device *dev); 641 void (*hotplug_enable)(struct drm_device *dev, bool on); 642 /* Power management hooks */ 643 void (*init_pm)(struct drm_device *dev); 644 int (*save_regs)(struct drm_device *dev); 645 int (*restore_regs)(struct drm_device *dev); 646 void (*save_crtc)(struct drm_crtc *crtc); 647 void (*restore_crtc)(struct drm_crtc *crtc); 648 int (*power_up)(struct drm_device *dev); 649 int (*power_down)(struct drm_device *dev); 650 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc); 651 void (*disable_sr)(struct drm_device *dev); 652 653 void (*lvds_bl_power)(struct drm_device *dev, bool on); 654 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 655 /* Backlight */ 656 int (*backlight_init)(struct drm_device *dev); 657 #endif 658 int i2c_bus; /* I2C bus identifier for Moorestown */ 659 }; 660 661 662 663 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int); 664 extern int drm_pick_crtcs(struct drm_device *dev); 665 666 static inline struct drm_psb_private *psb_priv(struct drm_device *dev) 667 { 668 return (struct drm_psb_private *) dev->dev_private; 669 } 670 671 /* psb_irq.c */ 672 extern irqreturn_t psb_irq_handler(int irq, void *arg); 673 extern int psb_irq_enable_dpst(struct drm_device *dev); 674 extern int psb_irq_disable_dpst(struct drm_device *dev); 675 extern void psb_irq_preinstall(struct drm_device *dev); 676 extern int psb_irq_postinstall(struct drm_device *dev); 677 extern void psb_irq_uninstall(struct drm_device *dev); 678 extern void psb_irq_turn_on_dpst(struct drm_device *dev); 679 extern void psb_irq_turn_off_dpst(struct drm_device *dev); 680 681 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); 682 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); 683 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); 684 extern int psb_enable_vblank(struct drm_crtc *crtc); 685 extern void psb_disable_vblank(struct drm_crtc *crtc); 686 void 687 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 688 689 void 690 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 691 692 extern u32 psb_get_vblank_counter(struct drm_crtc *crtc); 693 694 /* framebuffer.c */ 695 extern int psbfb_probed(struct drm_device *dev); 696 extern int psbfb_remove(struct drm_device *dev, 697 struct drm_framebuffer *fb); 698 /* accel_2d.c */ 699 extern void psbfb_copyarea(struct fb_info *info, 700 const struct fb_copyarea *region); 701 extern int psbfb_sync(struct fb_info *info); 702 extern void psb_spank(struct drm_psb_private *dev_priv); 703 704 /* psb_reset.c */ 705 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); 706 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); 707 extern void psb_print_pagefault(struct drm_psb_private *dev_priv); 708 709 /* modesetting */ 710 extern void psb_modeset_init(struct drm_device *dev); 711 extern void psb_modeset_cleanup(struct drm_device *dev); 712 extern int psb_fbdev_init(struct drm_device *dev); 713 714 /* backlight.c */ 715 int gma_backlight_init(struct drm_device *dev); 716 void gma_backlight_exit(struct drm_device *dev); 717 void gma_backlight_disable(struct drm_device *dev); 718 void gma_backlight_enable(struct drm_device *dev); 719 void gma_backlight_set(struct drm_device *dev, int v); 720 721 /* oaktrail_crtc.c */ 722 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; 723 724 /* oaktrail_lvds.c */ 725 extern void oaktrail_lvds_init(struct drm_device *dev, 726 struct psb_intel_mode_device *mode_dev); 727 728 /* psb_intel_display.c */ 729 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; 730 extern const struct drm_crtc_funcs psb_intel_crtc_funcs; 731 732 /* psb_intel_lvds.c */ 733 extern const struct drm_connector_helper_funcs 734 psb_intel_lvds_connector_helper_funcs; 735 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; 736 737 /* gem.c */ 738 extern void psb_gem_free_object(struct drm_gem_object *obj); 739 extern int psb_gem_get_aperture(struct drm_device *dev, void *data, 740 struct drm_file *file); 741 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 742 struct drm_mode_create_dumb *args); 743 extern vm_fault_t psb_gem_fault(struct vm_fault *vmf); 744 745 /* psb_device.c */ 746 extern const struct psb_ops psb_chip_ops; 747 748 /* oaktrail_device.c */ 749 extern const struct psb_ops oaktrail_chip_ops; 750 751 /* mdlfd_device.c */ 752 extern const struct psb_ops mdfld_chip_ops; 753 754 /* cdv_device.c */ 755 extern const struct psb_ops cdv_chip_ops; 756 757 /* Debug print bits setting */ 758 #define PSB_D_GENERAL (1 << 0) 759 #define PSB_D_INIT (1 << 1) 760 #define PSB_D_IRQ (1 << 2) 761 #define PSB_D_ENTRY (1 << 3) 762 /* debug the get H/V BP/FP count */ 763 #define PSB_D_HV (1 << 4) 764 #define PSB_D_DBI_BF (1 << 5) 765 #define PSB_D_PM (1 << 6) 766 #define PSB_D_RENDER (1 << 7) 767 #define PSB_D_REG (1 << 8) 768 #define PSB_D_MSVDX (1 << 9) 769 #define PSB_D_TOPAZ (1 << 10) 770 771 extern int drm_idle_check_interval; 772 773 /* Utilities */ 774 static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset) 775 { 776 int mcr = (0xD0<<24) | (port << 16) | (offset << 8); 777 uint32_t ret_val = 0; 778 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 779 pci_write_config_dword(pci_root, 0xD0, mcr); 780 pci_read_config_dword(pci_root, 0xD4, &ret_val); 781 pci_dev_put(pci_root); 782 return ret_val; 783 } 784 static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset, 785 u32 value) 786 { 787 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; 788 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 789 pci_write_config_dword(pci_root, 0xD4, value); 790 pci_write_config_dword(pci_root, 0xD0, mcr); 791 pci_dev_put(pci_root); 792 } 793 static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset) 794 { 795 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 796 uint32_t ret_val = 0; 797 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 798 pci_write_config_dword(pci_root, 0xD0, mcr); 799 pci_read_config_dword(pci_root, 0xD4, &ret_val); 800 pci_dev_put(pci_root); 801 return ret_val; 802 } 803 static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset, 804 u32 value) 805 { 806 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 807 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 808 pci_write_config_dword(pci_root, 0xD4, value); 809 pci_write_config_dword(pci_root, 0xD0, mcr); 810 pci_dev_put(pci_root); 811 } 812 813 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) 814 { 815 struct drm_psb_private *dev_priv = dev->dev_private; 816 return ioread32(dev_priv->vdc_reg + reg); 817 } 818 819 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) 820 { 821 struct drm_psb_private *dev_priv = dev->dev_private; 822 return ioread32(dev_priv->aux_reg + reg); 823 } 824 825 #define REG_READ(reg) REGISTER_READ(dev, (reg)) 826 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg)) 827 828 /* Useful for post reads */ 829 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, 830 uint32_t reg, int aux) 831 { 832 uint32_t val; 833 834 if (aux) 835 val = REG_READ_AUX(reg); 836 else 837 val = REG_READ(reg); 838 839 return val; 840 } 841 842 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux)) 843 844 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, 845 uint32_t val) 846 { 847 struct drm_psb_private *dev_priv = dev->dev_private; 848 iowrite32((val), dev_priv->vdc_reg + (reg)); 849 } 850 851 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, 852 uint32_t val) 853 { 854 struct drm_psb_private *dev_priv = dev->dev_private; 855 iowrite32((val), dev_priv->aux_reg + (reg)); 856 } 857 858 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) 859 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) 860 861 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, 862 uint32_t val, int aux) 863 { 864 if (aux) 865 REG_WRITE_AUX(reg, val); 866 else 867 REG_WRITE(reg, val); 868 } 869 870 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) 871 872 static inline void REGISTER_WRITE16(struct drm_device *dev, 873 uint32_t reg, uint32_t val) 874 { 875 struct drm_psb_private *dev_priv = dev->dev_private; 876 iowrite16((val), dev_priv->vdc_reg + (reg)); 877 } 878 879 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) 880 881 static inline void REGISTER_WRITE8(struct drm_device *dev, 882 uint32_t reg, uint32_t val) 883 { 884 struct drm_psb_private *dev_priv = dev->dev_private; 885 iowrite8((val), dev_priv->vdc_reg + (reg)); 886 } 887 888 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) 889 890 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) 891 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) 892 893 /* #define TRAP_SGX_PM_FAULT 1 */ 894 #ifdef TRAP_SGX_PM_FAULT 895 #define PSB_RSGX32(_offs) \ 896 ({ \ 897 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ 898 pr_err("access sgx when it's off!! (READ) %s, %d\n", \ 899 __FILE__, __LINE__); \ 900 melay(1000); \ 901 } \ 902 ioread32(dev_priv->sgx_reg + (_offs)); \ 903 }) 904 #else 905 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) 906 #endif 907 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) 908 909 #define MSVDX_REG_DUMP 0 910 911 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) 912 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) 913 914 #endif 915