1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 #ifndef _PSB_DRV_H_ 9 #define _PSB_DRV_H_ 10 11 #include <linux/kref.h> 12 #include <linux/mm_types.h> 13 14 #include <drm/drm_device.h> 15 16 #include "gtt.h" 17 #include "intel_bios.h" 18 #include "mmu.h" 19 #include "oaktrail.h" 20 #include "opregion.h" 21 #include "power.h" 22 #include "psb_intel_drv.h" 23 #include "psb_reg.h" 24 25 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others" 26 27 #define DRIVER_NAME "gma500" 28 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650" 29 #define DRIVER_DATE "20140314" 30 31 #define DRIVER_MAJOR 1 32 #define DRIVER_MINOR 0 33 #define DRIVER_PATCHLEVEL 0 34 35 /* Append new drm mode definition here, align with libdrm definition */ 36 #define DRM_MODE_SCALE_NO_SCALE 2 37 38 #define IS_PSB(drm) ((to_pci_dev((drm)->dev)->device & 0xfffe) == 0x8108) 39 #define IS_MRST(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x4100) 40 #define IS_CDV(drm) ((to_pci_dev((drm)->dev)->device & 0xfff0) == 0x0be0) 41 42 /* Hardware offsets */ 43 #define PSB_VDC_OFFSET 0x00000000 44 #define PSB_VDC_SIZE 0x000080000 45 #define MRST_MMIO_SIZE 0x0000C0000 46 #define PSB_SGX_SIZE 0x8000 47 #define PSB_SGX_OFFSET 0x00040000 48 #define MRST_SGX_OFFSET 0x00080000 49 50 /* PCI resource identifiers */ 51 #define PSB_MMIO_RESOURCE 0 52 #define PSB_AUX_RESOURCE 0 53 #define PSB_GATT_RESOURCE 2 54 #define PSB_GTT_RESOURCE 3 55 56 /* PCI configuration */ 57 #define PSB_GMCH_CTRL 0x52 58 #define PSB_BSM 0x5C 59 #define _PSB_GMCH_ENABLED 0x4 60 #define PSB_PGETBL_CTL 0x2020 61 #define _PSB_PGETBL_ENABLED 0x00000001 62 #define PSB_SGX_2D_SLAVE_PORT 0x4000 63 #define PSB_LPC_GBA 0x44 64 65 /* TODO: To get rid of */ 66 #define PSB_TT_PRIV0_LIMIT (256*1024*1024) 67 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) 68 69 /* SGX side MMU definitions (these can probably go) */ 70 71 /* Flags for external memory type field */ 72 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ 73 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ 74 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ 75 76 /* PTE's and PDE's */ 77 #define PSB_PDE_MASK 0x003FFFFF 78 #define PSB_PDE_SHIFT 22 79 #define PSB_PTE_SHIFT 12 80 81 /* Cache control */ 82 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ 83 #define PSB_PTE_WO 0x0002 /* Write only */ 84 #define PSB_PTE_RO 0x0004 /* Read only */ 85 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ 86 87 /* VDC registers and bits */ 88 #define PSB_MSVDX_CLOCKGATING 0x2064 89 #define PSB_TOPAZ_CLOCKGATING 0x2068 90 #define PSB_HWSTAM 0x2098 91 #define PSB_INSTPM 0x20C0 92 #define PSB_INT_IDENTITY_R 0x20A4 93 #define _PSB_IRQ_ASLE (1<<0) 94 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2) 95 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) 96 #define _PSB_DPST_PIPEB_FLAG (1<<4) 97 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4) 98 #define _PSB_VSYNC_PIPEB_FLAG (1<<5) 99 #define _PSB_DPST_PIPEA_FLAG (1<<6) 100 #define _PSB_PIPEA_EVENT_FLAG (1<<6) 101 #define _PSB_VSYNC_PIPEA_FLAG (1<<7) 102 #define _PSB_IRQ_DISP_HOTSYNC (1<<17) 103 #define _PSB_IRQ_SGX_FLAG (1<<18) 104 #define _PSB_IRQ_MSVDX_FLAG (1<<19) 105 #define _LNC_IRQ_TOPAZ_FLAG (1<<20) 106 107 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ 108 _PSB_VSYNC_PIPEB_FLAG) 109 110 #define PSB_INT_IDENTITY_R 0x20A4 111 #define PSB_INT_MASK_R 0x20A8 112 #define PSB_INT_ENABLE_R 0x20A0 113 114 #define _PSB_MMU_ER_MASK 0x0001FF00 115 #define _PSB_MMU_ER_HOST (1 << 16) 116 #define GPIOA 0x5010 117 #define GPIOB 0x5014 118 #define GPIOC 0x5018 119 #define GPIOD 0x501c 120 #define GPIOE 0x5020 121 #define GPIOF 0x5024 122 #define GPIOG 0x5028 123 #define GPIOH 0x502c 124 #define GPIO_CLOCK_DIR_MASK (1 << 0) 125 #define GPIO_CLOCK_DIR_IN (0 << 1) 126 #define GPIO_CLOCK_DIR_OUT (1 << 1) 127 #define GPIO_CLOCK_VAL_MASK (1 << 2) 128 #define GPIO_CLOCK_VAL_OUT (1 << 3) 129 #define GPIO_CLOCK_VAL_IN (1 << 4) 130 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 131 #define GPIO_DATA_DIR_MASK (1 << 8) 132 #define GPIO_DATA_DIR_IN (0 << 9) 133 #define GPIO_DATA_DIR_OUT (1 << 9) 134 #define GPIO_DATA_VAL_MASK (1 << 10) 135 #define GPIO_DATA_VAL_OUT (1 << 11) 136 #define GPIO_DATA_VAL_IN (1 << 12) 137 #define GPIO_DATA_PULLUP_DISABLE (1 << 13) 138 139 #define VCLK_DIVISOR_VGA0 0x6000 140 #define VCLK_DIVISOR_VGA1 0x6004 141 #define VCLK_POST_DIV 0x6010 142 143 #define PSB_COMM_2D (PSB_ENGINE_2D << 4) 144 #define PSB_COMM_3D (PSB_ENGINE_3D << 4) 145 #define PSB_COMM_TA (PSB_ENGINE_TA << 4) 146 #define PSB_COMM_HP (PSB_ENGINE_HP << 4) 147 #define PSB_COMM_USER_IRQ (1024 >> 2) 148 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) 149 #define PSB_COMM_FW (2048 >> 2) 150 151 #define PSB_UIRQ_VISTEST 1 152 #define PSB_UIRQ_OOM_REPLY 2 153 #define PSB_UIRQ_FIRE_TA_REPLY 3 154 #define PSB_UIRQ_FIRE_RASTER_REPLY 4 155 156 #define PSB_2D_SIZE (256*1024*1024) 157 #define PSB_MAX_RELOC_PAGES 1024 158 159 #define PSB_LOW_REG_OFFS 0x0204 160 #define PSB_HIGH_REG_OFFS 0x0600 161 162 #define PSB_NUM_VBLANKS 2 163 164 165 #define PSB_2D_SIZE (256*1024*1024) 166 #define PSB_MAX_RELOC_PAGES 1024 167 168 #define PSB_LOW_REG_OFFS 0x0204 169 #define PSB_HIGH_REG_OFFS 0x0600 170 171 #define PSB_NUM_VBLANKS 2 172 #define PSB_WATCHDOG_DELAY (HZ * 2) 173 174 #define PSB_MAX_BRIGHTNESS 100 175 176 #define PSB_PWR_STATE_ON 1 177 #define PSB_PWR_STATE_OFF 2 178 179 #define PSB_PMPOLICY_NOPM 0 180 #define PSB_PMPOLICY_CLOCKGATING 1 181 #define PSB_PMPOLICY_POWERDOWN 2 182 183 #define PSB_PMSTATE_POWERUP 0 184 #define PSB_PMSTATE_CLOCKGATED 1 185 #define PSB_PMSTATE_POWERDOWN 2 186 #define PSB_PCIx_MSI_ADDR_LOC 0x94 187 #define PSB_PCIx_MSI_DATA_LOC 0x98 188 189 /* Medfield crystal settings */ 190 #define KSEL_CRYSTAL_19 1 191 #define KSEL_BYPASS_19 5 192 #define KSEL_BYPASS_25 6 193 #define KSEL_BYPASS_83_100 7 194 195 struct opregion_header; 196 struct opregion_acpi; 197 struct opregion_swsci; 198 struct opregion_asle; 199 200 struct psb_intel_opregion { 201 struct opregion_header *header; 202 struct opregion_acpi *acpi; 203 struct opregion_swsci *swsci; 204 struct opregion_asle *asle; 205 void *vbt; 206 u32 __iomem *lid_state; 207 struct work_struct asle_work; 208 }; 209 210 struct sdvo_device_mapping { 211 u8 initialized; 212 u8 dvo_port; 213 u8 slave_addr; 214 u8 dvo_wiring; 215 u8 i2c_pin; 216 u8 i2c_speed; 217 u8 ddc_pin; 218 }; 219 220 struct intel_gmbus { 221 struct i2c_adapter adapter; 222 struct i2c_adapter *force_bit; 223 u32 reg0; 224 }; 225 226 /* Register offset maps */ 227 struct psb_offset { 228 u32 fp0; 229 u32 fp1; 230 u32 cntr; 231 u32 conf; 232 u32 src; 233 u32 dpll; 234 u32 dpll_md; 235 u32 htotal; 236 u32 hblank; 237 u32 hsync; 238 u32 vtotal; 239 u32 vblank; 240 u32 vsync; 241 u32 stride; 242 u32 size; 243 u32 pos; 244 u32 surf; 245 u32 addr; 246 u32 base; 247 u32 status; 248 u32 linoff; 249 u32 tileoff; 250 u32 palette; 251 }; 252 253 /* 254 * Register save state. This is used to hold the context when the 255 * device is powered off. In the case of Oaktrail this can (but does not 256 * yet) include screen blank. Operations occuring during the save 257 * update the register cache instead. 258 */ 259 260 /* Common status for pipes */ 261 struct psb_pipe { 262 u32 fp0; 263 u32 fp1; 264 u32 cntr; 265 u32 conf; 266 u32 src; 267 u32 dpll; 268 u32 dpll_md; 269 u32 htotal; 270 u32 hblank; 271 u32 hsync; 272 u32 vtotal; 273 u32 vblank; 274 u32 vsync; 275 u32 stride; 276 u32 size; 277 u32 pos; 278 u32 base; 279 u32 surf; 280 u32 addr; 281 u32 status; 282 u32 linoff; 283 u32 tileoff; 284 u32 palette[256]; 285 }; 286 287 struct psb_state { 288 uint32_t saveVCLK_DIVISOR_VGA0; 289 uint32_t saveVCLK_DIVISOR_VGA1; 290 uint32_t saveVCLK_POST_DIV; 291 uint32_t saveVGACNTRL; 292 uint32_t saveADPA; 293 uint32_t saveLVDS; 294 uint32_t saveDVOA; 295 uint32_t saveDVOB; 296 uint32_t saveDVOC; 297 uint32_t savePP_ON; 298 uint32_t savePP_OFF; 299 uint32_t savePP_CONTROL; 300 uint32_t savePP_CYCLE; 301 uint32_t savePFIT_CONTROL; 302 uint32_t saveCLOCKGATING; 303 uint32_t saveDSPARB; 304 uint32_t savePFIT_AUTO_RATIOS; 305 uint32_t savePFIT_PGM_RATIOS; 306 uint32_t savePP_ON_DELAYS; 307 uint32_t savePP_OFF_DELAYS; 308 uint32_t savePP_DIVISOR; 309 uint32_t saveBCLRPAT_A; 310 uint32_t saveBCLRPAT_B; 311 uint32_t savePERF_MODE; 312 uint32_t saveDSPFW1; 313 uint32_t saveDSPFW2; 314 uint32_t saveDSPFW3; 315 uint32_t saveDSPFW4; 316 uint32_t saveDSPFW5; 317 uint32_t saveDSPFW6; 318 uint32_t saveCHICKENBIT; 319 uint32_t saveDSPACURSOR_CTRL; 320 uint32_t saveDSPBCURSOR_CTRL; 321 uint32_t saveDSPACURSOR_BASE; 322 uint32_t saveDSPBCURSOR_BASE; 323 uint32_t saveDSPACURSOR_POS; 324 uint32_t saveDSPBCURSOR_POS; 325 uint32_t saveOV_OVADD; 326 uint32_t saveOV_OGAMC0; 327 uint32_t saveOV_OGAMC1; 328 uint32_t saveOV_OGAMC2; 329 uint32_t saveOV_OGAMC3; 330 uint32_t saveOV_OGAMC4; 331 uint32_t saveOV_OGAMC5; 332 uint32_t saveOVC_OVADD; 333 uint32_t saveOVC_OGAMC0; 334 uint32_t saveOVC_OGAMC1; 335 uint32_t saveOVC_OGAMC2; 336 uint32_t saveOVC_OGAMC3; 337 uint32_t saveOVC_OGAMC4; 338 uint32_t saveOVC_OGAMC5; 339 340 /* DPST register save */ 341 uint32_t saveHISTOGRAM_INT_CONTROL_REG; 342 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; 343 uint32_t savePWM_CONTROL_LOGIC; 344 }; 345 346 struct cdv_state { 347 uint32_t saveDSPCLK_GATE_D; 348 uint32_t saveRAMCLK_GATE_D; 349 uint32_t saveDSPARB; 350 uint32_t saveDSPFW[6]; 351 uint32_t saveADPA; 352 uint32_t savePP_CONTROL; 353 uint32_t savePFIT_PGM_RATIOS; 354 uint32_t saveLVDS; 355 uint32_t savePFIT_CONTROL; 356 uint32_t savePP_ON_DELAYS; 357 uint32_t savePP_OFF_DELAYS; 358 uint32_t savePP_CYCLE; 359 uint32_t saveVGACNTRL; 360 uint32_t saveIER; 361 uint32_t saveIMR; 362 u8 saveLBB; 363 }; 364 365 struct psb_save_area { 366 struct psb_pipe pipe[3]; 367 uint32_t saveBSM; 368 uint32_t saveVBT; 369 union { 370 struct psb_state psb; 371 struct cdv_state cdv; 372 }; 373 uint32_t saveBLC_PWM_CTL2; 374 uint32_t saveBLC_PWM_CTL; 375 }; 376 377 struct psb_ops; 378 379 #define PSB_NUM_PIPE 3 380 381 struct intel_scu_ipc_dev; 382 383 struct drm_psb_private { 384 struct drm_device dev; 385 386 struct pci_dev *aux_pdev; /* Currently only used by mrst */ 387 struct pci_dev *lpc_pdev; /* Currently only used by mrst */ 388 const struct psb_ops *ops; 389 const struct psb_offset *regmap; 390 391 struct child_device_config *child_dev; 392 int child_dev_num; 393 394 struct psb_gtt gtt; 395 396 /* GTT Memory manager */ 397 struct psb_gtt_mm *gtt_mm; 398 struct page *scratch_page; 399 u32 __iomem *gtt_map; 400 uint32_t stolen_base; 401 u8 __iomem *vram_addr; 402 unsigned long vram_stolen_size; 403 u16 gmch_ctrl; /* Saved GTT setup */ 404 u32 pge_ctl; 405 406 struct mutex gtt_mutex; 407 struct resource *gtt_mem; /* Our PCI resource */ 408 409 struct mutex mmap_mutex; 410 411 struct psb_mmu_driver *mmu; 412 struct psb_mmu_pd *pf_pd; 413 414 /* Register base */ 415 uint8_t __iomem *sgx_reg; 416 uint8_t __iomem *vdc_reg; 417 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */ 418 uint16_t lpc_gpio_base; 419 uint32_t gatt_free_offset; 420 421 /* Fencing / irq */ 422 uint32_t vdc_irq_mask; 423 uint32_t pipestat[PSB_NUM_PIPE]; 424 425 spinlock_t irqmask_lock; 426 bool irq_enabled; 427 428 /* Power */ 429 bool pm_initialized; 430 431 /* Modesetting */ 432 struct psb_intel_mode_device mode_dev; 433 bool modeset; /* true if we have done the mode_device setup */ 434 435 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; 436 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; 437 uint32_t num_pipe; 438 439 /* OSPM info (Power management base) (TODO: can go ?) */ 440 uint32_t ospm_base; 441 442 /* Sizes info */ 443 u32 fuse_reg_value; 444 u32 video_device_fuse; 445 446 /* PCI revision ID for B0:D2:F0 */ 447 uint8_t platform_rev_id; 448 449 /* gmbus */ 450 struct intel_gmbus *gmbus; 451 uint8_t __iomem *gmbus_reg; 452 453 /* Used by SDVO */ 454 int crt_ddc_pin; 455 /* FIXME: The mappings should be parsed from bios but for now we can 456 pretend there are no mappings available */ 457 struct sdvo_device_mapping sdvo_mappings[2]; 458 u32 hotplug_supported_mask; 459 struct drm_property *broadcast_rgb_property; 460 struct drm_property *force_audio_property; 461 462 /* LVDS info */ 463 int backlight_duty_cycle; /* restore backlight to this value */ 464 bool panel_wants_dither; 465 struct drm_display_mode *panel_fixed_mode; 466 struct drm_display_mode *lfp_lvds_vbt_mode; 467 struct drm_display_mode *sdvo_lvds_vbt_mode; 468 469 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ 470 struct gma_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */ 471 472 /* Feature bits from the VBIOS */ 473 unsigned int int_tv_support:1; 474 unsigned int lvds_dither:1; 475 unsigned int lvds_vbt:1; 476 unsigned int int_crt_support:1; 477 unsigned int lvds_use_ssc:1; 478 int lvds_ssc_freq; 479 bool is_lvds_on; 480 bool is_mipi_on; 481 bool lvds_enabled_in_vbt; 482 u32 mipi_ctrl_display; 483 484 unsigned int core_freq; 485 uint32_t iLVDS_enable; 486 487 /* MID specific */ 488 bool use_msi; 489 bool has_gct; 490 struct oaktrail_gct_data gct_data; 491 492 /* Oaktrail HDMI state */ 493 struct oaktrail_hdmi_dev *hdmi_priv; 494 495 /* Register state */ 496 struct psb_save_area regs; 497 498 /* Hotplug handling */ 499 struct work_struct hotplug_work; 500 501 struct psb_intel_opregion opregion; 502 503 /* Watchdog */ 504 uint32_t apm_reg; 505 uint16_t apm_base; 506 507 /* 508 * Used for modifying backlight from 509 * xrandr -- consider removing and using HAL instead 510 */ 511 struct intel_scu_ipc_dev *scu; 512 struct backlight_device *backlight_device; 513 struct drm_property *backlight_property; 514 bool backlight_enabled; 515 int backlight_level; 516 uint32_t blc_adj1; 517 uint32_t blc_adj2; 518 519 bool dsr_enable; 520 u32 dsr_fb_update; 521 bool dpi_panel_on[3]; 522 void *dsi_configs[2]; 523 u32 bpp; 524 u32 bpp2; 525 526 u32 pipeconf[3]; 527 u32 dspcntr[3]; 528 529 bool dplla_96mhz; /* DPLL data from the VBT */ 530 531 struct { 532 int rate; 533 int lanes; 534 int preemphasis; 535 int vswing; 536 537 bool initialized; 538 bool support; 539 int bpp; 540 struct edp_power_seq pps; 541 } edp; 542 uint8_t panel_type; 543 }; 544 545 static inline struct drm_psb_private *to_drm_psb_private(struct drm_device *dev) 546 { 547 return container_of(dev, struct drm_psb_private, dev); 548 } 549 550 /* Operations for each board type */ 551 struct psb_ops { 552 const char *name; 553 int pipes; /* Number of output pipes */ 554 int crtcs; /* Number of CRTCs */ 555 int sgx_offset; /* Base offset of SGX device */ 556 int hdmi_mask; /* Mask of HDMI CRTCs */ 557 int lvds_mask; /* Mask of LVDS CRTCs */ 558 int sdvo_mask; /* Mask of SDVO CRTCs */ 559 int cursor_needs_phys; /* If cursor base reg need physical address */ 560 561 /* Sub functions */ 562 struct drm_crtc_helper_funcs const *crtc_helper; 563 const struct gma_clock_funcs *clock_funcs; 564 565 /* Setup hooks */ 566 int (*chip_setup)(struct drm_device *dev); 567 void (*chip_teardown)(struct drm_device *dev); 568 /* Optional helper caller after modeset */ 569 void (*errata)(struct drm_device *dev); 570 571 /* Display management hooks */ 572 int (*output_init)(struct drm_device *dev); 573 int (*hotplug)(struct drm_device *dev); 574 void (*hotplug_enable)(struct drm_device *dev, bool on); 575 /* Power management hooks */ 576 void (*init_pm)(struct drm_device *dev); 577 int (*save_regs)(struct drm_device *dev); 578 int (*restore_regs)(struct drm_device *dev); 579 void (*save_crtc)(struct drm_crtc *crtc); 580 void (*restore_crtc)(struct drm_crtc *crtc); 581 int (*power_up)(struct drm_device *dev); 582 int (*power_down)(struct drm_device *dev); 583 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc); 584 void (*disable_sr)(struct drm_device *dev); 585 586 void (*lvds_bl_power)(struct drm_device *dev, bool on); 587 588 /* Backlight */ 589 int (*backlight_init)(struct drm_device *dev); 590 void (*backlight_set)(struct drm_device *dev, int level); 591 int (*backlight_get)(struct drm_device *dev); 592 const char *backlight_name; 593 594 int i2c_bus; /* I2C bus identifier for Moorestown */ 595 }; 596 597 /* modesetting */ 598 extern void psb_modeset_init(struct drm_device *dev); 599 extern void psb_modeset_cleanup(struct drm_device *dev); 600 601 /* framebuffer */ 602 struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev, 603 const struct drm_mode_fb_cmd2 *mode_cmd, 604 struct drm_gem_object *obj); 605 606 /* fbdev */ 607 #if defined(CONFIG_DRM_FBDEV_EMULATION) 608 void psb_fbdev_setup(struct drm_psb_private *dev_priv); 609 #else 610 static inline void psb_fbdev_setup(struct drm_psb_private *dev_priv) 611 { } 612 #endif 613 614 /* backlight.c */ 615 int gma_backlight_init(struct drm_device *dev); 616 void gma_backlight_exit(struct drm_device *dev); 617 void gma_backlight_disable(struct drm_device *dev); 618 void gma_backlight_enable(struct drm_device *dev); 619 void gma_backlight_set(struct drm_device *dev, int v); 620 621 /* oaktrail_crtc.c */ 622 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; 623 624 /* oaktrail_lvds.c */ 625 extern void oaktrail_lvds_init(struct drm_device *dev, 626 struct psb_intel_mode_device *mode_dev); 627 628 /* psb_intel_display.c */ 629 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; 630 631 /* psb_intel_lvds.c */ 632 extern const struct drm_connector_helper_funcs 633 psb_intel_lvds_connector_helper_funcs; 634 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; 635 636 /* gem.c */ 637 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 638 struct drm_mode_create_dumb *args); 639 640 /* psb_device.c */ 641 extern const struct psb_ops psb_chip_ops; 642 643 /* oaktrail_device.c */ 644 extern const struct psb_ops oaktrail_chip_ops; 645 646 /* cdv_device.c */ 647 extern const struct psb_ops cdv_chip_ops; 648 649 /* Utilities */ 650 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) 651 { 652 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 653 return ioread32(dev_priv->vdc_reg + reg); 654 } 655 656 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) 657 { 658 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 659 return ioread32(dev_priv->aux_reg + reg); 660 } 661 662 #define REG_READ(reg) REGISTER_READ(dev, (reg)) 663 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg)) 664 665 /* Useful for post reads */ 666 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, 667 uint32_t reg, int aux) 668 { 669 uint32_t val; 670 671 if (aux) 672 val = REG_READ_AUX(reg); 673 else 674 val = REG_READ(reg); 675 676 return val; 677 } 678 679 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux)) 680 681 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, 682 uint32_t val) 683 { 684 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 685 iowrite32((val), dev_priv->vdc_reg + (reg)); 686 } 687 688 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, 689 uint32_t val) 690 { 691 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 692 iowrite32((val), dev_priv->aux_reg + (reg)); 693 } 694 695 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) 696 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) 697 698 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, 699 uint32_t val, int aux) 700 { 701 if (aux) 702 REG_WRITE_AUX(reg, val); 703 else 704 REG_WRITE(reg, val); 705 } 706 707 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) 708 709 static inline void REGISTER_WRITE16(struct drm_device *dev, 710 uint32_t reg, uint32_t val) 711 { 712 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 713 iowrite16((val), dev_priv->vdc_reg + (reg)); 714 } 715 716 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) 717 718 static inline void REGISTER_WRITE8(struct drm_device *dev, 719 uint32_t reg, uint32_t val) 720 { 721 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 722 iowrite8((val), dev_priv->vdc_reg + (reg)); 723 } 724 725 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) 726 727 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) 728 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) 729 730 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) 731 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) 732 733 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) 734 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) 735 736 #endif 737