1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 #ifndef _PSB_DRV_H_ 9 #define _PSB_DRV_H_ 10 11 #include <linux/kref.h> 12 #include <linux/mm_types.h> 13 14 #include <drm/drmP.h> 15 #include <drm/gma_drm.h> 16 #include "psb_reg.h" 17 #include "psb_intel_drv.h" 18 #include "gma_display.h" 19 #include "intel_bios.h" 20 #include "gtt.h" 21 #include "power.h" 22 #include "opregion.h" 23 #include "oaktrail.h" 24 #include "mmu.h" 25 26 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others" 27 28 #define DRIVER_NAME "gma500" 29 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650" 30 #define DRIVER_DATE "20140314" 31 32 #define DRIVER_MAJOR 1 33 #define DRIVER_MINOR 0 34 #define DRIVER_PATCHLEVEL 0 35 36 /* Append new drm mode definition here, align with libdrm definition */ 37 #define DRM_MODE_SCALE_NO_SCALE 2 38 39 enum { 40 CHIP_PSB_8108 = 0, /* Poulsbo */ 41 CHIP_PSB_8109 = 1, /* Poulsbo */ 42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */ 43 CHIP_MFLD_0130 = 3, /* Medfield */ 44 }; 45 46 #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108) 47 #define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100) 48 #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130) 49 #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0) 50 51 /* Hardware offsets */ 52 #define PSB_VDC_OFFSET 0x00000000 53 #define PSB_VDC_SIZE 0x000080000 54 #define MRST_MMIO_SIZE 0x0000C0000 55 #define MDFLD_MMIO_SIZE 0x000100000 56 #define PSB_SGX_SIZE 0x8000 57 #define PSB_SGX_OFFSET 0x00040000 58 #define MRST_SGX_OFFSET 0x00080000 59 60 /* PCI resource identifiers */ 61 #define PSB_MMIO_RESOURCE 0 62 #define PSB_AUX_RESOURCE 0 63 #define PSB_GATT_RESOURCE 2 64 #define PSB_GTT_RESOURCE 3 65 66 /* PCI configuration */ 67 #define PSB_GMCH_CTRL 0x52 68 #define PSB_BSM 0x5C 69 #define _PSB_GMCH_ENABLED 0x4 70 #define PSB_PGETBL_CTL 0x2020 71 #define _PSB_PGETBL_ENABLED 0x00000001 72 #define PSB_SGX_2D_SLAVE_PORT 0x4000 73 #define PSB_LPC_GBA 0x44 74 75 /* TODO: To get rid of */ 76 #define PSB_TT_PRIV0_LIMIT (256*1024*1024) 77 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) 78 79 /* SGX side MMU definitions (these can probably go) */ 80 81 /* Flags for external memory type field */ 82 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ 83 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ 84 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ 85 86 /* PTE's and PDE's */ 87 #define PSB_PDE_MASK 0x003FFFFF 88 #define PSB_PDE_SHIFT 22 89 #define PSB_PTE_SHIFT 12 90 91 /* Cache control */ 92 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ 93 #define PSB_PTE_WO 0x0002 /* Write only */ 94 #define PSB_PTE_RO 0x0004 /* Read only */ 95 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ 96 97 /* VDC registers and bits */ 98 #define PSB_MSVDX_CLOCKGATING 0x2064 99 #define PSB_TOPAZ_CLOCKGATING 0x2068 100 #define PSB_HWSTAM 0x2098 101 #define PSB_INSTPM 0x20C0 102 #define PSB_INT_IDENTITY_R 0x20A4 103 #define _PSB_IRQ_ASLE (1<<0) 104 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2) 105 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3) 106 #define _PSB_DPST_PIPEB_FLAG (1<<4) 107 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4) 108 #define _PSB_VSYNC_PIPEB_FLAG (1<<5) 109 #define _PSB_DPST_PIPEA_FLAG (1<<6) 110 #define _PSB_PIPEA_EVENT_FLAG (1<<6) 111 #define _PSB_VSYNC_PIPEA_FLAG (1<<7) 112 #define _MDFLD_MIPIA_FLAG (1<<16) 113 #define _MDFLD_MIPIC_FLAG (1<<17) 114 #define _PSB_IRQ_DISP_HOTSYNC (1<<17) 115 #define _PSB_IRQ_SGX_FLAG (1<<18) 116 #define _PSB_IRQ_MSVDX_FLAG (1<<19) 117 #define _LNC_IRQ_TOPAZ_FLAG (1<<20) 118 119 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \ 120 _PSB_VSYNC_PIPEB_FLAG) 121 122 /* This flag includes all the display IRQ bits excepts the vblank irqs. */ 123 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \ 124 _MDFLD_PIPEB_EVENT_FLAG | \ 125 _PSB_PIPEA_EVENT_FLAG | \ 126 _PSB_VSYNC_PIPEA_FLAG | \ 127 _MDFLD_MIPIA_FLAG | \ 128 _MDFLD_MIPIC_FLAG) 129 #define PSB_INT_IDENTITY_R 0x20A4 130 #define PSB_INT_MASK_R 0x20A8 131 #define PSB_INT_ENABLE_R 0x20A0 132 133 #define _PSB_MMU_ER_MASK 0x0001FF00 134 #define _PSB_MMU_ER_HOST (1 << 16) 135 #define GPIOA 0x5010 136 #define GPIOB 0x5014 137 #define GPIOC 0x5018 138 #define GPIOD 0x501c 139 #define GPIOE 0x5020 140 #define GPIOF 0x5024 141 #define GPIOG 0x5028 142 #define GPIOH 0x502c 143 #define GPIO_CLOCK_DIR_MASK (1 << 0) 144 #define GPIO_CLOCK_DIR_IN (0 << 1) 145 #define GPIO_CLOCK_DIR_OUT (1 << 1) 146 #define GPIO_CLOCK_VAL_MASK (1 << 2) 147 #define GPIO_CLOCK_VAL_OUT (1 << 3) 148 #define GPIO_CLOCK_VAL_IN (1 << 4) 149 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 150 #define GPIO_DATA_DIR_MASK (1 << 8) 151 #define GPIO_DATA_DIR_IN (0 << 9) 152 #define GPIO_DATA_DIR_OUT (1 << 9) 153 #define GPIO_DATA_VAL_MASK (1 << 10) 154 #define GPIO_DATA_VAL_OUT (1 << 11) 155 #define GPIO_DATA_VAL_IN (1 << 12) 156 #define GPIO_DATA_PULLUP_DISABLE (1 << 13) 157 158 #define VCLK_DIVISOR_VGA0 0x6000 159 #define VCLK_DIVISOR_VGA1 0x6004 160 #define VCLK_POST_DIV 0x6010 161 162 #define PSB_COMM_2D (PSB_ENGINE_2D << 4) 163 #define PSB_COMM_3D (PSB_ENGINE_3D << 4) 164 #define PSB_COMM_TA (PSB_ENGINE_TA << 4) 165 #define PSB_COMM_HP (PSB_ENGINE_HP << 4) 166 #define PSB_COMM_USER_IRQ (1024 >> 2) 167 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) 168 #define PSB_COMM_FW (2048 >> 2) 169 170 #define PSB_UIRQ_VISTEST 1 171 #define PSB_UIRQ_OOM_REPLY 2 172 #define PSB_UIRQ_FIRE_TA_REPLY 3 173 #define PSB_UIRQ_FIRE_RASTER_REPLY 4 174 175 #define PSB_2D_SIZE (256*1024*1024) 176 #define PSB_MAX_RELOC_PAGES 1024 177 178 #define PSB_LOW_REG_OFFS 0x0204 179 #define PSB_HIGH_REG_OFFS 0x0600 180 181 #define PSB_NUM_VBLANKS 2 182 183 184 #define PSB_2D_SIZE (256*1024*1024) 185 #define PSB_MAX_RELOC_PAGES 1024 186 187 #define PSB_LOW_REG_OFFS 0x0204 188 #define PSB_HIGH_REG_OFFS 0x0600 189 190 #define PSB_NUM_VBLANKS 2 191 #define PSB_WATCHDOG_DELAY (HZ * 2) 192 #define PSB_LID_DELAY (HZ / 10) 193 194 #define MDFLD_PNW_B0 0x04 195 #define MDFLD_PNW_C0 0x08 196 197 #define MDFLD_DSR_2D_3D_0 (1 << 0) 198 #define MDFLD_DSR_2D_3D_2 (1 << 1) 199 #define MDFLD_DSR_CURSOR_0 (1 << 2) 200 #define MDFLD_DSR_CURSOR_2 (1 << 3) 201 #define MDFLD_DSR_OVERLAY_0 (1 << 4) 202 #define MDFLD_DSR_OVERLAY_2 (1 << 5) 203 #define MDFLD_DSR_MIPI_CONTROL (1 << 6) 204 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4)) 205 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5)) 206 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2) 207 208 #define MDFLD_DSR_RR 45 209 #define MDFLD_DPU_ENABLE (1 << 31) 210 #define MDFLD_DSR_FULLSCREEN (1 << 30) 211 #define MDFLD_DSR_DELAY (HZ / MDFLD_DSR_RR) 212 213 #define PSB_PWR_STATE_ON 1 214 #define PSB_PWR_STATE_OFF 2 215 216 #define PSB_PMPOLICY_NOPM 0 217 #define PSB_PMPOLICY_CLOCKGATING 1 218 #define PSB_PMPOLICY_POWERDOWN 2 219 220 #define PSB_PMSTATE_POWERUP 0 221 #define PSB_PMSTATE_CLOCKGATED 1 222 #define PSB_PMSTATE_POWERDOWN 2 223 #define PSB_PCIx_MSI_ADDR_LOC 0x94 224 #define PSB_PCIx_MSI_DATA_LOC 0x98 225 226 /* Medfield crystal settings */ 227 #define KSEL_CRYSTAL_19 1 228 #define KSEL_BYPASS_19 5 229 #define KSEL_BYPASS_25 6 230 #define KSEL_BYPASS_83_100 7 231 232 struct opregion_header; 233 struct opregion_acpi; 234 struct opregion_swsci; 235 struct opregion_asle; 236 237 struct psb_intel_opregion { 238 struct opregion_header *header; 239 struct opregion_acpi *acpi; 240 struct opregion_swsci *swsci; 241 struct opregion_asle *asle; 242 void *vbt; 243 u32 __iomem *lid_state; 244 struct work_struct asle_work; 245 }; 246 247 struct sdvo_device_mapping { 248 u8 initialized; 249 u8 dvo_port; 250 u8 slave_addr; 251 u8 dvo_wiring; 252 u8 i2c_pin; 253 u8 i2c_speed; 254 u8 ddc_pin; 255 }; 256 257 struct intel_gmbus { 258 struct i2c_adapter adapter; 259 struct i2c_adapter *force_bit; 260 u32 reg0; 261 }; 262 263 /* Register offset maps */ 264 struct psb_offset { 265 u32 fp0; 266 u32 fp1; 267 u32 cntr; 268 u32 conf; 269 u32 src; 270 u32 dpll; 271 u32 dpll_md; 272 u32 htotal; 273 u32 hblank; 274 u32 hsync; 275 u32 vtotal; 276 u32 vblank; 277 u32 vsync; 278 u32 stride; 279 u32 size; 280 u32 pos; 281 u32 surf; 282 u32 addr; 283 u32 base; 284 u32 status; 285 u32 linoff; 286 u32 tileoff; 287 u32 palette; 288 }; 289 290 /* 291 * Register save state. This is used to hold the context when the 292 * device is powered off. In the case of Oaktrail this can (but does not 293 * yet) include screen blank. Operations occuring during the save 294 * update the register cache instead. 295 */ 296 297 /* Common status for pipes */ 298 struct psb_pipe { 299 u32 fp0; 300 u32 fp1; 301 u32 cntr; 302 u32 conf; 303 u32 src; 304 u32 dpll; 305 u32 dpll_md; 306 u32 htotal; 307 u32 hblank; 308 u32 hsync; 309 u32 vtotal; 310 u32 vblank; 311 u32 vsync; 312 u32 stride; 313 u32 size; 314 u32 pos; 315 u32 base; 316 u32 surf; 317 u32 addr; 318 u32 status; 319 u32 linoff; 320 u32 tileoff; 321 u32 palette[256]; 322 }; 323 324 struct psb_state { 325 uint32_t saveVCLK_DIVISOR_VGA0; 326 uint32_t saveVCLK_DIVISOR_VGA1; 327 uint32_t saveVCLK_POST_DIV; 328 uint32_t saveVGACNTRL; 329 uint32_t saveADPA; 330 uint32_t saveLVDS; 331 uint32_t saveDVOA; 332 uint32_t saveDVOB; 333 uint32_t saveDVOC; 334 uint32_t savePP_ON; 335 uint32_t savePP_OFF; 336 uint32_t savePP_CONTROL; 337 uint32_t savePP_CYCLE; 338 uint32_t savePFIT_CONTROL; 339 uint32_t saveCLOCKGATING; 340 uint32_t saveDSPARB; 341 uint32_t savePFIT_AUTO_RATIOS; 342 uint32_t savePFIT_PGM_RATIOS; 343 uint32_t savePP_ON_DELAYS; 344 uint32_t savePP_OFF_DELAYS; 345 uint32_t savePP_DIVISOR; 346 uint32_t saveBCLRPAT_A; 347 uint32_t saveBCLRPAT_B; 348 uint32_t savePERF_MODE; 349 uint32_t saveDSPFW1; 350 uint32_t saveDSPFW2; 351 uint32_t saveDSPFW3; 352 uint32_t saveDSPFW4; 353 uint32_t saveDSPFW5; 354 uint32_t saveDSPFW6; 355 uint32_t saveCHICKENBIT; 356 uint32_t saveDSPACURSOR_CTRL; 357 uint32_t saveDSPBCURSOR_CTRL; 358 uint32_t saveDSPACURSOR_BASE; 359 uint32_t saveDSPBCURSOR_BASE; 360 uint32_t saveDSPACURSOR_POS; 361 uint32_t saveDSPBCURSOR_POS; 362 uint32_t saveOV_OVADD; 363 uint32_t saveOV_OGAMC0; 364 uint32_t saveOV_OGAMC1; 365 uint32_t saveOV_OGAMC2; 366 uint32_t saveOV_OGAMC3; 367 uint32_t saveOV_OGAMC4; 368 uint32_t saveOV_OGAMC5; 369 uint32_t saveOVC_OVADD; 370 uint32_t saveOVC_OGAMC0; 371 uint32_t saveOVC_OGAMC1; 372 uint32_t saveOVC_OGAMC2; 373 uint32_t saveOVC_OGAMC3; 374 uint32_t saveOVC_OGAMC4; 375 uint32_t saveOVC_OGAMC5; 376 377 /* DPST register save */ 378 uint32_t saveHISTOGRAM_INT_CONTROL_REG; 379 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG; 380 uint32_t savePWM_CONTROL_LOGIC; 381 }; 382 383 struct medfield_state { 384 uint32_t saveMIPI; 385 uint32_t saveMIPI_C; 386 387 uint32_t savePFIT_CONTROL; 388 uint32_t savePFIT_PGM_RATIOS; 389 uint32_t saveHDMIPHYMISCCTL; 390 uint32_t saveHDMIB_CONTROL; 391 }; 392 393 struct cdv_state { 394 uint32_t saveDSPCLK_GATE_D; 395 uint32_t saveRAMCLK_GATE_D; 396 uint32_t saveDSPARB; 397 uint32_t saveDSPFW[6]; 398 uint32_t saveADPA; 399 uint32_t savePP_CONTROL; 400 uint32_t savePFIT_PGM_RATIOS; 401 uint32_t saveLVDS; 402 uint32_t savePFIT_CONTROL; 403 uint32_t savePP_ON_DELAYS; 404 uint32_t savePP_OFF_DELAYS; 405 uint32_t savePP_CYCLE; 406 uint32_t saveVGACNTRL; 407 uint32_t saveIER; 408 uint32_t saveIMR; 409 u8 saveLBB; 410 }; 411 412 struct psb_save_area { 413 struct psb_pipe pipe[3]; 414 uint32_t saveBSM; 415 uint32_t saveVBT; 416 union { 417 struct psb_state psb; 418 struct medfield_state mdfld; 419 struct cdv_state cdv; 420 }; 421 uint32_t saveBLC_PWM_CTL2; 422 uint32_t saveBLC_PWM_CTL; 423 }; 424 425 struct psb_ops; 426 427 #define PSB_NUM_PIPE 3 428 429 struct drm_psb_private { 430 struct drm_device *dev; 431 struct pci_dev *aux_pdev; /* Currently only used by mrst */ 432 struct pci_dev *lpc_pdev; /* Currently only used by mrst */ 433 const struct psb_ops *ops; 434 const struct psb_offset *regmap; 435 436 struct child_device_config *child_dev; 437 int child_dev_num; 438 439 struct psb_gtt gtt; 440 441 /* GTT Memory manager */ 442 struct psb_gtt_mm *gtt_mm; 443 struct page *scratch_page; 444 u32 __iomem *gtt_map; 445 uint32_t stolen_base; 446 u8 __iomem *vram_addr; 447 unsigned long vram_stolen_size; 448 int gtt_initialized; 449 u16 gmch_ctrl; /* Saved GTT setup */ 450 u32 pge_ctl; 451 452 struct mutex gtt_mutex; 453 struct resource *gtt_mem; /* Our PCI resource */ 454 455 struct mutex mmap_mutex; 456 457 struct psb_mmu_driver *mmu; 458 struct psb_mmu_pd *pf_pd; 459 460 /* Register base */ 461 uint8_t __iomem *sgx_reg; 462 uint8_t __iomem *vdc_reg; 463 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */ 464 uint16_t lpc_gpio_base; 465 uint32_t gatt_free_offset; 466 467 /* Fencing / irq */ 468 uint32_t vdc_irq_mask; 469 uint32_t pipestat[PSB_NUM_PIPE]; 470 471 spinlock_t irqmask_lock; 472 473 /* Power */ 474 bool suspended; 475 bool display_power; 476 int display_count; 477 478 /* Modesetting */ 479 struct psb_intel_mode_device mode_dev; 480 bool modeset; /* true if we have done the mode_device setup */ 481 482 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE]; 483 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE]; 484 uint32_t num_pipe; 485 486 /* OSPM info (Power management base) (TODO: can go ?) */ 487 uint32_t ospm_base; 488 489 /* Sizes info */ 490 u32 fuse_reg_value; 491 u32 video_device_fuse; 492 493 /* PCI revision ID for B0:D2:F0 */ 494 uint8_t platform_rev_id; 495 496 /* gmbus */ 497 struct intel_gmbus *gmbus; 498 uint8_t __iomem *gmbus_reg; 499 500 /* Used by SDVO */ 501 int crt_ddc_pin; 502 /* FIXME: The mappings should be parsed from bios but for now we can 503 pretend there are no mappings available */ 504 struct sdvo_device_mapping sdvo_mappings[2]; 505 u32 hotplug_supported_mask; 506 struct drm_property *broadcast_rgb_property; 507 struct drm_property *force_audio_property; 508 509 /* LVDS info */ 510 int backlight_duty_cycle; /* restore backlight to this value */ 511 bool panel_wants_dither; 512 struct drm_display_mode *panel_fixed_mode; 513 struct drm_display_mode *lfp_lvds_vbt_mode; 514 struct drm_display_mode *sdvo_lvds_vbt_mode; 515 516 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */ 517 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */ 518 519 /* Feature bits from the VBIOS */ 520 unsigned int int_tv_support:1; 521 unsigned int lvds_dither:1; 522 unsigned int lvds_vbt:1; 523 unsigned int int_crt_support:1; 524 unsigned int lvds_use_ssc:1; 525 int lvds_ssc_freq; 526 bool is_lvds_on; 527 bool is_mipi_on; 528 bool lvds_enabled_in_vbt; 529 u32 mipi_ctrl_display; 530 531 unsigned int core_freq; 532 uint32_t iLVDS_enable; 533 534 /* Runtime PM state */ 535 int rpm_enabled; 536 537 /* MID specific */ 538 bool has_gct; 539 struct oaktrail_gct_data gct_data; 540 541 /* Oaktrail HDMI state */ 542 struct oaktrail_hdmi_dev *hdmi_priv; 543 544 /* Register state */ 545 struct psb_save_area regs; 546 547 /* MSI reg save */ 548 uint32_t msi_addr; 549 uint32_t msi_data; 550 551 /* Hotplug handling */ 552 struct work_struct hotplug_work; 553 554 /* LID-Switch */ 555 spinlock_t lid_lock; 556 struct timer_list lid_timer; 557 struct psb_intel_opregion opregion; 558 u32 lid_last_state; 559 560 /* Watchdog */ 561 uint32_t apm_reg; 562 uint16_t apm_base; 563 564 /* 565 * Used for modifying backlight from 566 * xrandr -- consider removing and using HAL instead 567 */ 568 struct backlight_device *backlight_device; 569 struct drm_property *backlight_property; 570 bool backlight_enabled; 571 int backlight_level; 572 uint32_t blc_adj1; 573 uint32_t blc_adj2; 574 575 void *fbdev; 576 577 /* 2D acceleration */ 578 spinlock_t lock_2d; 579 580 /* Panel brightness */ 581 int brightness; 582 int brightness_adjusted; 583 584 bool dsr_enable; 585 u32 dsr_fb_update; 586 bool dpi_panel_on[3]; 587 void *dsi_configs[2]; 588 u32 bpp; 589 u32 bpp2; 590 591 u32 pipeconf[3]; 592 u32 dspcntr[3]; 593 594 int mdfld_panel_id; 595 596 bool dplla_96mhz; /* DPLL data from the VBT */ 597 598 struct { 599 int rate; 600 int lanes; 601 int preemphasis; 602 int vswing; 603 604 bool initialized; 605 bool support; 606 int bpp; 607 struct edp_power_seq pps; 608 } edp; 609 uint8_t panel_type; 610 }; 611 612 613 /* Operations for each board type */ 614 struct psb_ops { 615 const char *name; 616 unsigned int accel_2d:1; 617 int pipes; /* Number of output pipes */ 618 int crtcs; /* Number of CRTCs */ 619 int sgx_offset; /* Base offset of SGX device */ 620 int hdmi_mask; /* Mask of HDMI CRTCs */ 621 int lvds_mask; /* Mask of LVDS CRTCs */ 622 int sdvo_mask; /* Mask of SDVO CRTCs */ 623 int cursor_needs_phys; /* If cursor base reg need physical address */ 624 625 /* Sub functions */ 626 struct drm_crtc_helper_funcs const *crtc_helper; 627 struct drm_crtc_funcs const *crtc_funcs; 628 const struct gma_clock_funcs *clock_funcs; 629 630 /* Setup hooks */ 631 int (*chip_setup)(struct drm_device *dev); 632 void (*chip_teardown)(struct drm_device *dev); 633 /* Optional helper caller after modeset */ 634 void (*errata)(struct drm_device *dev); 635 636 /* Display management hooks */ 637 int (*output_init)(struct drm_device *dev); 638 int (*hotplug)(struct drm_device *dev); 639 void (*hotplug_enable)(struct drm_device *dev, bool on); 640 /* Power management hooks */ 641 void (*init_pm)(struct drm_device *dev); 642 int (*save_regs)(struct drm_device *dev); 643 int (*restore_regs)(struct drm_device *dev); 644 void (*save_crtc)(struct drm_crtc *crtc); 645 void (*restore_crtc)(struct drm_crtc *crtc); 646 int (*power_up)(struct drm_device *dev); 647 int (*power_down)(struct drm_device *dev); 648 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc); 649 void (*disable_sr)(struct drm_device *dev); 650 651 void (*lvds_bl_power)(struct drm_device *dev, bool on); 652 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 653 /* Backlight */ 654 int (*backlight_init)(struct drm_device *dev); 655 #endif 656 int i2c_bus; /* I2C bus identifier for Moorestown */ 657 }; 658 659 660 661 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int); 662 extern int drm_pick_crtcs(struct drm_device *dev); 663 664 static inline struct drm_psb_private *psb_priv(struct drm_device *dev) 665 { 666 return (struct drm_psb_private *) dev->dev_private; 667 } 668 669 /* psb_irq.c */ 670 extern irqreturn_t psb_irq_handler(int irq, void *arg); 671 extern int psb_irq_enable_dpst(struct drm_device *dev); 672 extern int psb_irq_disable_dpst(struct drm_device *dev); 673 extern void psb_irq_preinstall(struct drm_device *dev); 674 extern int psb_irq_postinstall(struct drm_device *dev); 675 extern void psb_irq_uninstall(struct drm_device *dev); 676 extern void psb_irq_turn_on_dpst(struct drm_device *dev); 677 extern void psb_irq_turn_off_dpst(struct drm_device *dev); 678 679 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); 680 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); 681 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); 682 extern int psb_enable_vblank(struct drm_device *dev, unsigned int pipe); 683 extern void psb_disable_vblank(struct drm_device *dev, unsigned int pipe); 684 void 685 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 686 687 void 688 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); 689 690 extern u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe); 691 692 /* framebuffer.c */ 693 extern int psbfb_probed(struct drm_device *dev); 694 extern int psbfb_remove(struct drm_device *dev, 695 struct drm_framebuffer *fb); 696 /* accel_2d.c */ 697 extern void psbfb_copyarea(struct fb_info *info, 698 const struct fb_copyarea *region); 699 extern int psbfb_sync(struct fb_info *info); 700 extern void psb_spank(struct drm_psb_private *dev_priv); 701 702 /* psb_reset.c */ 703 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv); 704 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv); 705 extern void psb_print_pagefault(struct drm_psb_private *dev_priv); 706 707 /* modesetting */ 708 extern void psb_modeset_init(struct drm_device *dev); 709 extern void psb_modeset_cleanup(struct drm_device *dev); 710 extern int psb_fbdev_init(struct drm_device *dev); 711 712 /* backlight.c */ 713 int gma_backlight_init(struct drm_device *dev); 714 void gma_backlight_exit(struct drm_device *dev); 715 void gma_backlight_disable(struct drm_device *dev); 716 void gma_backlight_enable(struct drm_device *dev); 717 void gma_backlight_set(struct drm_device *dev, int v); 718 719 /* oaktrail_crtc.c */ 720 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs; 721 722 /* oaktrail_lvds.c */ 723 extern void oaktrail_lvds_init(struct drm_device *dev, 724 struct psb_intel_mode_device *mode_dev); 725 726 /* psb_intel_display.c */ 727 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs; 728 extern const struct drm_crtc_funcs psb_intel_crtc_funcs; 729 730 /* psb_intel_lvds.c */ 731 extern const struct drm_connector_helper_funcs 732 psb_intel_lvds_connector_helper_funcs; 733 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs; 734 735 /* gem.c */ 736 extern void psb_gem_free_object(struct drm_gem_object *obj); 737 extern int psb_gem_get_aperture(struct drm_device *dev, void *data, 738 struct drm_file *file); 739 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 740 struct drm_mode_create_dumb *args); 741 extern vm_fault_t psb_gem_fault(struct vm_fault *vmf); 742 743 /* psb_device.c */ 744 extern const struct psb_ops psb_chip_ops; 745 746 /* oaktrail_device.c */ 747 extern const struct psb_ops oaktrail_chip_ops; 748 749 /* mdlfd_device.c */ 750 extern const struct psb_ops mdfld_chip_ops; 751 752 /* cdv_device.c */ 753 extern const struct psb_ops cdv_chip_ops; 754 755 /* Debug print bits setting */ 756 #define PSB_D_GENERAL (1 << 0) 757 #define PSB_D_INIT (1 << 1) 758 #define PSB_D_IRQ (1 << 2) 759 #define PSB_D_ENTRY (1 << 3) 760 /* debug the get H/V BP/FP count */ 761 #define PSB_D_HV (1 << 4) 762 #define PSB_D_DBI_BF (1 << 5) 763 #define PSB_D_PM (1 << 6) 764 #define PSB_D_RENDER (1 << 7) 765 #define PSB_D_REG (1 << 8) 766 #define PSB_D_MSVDX (1 << 9) 767 #define PSB_D_TOPAZ (1 << 10) 768 769 extern int drm_idle_check_interval; 770 771 /* Utilities */ 772 static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset) 773 { 774 int mcr = (0xD0<<24) | (port << 16) | (offset << 8); 775 uint32_t ret_val = 0; 776 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 777 pci_write_config_dword(pci_root, 0xD0, mcr); 778 pci_read_config_dword(pci_root, 0xD4, &ret_val); 779 pci_dev_put(pci_root); 780 return ret_val; 781 } 782 static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset, 783 u32 value) 784 { 785 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; 786 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 787 pci_write_config_dword(pci_root, 0xD4, value); 788 pci_write_config_dword(pci_root, 0xD0, mcr); 789 pci_dev_put(pci_root); 790 } 791 static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset) 792 { 793 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 794 uint32_t ret_val = 0; 795 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 796 pci_write_config_dword(pci_root, 0xD0, mcr); 797 pci_read_config_dword(pci_root, 0xD4, &ret_val); 798 pci_dev_put(pci_root); 799 return ret_val; 800 } 801 static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset, 802 u32 value) 803 { 804 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 805 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 806 pci_write_config_dword(pci_root, 0xD4, value); 807 pci_write_config_dword(pci_root, 0xD0, mcr); 808 pci_dev_put(pci_root); 809 } 810 811 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) 812 { 813 struct drm_psb_private *dev_priv = dev->dev_private; 814 return ioread32(dev_priv->vdc_reg + reg); 815 } 816 817 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg) 818 { 819 struct drm_psb_private *dev_priv = dev->dev_private; 820 return ioread32(dev_priv->aux_reg + reg); 821 } 822 823 #define REG_READ(reg) REGISTER_READ(dev, (reg)) 824 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg)) 825 826 /* Useful for post reads */ 827 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev, 828 uint32_t reg, int aux) 829 { 830 uint32_t val; 831 832 if (aux) 833 val = REG_READ_AUX(reg); 834 else 835 val = REG_READ(reg); 836 837 return val; 838 } 839 840 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux)) 841 842 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, 843 uint32_t val) 844 { 845 struct drm_psb_private *dev_priv = dev->dev_private; 846 iowrite32((val), dev_priv->vdc_reg + (reg)); 847 } 848 849 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg, 850 uint32_t val) 851 { 852 struct drm_psb_private *dev_priv = dev->dev_private; 853 iowrite32((val), dev_priv->aux_reg + (reg)); 854 } 855 856 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) 857 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val)) 858 859 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg, 860 uint32_t val, int aux) 861 { 862 if (aux) 863 REG_WRITE_AUX(reg, val); 864 else 865 REG_WRITE(reg, val); 866 } 867 868 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux)) 869 870 static inline void REGISTER_WRITE16(struct drm_device *dev, 871 uint32_t reg, uint32_t val) 872 { 873 struct drm_psb_private *dev_priv = dev->dev_private; 874 iowrite16((val), dev_priv->vdc_reg + (reg)); 875 } 876 877 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) 878 879 static inline void REGISTER_WRITE8(struct drm_device *dev, 880 uint32_t reg, uint32_t val) 881 { 882 struct drm_psb_private *dev_priv = dev->dev_private; 883 iowrite8((val), dev_priv->vdc_reg + (reg)); 884 } 885 886 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) 887 888 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs)) 889 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs)) 890 891 /* #define TRAP_SGX_PM_FAULT 1 */ 892 #ifdef TRAP_SGX_PM_FAULT 893 #define PSB_RSGX32(_offs) \ 894 ({ \ 895 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \ 896 pr_err("access sgx when it's off!! (READ) %s, %d\n", \ 897 __FILE__, __LINE__); \ 898 melay(1000); \ 899 } \ 900 ioread32(dev_priv->sgx_reg + (_offs)); \ 901 }) 902 #else 903 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs)) 904 #endif 905 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs)) 906 907 #define MSVDX_REG_DUMP 0 908 909 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs)) 910 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) 911 912 #endif 913