1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA. 6 * All Rights Reserved. 7 * 8 **************************************************************************/ 9 10 #include <linux/cpu.h> 11 #include <linux/module.h> 12 #include <linux/notifier.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/spinlock.h> 15 16 #include <asm/set_memory.h> 17 18 #include <acpi/video.h> 19 20 #include <drm/drm.h> 21 #include <drm/drm_drv.h> 22 #include <drm/drm_file.h> 23 #include <drm/drm_ioctl.h> 24 #include <drm/drm_irq.h> 25 #include <drm/drm_pci.h> 26 #include <drm/drm_pciids.h> 27 #include <drm/drm_vblank.h> 28 29 #include "framebuffer.h" 30 #include "intel_bios.h" 31 #include "mid_bios.h" 32 #include "power.h" 33 #include "psb_drv.h" 34 #include "psb_intel_reg.h" 35 #include "psb_reg.h" 36 37 static struct drm_driver driver; 38 static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 39 40 /* 41 * The table below contains a mapping of the PCI vendor ID and the PCI Device ID 42 * to the different groups of PowerVR 5-series chip designs 43 * 44 * 0x8086 = Intel Corporation 45 * 46 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx 47 * PowerVR SGX535 - Moorestown - Intel GMA 600 48 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx 49 * PowerVR SGX540 - Medfield - Intel Atom Z2460 50 * PowerVR SGX544MP2 - Medfield - 51 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600 52 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700, 53 * N2800 54 */ 55 static const struct pci_device_id pciidlist[] = { 56 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops }, 57 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops }, 58 #if defined(CONFIG_DRM_GMA600) 59 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 60 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 61 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 62 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 63 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 64 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 65 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 66 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 67 { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 68 #endif 69 #if defined(CONFIG_DRM_MEDFIELD) 70 { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 71 { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 72 { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 73 { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 74 { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 75 { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 76 { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 77 { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 78 #endif 79 #if defined(CONFIG_DRM_GMA3600) 80 { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 81 { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 82 { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 83 { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 84 { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 85 { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 86 { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 87 { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 88 { 0x8086, 0x0be8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 89 { 0x8086, 0x0be9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 90 { 0x8086, 0x0bea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 91 { 0x8086, 0x0beb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 92 { 0x8086, 0x0bec, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 93 { 0x8086, 0x0bed, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 94 { 0x8086, 0x0bee, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 95 { 0x8086, 0x0bef, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 96 #endif 97 { 0, } 98 }; 99 MODULE_DEVICE_TABLE(pci, pciidlist); 100 101 /* 102 * Standard IOCTLs. 103 */ 104 static const struct drm_ioctl_desc psb_ioctls[] = { 105 }; 106 107 static int psb_do_init(struct drm_device *dev) 108 { 109 struct drm_psb_private *dev_priv = dev->dev_private; 110 struct psb_gtt *pg = &dev_priv->gtt; 111 112 uint32_t stolen_gtt; 113 114 if (pg->mmu_gatt_start & 0x0FFFFFFF) { 115 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n"); 116 return -EINVAL; 117 } 118 119 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4; 120 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT; 121 stolen_gtt = (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages; 122 123 dev_priv->gatt_free_offset = pg->mmu_gatt_start + 124 (stolen_gtt << PAGE_SHIFT) * 1024; 125 126 spin_lock_init(&dev_priv->irqmask_lock); 127 spin_lock_init(&dev_priv->lock_2d); 128 129 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0); 130 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1); 131 PSB_RSGX32(PSB_CR_BIF_BANK1); 132 133 /* Do not bypass any MMU access, let them pagefault instead */ 134 PSB_WSGX32((PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_MMU_ER_MASK), 135 PSB_CR_BIF_CTRL); 136 PSB_RSGX32(PSB_CR_BIF_CTRL); 137 138 psb_spank(dev_priv); 139 140 /* mmu_gatt ?? */ 141 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); 142 PSB_RSGX32(PSB_CR_BIF_TWOD_REQ_BASE); /* Post */ 143 144 return 0; 145 } 146 147 static void psb_driver_unload(struct drm_device *dev) 148 { 149 struct drm_psb_private *dev_priv = dev->dev_private; 150 151 /* TODO: Kill vblank etc here */ 152 153 if (dev_priv) { 154 if (dev_priv->backlight_device) 155 gma_backlight_exit(dev); 156 psb_modeset_cleanup(dev); 157 158 if (dev_priv->ops->chip_teardown) 159 dev_priv->ops->chip_teardown(dev); 160 161 psb_intel_opregion_fini(dev); 162 163 if (dev_priv->pf_pd) { 164 psb_mmu_free_pagedir(dev_priv->pf_pd); 165 dev_priv->pf_pd = NULL; 166 } 167 if (dev_priv->mmu) { 168 struct psb_gtt *pg = &dev_priv->gtt; 169 170 down_read(&pg->sem); 171 psb_mmu_remove_pfn_sequence( 172 psb_mmu_get_default_pd 173 (dev_priv->mmu), 174 pg->mmu_gatt_start, 175 dev_priv->vram_stolen_size >> PAGE_SHIFT); 176 up_read(&pg->sem); 177 psb_mmu_driver_takedown(dev_priv->mmu); 178 dev_priv->mmu = NULL; 179 } 180 psb_gtt_takedown(dev); 181 if (dev_priv->scratch_page) { 182 set_pages_wb(dev_priv->scratch_page, 1); 183 __free_page(dev_priv->scratch_page); 184 dev_priv->scratch_page = NULL; 185 } 186 if (dev_priv->vdc_reg) { 187 iounmap(dev_priv->vdc_reg); 188 dev_priv->vdc_reg = NULL; 189 } 190 if (dev_priv->sgx_reg) { 191 iounmap(dev_priv->sgx_reg); 192 dev_priv->sgx_reg = NULL; 193 } 194 if (dev_priv->aux_reg) { 195 iounmap(dev_priv->aux_reg); 196 dev_priv->aux_reg = NULL; 197 } 198 pci_dev_put(dev_priv->aux_pdev); 199 pci_dev_put(dev_priv->lpc_pdev); 200 201 /* Destroy VBT data */ 202 psb_intel_destroy_bios(dev); 203 204 kfree(dev_priv); 205 dev->dev_private = NULL; 206 } 207 gma_power_uninit(dev); 208 } 209 210 static int psb_driver_load(struct drm_device *dev, unsigned long flags) 211 { 212 struct drm_psb_private *dev_priv; 213 unsigned long resource_start, resource_len; 214 unsigned long irqflags; 215 int ret = -ENOMEM; 216 struct drm_connector *connector; 217 struct gma_encoder *gma_encoder; 218 struct psb_gtt *pg; 219 220 /* allocating and initializing driver private data */ 221 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 222 if (dev_priv == NULL) 223 return -ENOMEM; 224 225 dev_priv->ops = (struct psb_ops *)flags; 226 dev_priv->dev = dev; 227 dev->dev_private = (void *) dev_priv; 228 229 pg = &dev_priv->gtt; 230 231 pci_set_master(dev->pdev); 232 233 dev_priv->num_pipe = dev_priv->ops->pipes; 234 235 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE); 236 237 dev_priv->vdc_reg = 238 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE); 239 if (!dev_priv->vdc_reg) 240 goto out_err; 241 242 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset, 243 PSB_SGX_SIZE); 244 if (!dev_priv->sgx_reg) 245 goto out_err; 246 247 if (IS_MRST(dev)) { 248 int domain = pci_domain_nr(dev->pdev->bus); 249 250 dev_priv->aux_pdev = 251 pci_get_domain_bus_and_slot(domain, 0, 252 PCI_DEVFN(3, 0)); 253 254 if (dev_priv->aux_pdev) { 255 resource_start = pci_resource_start(dev_priv->aux_pdev, 256 PSB_AUX_RESOURCE); 257 resource_len = pci_resource_len(dev_priv->aux_pdev, 258 PSB_AUX_RESOURCE); 259 dev_priv->aux_reg = ioremap_nocache(resource_start, 260 resource_len); 261 if (!dev_priv->aux_reg) 262 goto out_err; 263 264 DRM_DEBUG_KMS("Found aux vdc"); 265 } else { 266 /* Couldn't find the aux vdc so map to primary vdc */ 267 dev_priv->aux_reg = dev_priv->vdc_reg; 268 DRM_DEBUG_KMS("Couldn't find aux pci device"); 269 } 270 dev_priv->gmbus_reg = dev_priv->aux_reg; 271 272 dev_priv->lpc_pdev = 273 pci_get_domain_bus_and_slot(domain, 0, 274 PCI_DEVFN(31, 0)); 275 if (dev_priv->lpc_pdev) { 276 pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA, 277 &dev_priv->lpc_gpio_base); 278 pci_write_config_dword(dev_priv->lpc_pdev, PSB_LPC_GBA, 279 (u32)dev_priv->lpc_gpio_base | (1L<<31)); 280 pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA, 281 &dev_priv->lpc_gpio_base); 282 dev_priv->lpc_gpio_base &= 0xffc0; 283 if (dev_priv->lpc_gpio_base) 284 DRM_DEBUG_KMS("Found LPC GPIO at 0x%04x\n", 285 dev_priv->lpc_gpio_base); 286 else { 287 pci_dev_put(dev_priv->lpc_pdev); 288 dev_priv->lpc_pdev = NULL; 289 } 290 } 291 } else { 292 dev_priv->gmbus_reg = dev_priv->vdc_reg; 293 } 294 295 psb_intel_opregion_setup(dev); 296 297 ret = dev_priv->ops->chip_setup(dev); 298 if (ret) 299 goto out_err; 300 301 /* Init OSPM support */ 302 gma_power_init(dev); 303 304 ret = -ENOMEM; 305 306 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO); 307 if (!dev_priv->scratch_page) 308 goto out_err; 309 310 set_pages_uc(dev_priv->scratch_page, 1); 311 312 ret = psb_gtt_init(dev, 0); 313 if (ret) 314 goto out_err; 315 316 dev_priv->mmu = psb_mmu_driver_init(dev, 1, 0, 0); 317 if (!dev_priv->mmu) 318 goto out_err; 319 320 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0); 321 if (!dev_priv->pf_pd) 322 goto out_err; 323 324 ret = psb_do_init(dev); 325 if (ret) 326 return ret; 327 328 /* Add stolen memory to SGX MMU */ 329 down_read(&pg->sem); 330 ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu), 331 dev_priv->stolen_base >> PAGE_SHIFT, 332 pg->gatt_start, 333 pg->stolen_size >> PAGE_SHIFT, 0); 334 up_read(&pg->sem); 335 336 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0); 337 psb_mmu_set_pd_context(dev_priv->pf_pd, 1); 338 339 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE); 340 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE); 341 342 acpi_video_register(); 343 344 /* Setup vertical blanking handling */ 345 ret = drm_vblank_init(dev, dev_priv->num_pipe); 346 if (ret) 347 goto out_err; 348 349 /* 350 * Install interrupt handlers prior to powering off SGX or else we will 351 * crash. 352 */ 353 dev_priv->vdc_irq_mask = 0; 354 dev_priv->pipestat[0] = 0; 355 dev_priv->pipestat[1] = 0; 356 dev_priv->pipestat[2] = 0; 357 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 358 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 359 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); 360 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R); 361 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 362 363 drm_irq_install(dev, dev->pdev->irq); 364 365 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 366 dev->driver->get_vblank_counter = psb_get_vblank_counter; 367 368 psb_modeset_init(dev); 369 psb_fbdev_init(dev); 370 drm_kms_helper_poll_init(dev); 371 372 /* Only add backlight support if we have LVDS output */ 373 list_for_each_entry(connector, &dev->mode_config.connector_list, 374 head) { 375 gma_encoder = gma_attached_encoder(connector); 376 377 switch (gma_encoder->type) { 378 case INTEL_OUTPUT_LVDS: 379 case INTEL_OUTPUT_MIPI: 380 ret = gma_backlight_init(dev); 381 break; 382 } 383 } 384 385 if (ret) 386 return ret; 387 psb_intel_opregion_enable_asle(dev); 388 #if 0 389 /* Enable runtime pm at last */ 390 pm_runtime_enable(&dev->pdev->dev); 391 pm_runtime_set_active(&dev->pdev->dev); 392 #endif 393 /* Intel drm driver load is done, continue doing pvr load */ 394 return 0; 395 out_err: 396 psb_driver_unload(dev); 397 return ret; 398 } 399 400 static inline void get_brightness(struct backlight_device *bd) 401 { 402 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 403 if (bd) { 404 bd->props.brightness = bd->ops->get_brightness(bd); 405 backlight_update_status(bd); 406 } 407 #endif 408 } 409 410 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd, 411 unsigned long arg) 412 { 413 struct drm_file *file_priv = filp->private_data; 414 struct drm_device *dev = file_priv->minor->dev; 415 struct drm_psb_private *dev_priv = dev->dev_private; 416 static unsigned int runtime_allowed; 417 418 if (runtime_allowed == 1 && dev_priv->is_lvds_on) { 419 runtime_allowed++; 420 pm_runtime_allow(&dev->pdev->dev); 421 dev_priv->rpm_enabled = 1; 422 } 423 return drm_ioctl(filp, cmd, arg); 424 /* FIXME: do we need to wrap the other side of this */ 425 } 426 427 static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 428 { 429 return drm_get_pci_dev(pdev, ent, &driver); 430 } 431 432 433 static void psb_pci_remove(struct pci_dev *pdev) 434 { 435 struct drm_device *dev = pci_get_drvdata(pdev); 436 drm_put_dev(dev); 437 } 438 439 static const struct dev_pm_ops psb_pm_ops = { 440 .resume = gma_power_resume, 441 .suspend = gma_power_suspend, 442 .thaw = gma_power_thaw, 443 .freeze = gma_power_freeze, 444 .restore = gma_power_restore, 445 .runtime_suspend = psb_runtime_suspend, 446 .runtime_resume = psb_runtime_resume, 447 .runtime_idle = psb_runtime_idle, 448 }; 449 450 static const struct vm_operations_struct psb_gem_vm_ops = { 451 .fault = psb_gem_fault, 452 .open = drm_gem_vm_open, 453 .close = drm_gem_vm_close, 454 }; 455 456 static const struct file_operations psb_gem_fops = { 457 .owner = THIS_MODULE, 458 .open = drm_open, 459 .release = drm_release, 460 .unlocked_ioctl = psb_unlocked_ioctl, 461 .compat_ioctl = drm_compat_ioctl, 462 .mmap = drm_gem_mmap, 463 .poll = drm_poll, 464 .read = drm_read, 465 }; 466 467 static struct drm_driver driver = { 468 .driver_features = DRIVER_MODESET | DRIVER_GEM, 469 .load = psb_driver_load, 470 .unload = psb_driver_unload, 471 .lastclose = drm_fb_helper_lastclose, 472 473 .num_ioctls = ARRAY_SIZE(psb_ioctls), 474 .irq_preinstall = psb_irq_preinstall, 475 .irq_postinstall = psb_irq_postinstall, 476 .irq_uninstall = psb_irq_uninstall, 477 .irq_handler = psb_irq_handler, 478 .enable_vblank = psb_enable_vblank, 479 .disable_vblank = psb_disable_vblank, 480 .get_vblank_counter = psb_get_vblank_counter, 481 482 .gem_free_object = psb_gem_free_object, 483 .gem_vm_ops = &psb_gem_vm_ops, 484 485 .dumb_create = psb_gem_dumb_create, 486 .ioctls = psb_ioctls, 487 .fops = &psb_gem_fops, 488 .name = DRIVER_NAME, 489 .desc = DRIVER_DESC, 490 .date = DRIVER_DATE, 491 .major = DRIVER_MAJOR, 492 .minor = DRIVER_MINOR, 493 .patchlevel = DRIVER_PATCHLEVEL 494 }; 495 496 static struct pci_driver psb_pci_driver = { 497 .name = DRIVER_NAME, 498 .id_table = pciidlist, 499 .probe = psb_pci_probe, 500 .remove = psb_pci_remove, 501 .driver.pm = &psb_pm_ops, 502 }; 503 504 static int __init psb_init(void) 505 { 506 return pci_register_driver(&psb_pci_driver); 507 } 508 509 static void __exit psb_exit(void) 510 { 511 pci_unregister_driver(&psb_pci_driver); 512 } 513 514 late_initcall(psb_init); 515 module_exit(psb_exit); 516 517 MODULE_AUTHOR(DRIVER_AUTHOR); 518 MODULE_DESCRIPTION(DRIVER_DESC); 519 MODULE_LICENSE("GPL"); 520