1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA. 6 * All Rights Reserved. 7 * 8 **************************************************************************/ 9 10 #include <drm/drmP.h> 11 #include <drm/drm.h> 12 #include "psb_drv.h" 13 #include "framebuffer.h" 14 #include "psb_reg.h" 15 #include "psb_intel_reg.h" 16 #include "intel_bios.h" 17 #include "mid_bios.h" 18 #include <drm/drm_pciids.h> 19 #include "power.h" 20 #include <linux/cpu.h> 21 #include <linux/notifier.h> 22 #include <linux/spinlock.h> 23 #include <linux/pm_runtime.h> 24 #include <acpi/video.h> 25 #include <linux/module.h> 26 #include <asm/set_memory.h> 27 28 static struct drm_driver driver; 29 static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent); 30 31 /* 32 * The table below contains a mapping of the PCI vendor ID and the PCI Device ID 33 * to the different groups of PowerVR 5-series chip designs 34 * 35 * 0x8086 = Intel Corporation 36 * 37 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx 38 * PowerVR SGX535 - Moorestown - Intel GMA 600 39 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx 40 * PowerVR SGX540 - Medfield - Intel Atom Z2460 41 * PowerVR SGX544MP2 - Medfield - 42 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600 43 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700, 44 * N2800 45 */ 46 static const struct pci_device_id pciidlist[] = { 47 { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops }, 48 { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &psb_chip_ops }, 49 #if defined(CONFIG_DRM_GMA600) 50 { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 51 { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 52 { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 53 { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 54 { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 55 { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 56 { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 57 { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 58 { 0x8086, 0x4108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &oaktrail_chip_ops }, 59 #endif 60 #if defined(CONFIG_DRM_MEDFIELD) 61 { 0x8086, 0x0130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 62 { 0x8086, 0x0131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 63 { 0x8086, 0x0132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 64 { 0x8086, 0x0133, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 65 { 0x8086, 0x0134, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 66 { 0x8086, 0x0135, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 67 { 0x8086, 0x0136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 68 { 0x8086, 0x0137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &mdfld_chip_ops }, 69 #endif 70 #if defined(CONFIG_DRM_GMA3600) 71 { 0x8086, 0x0be0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 72 { 0x8086, 0x0be1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 73 { 0x8086, 0x0be2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 74 { 0x8086, 0x0be3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 75 { 0x8086, 0x0be4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 76 { 0x8086, 0x0be5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 77 { 0x8086, 0x0be6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 78 { 0x8086, 0x0be7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 79 { 0x8086, 0x0be8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 80 { 0x8086, 0x0be9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 81 { 0x8086, 0x0bea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 82 { 0x8086, 0x0beb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 83 { 0x8086, 0x0bec, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 84 { 0x8086, 0x0bed, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 85 { 0x8086, 0x0bee, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 86 { 0x8086, 0x0bef, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (long) &cdv_chip_ops }, 87 #endif 88 { 0, } 89 }; 90 MODULE_DEVICE_TABLE(pci, pciidlist); 91 92 /* 93 * Standard IOCTLs. 94 */ 95 static const struct drm_ioctl_desc psb_ioctls[] = { 96 }; 97 98 static int psb_do_init(struct drm_device *dev) 99 { 100 struct drm_psb_private *dev_priv = dev->dev_private; 101 struct psb_gtt *pg = &dev_priv->gtt; 102 103 uint32_t stolen_gtt; 104 105 if (pg->mmu_gatt_start & 0x0FFFFFFF) { 106 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n"); 107 return -EINVAL; 108 } 109 110 stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4; 111 stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT; 112 stolen_gtt = (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages; 113 114 dev_priv->gatt_free_offset = pg->mmu_gatt_start + 115 (stolen_gtt << PAGE_SHIFT) * 1024; 116 117 spin_lock_init(&dev_priv->irqmask_lock); 118 spin_lock_init(&dev_priv->lock_2d); 119 120 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0); 121 PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1); 122 PSB_RSGX32(PSB_CR_BIF_BANK1); 123 124 /* Do not bypass any MMU access, let them pagefault instead */ 125 PSB_WSGX32((PSB_RSGX32(PSB_CR_BIF_CTRL) & ~_PSB_MMU_ER_MASK), 126 PSB_CR_BIF_CTRL); 127 PSB_RSGX32(PSB_CR_BIF_CTRL); 128 129 psb_spank(dev_priv); 130 131 /* mmu_gatt ?? */ 132 PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); 133 PSB_RSGX32(PSB_CR_BIF_TWOD_REQ_BASE); /* Post */ 134 135 return 0; 136 } 137 138 static void psb_driver_unload(struct drm_device *dev) 139 { 140 struct drm_psb_private *dev_priv = dev->dev_private; 141 142 /* TODO: Kill vblank etc here */ 143 144 if (dev_priv) { 145 if (dev_priv->backlight_device) 146 gma_backlight_exit(dev); 147 psb_modeset_cleanup(dev); 148 149 if (dev_priv->ops->chip_teardown) 150 dev_priv->ops->chip_teardown(dev); 151 152 psb_intel_opregion_fini(dev); 153 154 if (dev_priv->pf_pd) { 155 psb_mmu_free_pagedir(dev_priv->pf_pd); 156 dev_priv->pf_pd = NULL; 157 } 158 if (dev_priv->mmu) { 159 struct psb_gtt *pg = &dev_priv->gtt; 160 161 down_read(&pg->sem); 162 psb_mmu_remove_pfn_sequence( 163 psb_mmu_get_default_pd 164 (dev_priv->mmu), 165 pg->mmu_gatt_start, 166 dev_priv->vram_stolen_size >> PAGE_SHIFT); 167 up_read(&pg->sem); 168 psb_mmu_driver_takedown(dev_priv->mmu); 169 dev_priv->mmu = NULL; 170 } 171 psb_gtt_takedown(dev); 172 if (dev_priv->scratch_page) { 173 set_pages_wb(dev_priv->scratch_page, 1); 174 __free_page(dev_priv->scratch_page); 175 dev_priv->scratch_page = NULL; 176 } 177 if (dev_priv->vdc_reg) { 178 iounmap(dev_priv->vdc_reg); 179 dev_priv->vdc_reg = NULL; 180 } 181 if (dev_priv->sgx_reg) { 182 iounmap(dev_priv->sgx_reg); 183 dev_priv->sgx_reg = NULL; 184 } 185 if (dev_priv->aux_reg) { 186 iounmap(dev_priv->aux_reg); 187 dev_priv->aux_reg = NULL; 188 } 189 pci_dev_put(dev_priv->aux_pdev); 190 pci_dev_put(dev_priv->lpc_pdev); 191 192 /* Destroy VBT data */ 193 psb_intel_destroy_bios(dev); 194 195 kfree(dev_priv); 196 dev->dev_private = NULL; 197 } 198 gma_power_uninit(dev); 199 } 200 201 static int psb_driver_load(struct drm_device *dev, unsigned long flags) 202 { 203 struct drm_psb_private *dev_priv; 204 unsigned long resource_start, resource_len; 205 unsigned long irqflags; 206 int ret = -ENOMEM; 207 struct drm_connector *connector; 208 struct gma_encoder *gma_encoder; 209 struct psb_gtt *pg; 210 211 /* allocating and initializing driver private data */ 212 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 213 if (dev_priv == NULL) 214 return -ENOMEM; 215 216 dev_priv->ops = (struct psb_ops *)flags; 217 dev_priv->dev = dev; 218 dev->dev_private = (void *) dev_priv; 219 220 pg = &dev_priv->gtt; 221 222 pci_set_master(dev->pdev); 223 224 dev_priv->num_pipe = dev_priv->ops->pipes; 225 226 resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE); 227 228 dev_priv->vdc_reg = 229 ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE); 230 if (!dev_priv->vdc_reg) 231 goto out_err; 232 233 dev_priv->sgx_reg = ioremap(resource_start + dev_priv->ops->sgx_offset, 234 PSB_SGX_SIZE); 235 if (!dev_priv->sgx_reg) 236 goto out_err; 237 238 if (IS_MRST(dev)) { 239 int domain = pci_domain_nr(dev->pdev->bus); 240 241 dev_priv->aux_pdev = 242 pci_get_domain_bus_and_slot(domain, 0, 243 PCI_DEVFN(3, 0)); 244 245 if (dev_priv->aux_pdev) { 246 resource_start = pci_resource_start(dev_priv->aux_pdev, 247 PSB_AUX_RESOURCE); 248 resource_len = pci_resource_len(dev_priv->aux_pdev, 249 PSB_AUX_RESOURCE); 250 dev_priv->aux_reg = ioremap_nocache(resource_start, 251 resource_len); 252 if (!dev_priv->aux_reg) 253 goto out_err; 254 255 DRM_DEBUG_KMS("Found aux vdc"); 256 } else { 257 /* Couldn't find the aux vdc so map to primary vdc */ 258 dev_priv->aux_reg = dev_priv->vdc_reg; 259 DRM_DEBUG_KMS("Couldn't find aux pci device"); 260 } 261 dev_priv->gmbus_reg = dev_priv->aux_reg; 262 263 dev_priv->lpc_pdev = 264 pci_get_domain_bus_and_slot(domain, 0, 265 PCI_DEVFN(31, 0)); 266 if (dev_priv->lpc_pdev) { 267 pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA, 268 &dev_priv->lpc_gpio_base); 269 pci_write_config_dword(dev_priv->lpc_pdev, PSB_LPC_GBA, 270 (u32)dev_priv->lpc_gpio_base | (1L<<31)); 271 pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA, 272 &dev_priv->lpc_gpio_base); 273 dev_priv->lpc_gpio_base &= 0xffc0; 274 if (dev_priv->lpc_gpio_base) 275 DRM_DEBUG_KMS("Found LPC GPIO at 0x%04x\n", 276 dev_priv->lpc_gpio_base); 277 else { 278 pci_dev_put(dev_priv->lpc_pdev); 279 dev_priv->lpc_pdev = NULL; 280 } 281 } 282 } else { 283 dev_priv->gmbus_reg = dev_priv->vdc_reg; 284 } 285 286 psb_intel_opregion_setup(dev); 287 288 ret = dev_priv->ops->chip_setup(dev); 289 if (ret) 290 goto out_err; 291 292 /* Init OSPM support */ 293 gma_power_init(dev); 294 295 ret = -ENOMEM; 296 297 dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO); 298 if (!dev_priv->scratch_page) 299 goto out_err; 300 301 set_pages_uc(dev_priv->scratch_page, 1); 302 303 ret = psb_gtt_init(dev, 0); 304 if (ret) 305 goto out_err; 306 307 dev_priv->mmu = psb_mmu_driver_init(dev, 1, 0, 0); 308 if (!dev_priv->mmu) 309 goto out_err; 310 311 dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0); 312 if (!dev_priv->pf_pd) 313 goto out_err; 314 315 ret = psb_do_init(dev); 316 if (ret) 317 return ret; 318 319 /* Add stolen memory to SGX MMU */ 320 down_read(&pg->sem); 321 ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd(dev_priv->mmu), 322 dev_priv->stolen_base >> PAGE_SHIFT, 323 pg->gatt_start, 324 pg->stolen_size >> PAGE_SHIFT, 0); 325 up_read(&pg->sem); 326 327 psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0); 328 psb_mmu_set_pd_context(dev_priv->pf_pd, 1); 329 330 PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE); 331 PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE); 332 333 acpi_video_register(); 334 335 /* Setup vertical blanking handling */ 336 ret = drm_vblank_init(dev, dev_priv->num_pipe); 337 if (ret) 338 goto out_err; 339 340 /* 341 * Install interrupt handlers prior to powering off SGX or else we will 342 * crash. 343 */ 344 dev_priv->vdc_irq_mask = 0; 345 dev_priv->pipestat[0] = 0; 346 dev_priv->pipestat[1] = 0; 347 dev_priv->pipestat[2] = 0; 348 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 349 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM); 350 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R); 351 PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R); 352 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 353 354 drm_irq_install(dev, dev->pdev->irq); 355 356 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 357 dev->driver->get_vblank_counter = psb_get_vblank_counter; 358 359 psb_modeset_init(dev); 360 psb_fbdev_init(dev); 361 drm_kms_helper_poll_init(dev); 362 363 /* Only add backlight support if we have LVDS output */ 364 list_for_each_entry(connector, &dev->mode_config.connector_list, 365 head) { 366 gma_encoder = gma_attached_encoder(connector); 367 368 switch (gma_encoder->type) { 369 case INTEL_OUTPUT_LVDS: 370 case INTEL_OUTPUT_MIPI: 371 ret = gma_backlight_init(dev); 372 break; 373 } 374 } 375 376 if (ret) 377 return ret; 378 psb_intel_opregion_enable_asle(dev); 379 #if 0 380 /* Enable runtime pm at last */ 381 pm_runtime_enable(&dev->pdev->dev); 382 pm_runtime_set_active(&dev->pdev->dev); 383 #endif 384 /* Intel drm driver load is done, continue doing pvr load */ 385 return 0; 386 out_err: 387 psb_driver_unload(dev); 388 return ret; 389 } 390 391 static inline void get_brightness(struct backlight_device *bd) 392 { 393 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 394 if (bd) { 395 bd->props.brightness = bd->ops->get_brightness(bd); 396 backlight_update_status(bd); 397 } 398 #endif 399 } 400 401 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd, 402 unsigned long arg) 403 { 404 struct drm_file *file_priv = filp->private_data; 405 struct drm_device *dev = file_priv->minor->dev; 406 struct drm_psb_private *dev_priv = dev->dev_private; 407 static unsigned int runtime_allowed; 408 409 if (runtime_allowed == 1 && dev_priv->is_lvds_on) { 410 runtime_allowed++; 411 pm_runtime_allow(&dev->pdev->dev); 412 dev_priv->rpm_enabled = 1; 413 } 414 return drm_ioctl(filp, cmd, arg); 415 /* FIXME: do we need to wrap the other side of this */ 416 } 417 418 static int psb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 419 { 420 return drm_get_pci_dev(pdev, ent, &driver); 421 } 422 423 424 static void psb_pci_remove(struct pci_dev *pdev) 425 { 426 struct drm_device *dev = pci_get_drvdata(pdev); 427 drm_put_dev(dev); 428 } 429 430 static const struct dev_pm_ops psb_pm_ops = { 431 .resume = gma_power_resume, 432 .suspend = gma_power_suspend, 433 .thaw = gma_power_thaw, 434 .freeze = gma_power_freeze, 435 .restore = gma_power_restore, 436 .runtime_suspend = psb_runtime_suspend, 437 .runtime_resume = psb_runtime_resume, 438 .runtime_idle = psb_runtime_idle, 439 }; 440 441 static const struct vm_operations_struct psb_gem_vm_ops = { 442 .fault = psb_gem_fault, 443 .open = drm_gem_vm_open, 444 .close = drm_gem_vm_close, 445 }; 446 447 static const struct file_operations psb_gem_fops = { 448 .owner = THIS_MODULE, 449 .open = drm_open, 450 .release = drm_release, 451 .unlocked_ioctl = psb_unlocked_ioctl, 452 .compat_ioctl = drm_compat_ioctl, 453 .mmap = drm_gem_mmap, 454 .poll = drm_poll, 455 .read = drm_read, 456 }; 457 458 static struct drm_driver driver = { 459 .driver_features = DRIVER_MODESET | DRIVER_GEM, 460 .load = psb_driver_load, 461 .unload = psb_driver_unload, 462 .lastclose = drm_fb_helper_lastclose, 463 464 .num_ioctls = ARRAY_SIZE(psb_ioctls), 465 .irq_preinstall = psb_irq_preinstall, 466 .irq_postinstall = psb_irq_postinstall, 467 .irq_uninstall = psb_irq_uninstall, 468 .irq_handler = psb_irq_handler, 469 .enable_vblank = psb_enable_vblank, 470 .disable_vblank = psb_disable_vblank, 471 .get_vblank_counter = psb_get_vblank_counter, 472 473 .gem_free_object = psb_gem_free_object, 474 .gem_vm_ops = &psb_gem_vm_ops, 475 476 .dumb_create = psb_gem_dumb_create, 477 .ioctls = psb_ioctls, 478 .fops = &psb_gem_fops, 479 .name = DRIVER_NAME, 480 .desc = DRIVER_DESC, 481 .date = DRIVER_DATE, 482 .major = DRIVER_MAJOR, 483 .minor = DRIVER_MINOR, 484 .patchlevel = DRIVER_PATCHLEVEL 485 }; 486 487 static struct pci_driver psb_pci_driver = { 488 .name = DRIVER_NAME, 489 .id_table = pciidlist, 490 .probe = psb_pci_probe, 491 .remove = psb_pci_remove, 492 .driver.pm = &psb_pm_ops, 493 }; 494 495 static int __init psb_init(void) 496 { 497 return pci_register_driver(&psb_pci_driver); 498 } 499 500 static void __exit psb_exit(void) 501 { 502 pci_unregister_driver(&psb_pci_driver); 503 } 504 505 late_initcall(psb_init); 506 module_exit(psb_exit); 507 508 MODULE_AUTHOR(DRIVER_AUTHOR); 509 MODULE_DESCRIPTION(DRIVER_DESC); 510 MODULE_LICENSE("GPL"); 511