1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 * Dave Airlie <airlied@linux.ie> 8 * Jesse Barnes <jesse.barnes@intel.com> 9 */ 10 11 #include <linux/i2c.h> 12 #include <linux/pm_runtime.h> 13 14 #include <asm/intel-mid.h> 15 16 #include <drm/drm_edid.h> 17 #include <drm/drm_simple_kms_helper.h> 18 19 #include "intel_bios.h" 20 #include "power.h" 21 #include "psb_drv.h" 22 #include "psb_intel_drv.h" 23 #include "psb_intel_reg.h" 24 25 /* The max/min PWM frequency in BPCR[31:17] - */ 26 /* The smallest number is 1 (not 0) that can fit in the 27 * 15-bit field of the and then*/ 28 /* shifts to the left by one bit to get the actual 16-bit 29 * value that the 15-bits correspond to.*/ 30 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 31 #define BRIGHTNESS_MAX_LEVEL 100 32 33 /* 34 * Sets the power state for the panel. 35 */ 36 static void oaktrail_lvds_set_power(struct drm_device *dev, 37 struct gma_encoder *gma_encoder, 38 bool on) 39 { 40 u32 pp_status; 41 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 42 43 if (!gma_power_begin(dev, true)) 44 return; 45 46 if (on) { 47 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | 48 POWER_TARGET_ON); 49 do { 50 pp_status = REG_READ(PP_STATUS); 51 } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); 52 dev_priv->is_lvds_on = true; 53 if (dev_priv->ops->lvds_bl_power) 54 dev_priv->ops->lvds_bl_power(dev, true); 55 } else { 56 if (dev_priv->ops->lvds_bl_power) 57 dev_priv->ops->lvds_bl_power(dev, false); 58 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & 59 ~POWER_TARGET_ON); 60 do { 61 pp_status = REG_READ(PP_STATUS); 62 } while (pp_status & PP_ON); 63 dev_priv->is_lvds_on = false; 64 } 65 gma_power_end(dev); 66 } 67 68 static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode) 69 { 70 struct drm_device *dev = encoder->dev; 71 struct gma_encoder *gma_encoder = to_gma_encoder(encoder); 72 73 if (mode == DRM_MODE_DPMS_ON) 74 oaktrail_lvds_set_power(dev, gma_encoder, true); 75 else 76 oaktrail_lvds_set_power(dev, gma_encoder, false); 77 78 /* XXX: We never power down the LVDS pairs. */ 79 } 80 81 static void oaktrail_lvds_mode_set(struct drm_encoder *encoder, 82 struct drm_display_mode *mode, 83 struct drm_display_mode *adjusted_mode) 84 { 85 struct drm_device *dev = encoder->dev; 86 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 87 struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; 88 struct drm_connector_list_iter conn_iter; 89 struct drm_connector *connector = NULL; 90 struct drm_crtc *crtc = encoder->crtc; 91 u32 lvds_port; 92 uint64_t v = DRM_MODE_SCALE_FULLSCREEN; 93 94 if (!gma_power_begin(dev, true)) 95 return; 96 97 /* 98 * The LVDS pin pair will already have been turned on in the 99 * psb_intel_crtc_mode_set since it has a large impact on the DPLL 100 * settings. 101 */ 102 lvds_port = (REG_READ(LVDS) & 103 (~LVDS_PIPEB_SELECT)) | 104 LVDS_PORT_EN | 105 LVDS_BORDER_EN; 106 107 /* If the firmware says dither on Moorestown, or the BIOS does 108 on Oaktrail then enable dithering */ 109 if (mode_dev->panel_wants_dither || dev_priv->lvds_dither) 110 lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE; 111 112 REG_WRITE(LVDS, lvds_port); 113 114 /* Find the connector we're trying to set up */ 115 drm_connector_list_iter_begin(dev, &conn_iter); 116 drm_for_each_connector_iter(connector, &conn_iter) { 117 if (connector->encoder && connector->encoder->crtc == crtc) 118 break; 119 } 120 121 if (!connector) { 122 drm_connector_list_iter_end(&conn_iter); 123 DRM_ERROR("Couldn't find connector when setting mode"); 124 gma_power_end(dev); 125 return; 126 } 127 128 drm_object_property_get_value( &connector->base, 129 dev->mode_config.scaling_mode_property, &v); 130 drm_connector_list_iter_end(&conn_iter); 131 132 if (v == DRM_MODE_SCALE_NO_SCALE) 133 REG_WRITE(PFIT_CONTROL, 0); 134 else if (v == DRM_MODE_SCALE_ASPECT) { 135 if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) || 136 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { 137 if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) == 138 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) 139 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); 140 else if ((adjusted_mode->crtc_hdisplay * 141 mode->vdisplay) > (mode->hdisplay * 142 adjusted_mode->crtc_vdisplay)) 143 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | 144 PFIT_SCALING_MODE_PILLARBOX); 145 else 146 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE | 147 PFIT_SCALING_MODE_LETTERBOX); 148 } else 149 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); 150 } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/ 151 REG_WRITE(PFIT_CONTROL, PFIT_ENABLE); 152 153 gma_power_end(dev); 154 } 155 156 static void oaktrail_lvds_prepare(struct drm_encoder *encoder) 157 { 158 struct drm_device *dev = encoder->dev; 159 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 160 struct gma_encoder *gma_encoder = to_gma_encoder(encoder); 161 struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; 162 163 if (!gma_power_begin(dev, true)) 164 return; 165 166 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 167 mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL & 168 BACKLIGHT_DUTY_CYCLE_MASK); 169 oaktrail_lvds_set_power(dev, gma_encoder, false); 170 gma_power_end(dev); 171 } 172 173 static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev) 174 { 175 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 176 u32 ret; 177 178 if (gma_power_begin(dev, false)) { 179 ret = ((REG_READ(BLC_PWM_CTL) & 180 BACKLIGHT_MODULATION_FREQ_MASK) >> 181 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; 182 183 gma_power_end(dev); 184 } else 185 ret = ((dev_priv->regs.saveBLC_PWM_CTL & 186 BACKLIGHT_MODULATION_FREQ_MASK) >> 187 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; 188 189 return ret; 190 } 191 192 static void oaktrail_lvds_commit(struct drm_encoder *encoder) 193 { 194 struct drm_device *dev = encoder->dev; 195 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 196 struct gma_encoder *gma_encoder = to_gma_encoder(encoder); 197 struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; 198 199 if (mode_dev->backlight_duty_cycle == 0) 200 mode_dev->backlight_duty_cycle = 201 oaktrail_lvds_get_max_backlight(dev); 202 oaktrail_lvds_set_power(dev, gma_encoder, true); 203 } 204 205 static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = { 206 .dpms = oaktrail_lvds_dpms, 207 .mode_fixup = psb_intel_lvds_mode_fixup, 208 .prepare = oaktrail_lvds_prepare, 209 .mode_set = oaktrail_lvds_mode_set, 210 .commit = oaktrail_lvds_commit, 211 }; 212 213 /* Returns the panel fixed mode from configuration. */ 214 215 static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev, 216 struct psb_intel_mode_device *mode_dev) 217 { 218 struct drm_display_mode *mode = NULL; 219 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 220 struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD; 221 222 mode_dev->panel_fixed_mode = NULL; 223 224 /* Use the firmware provided data on Moorestown */ 225 if (dev_priv->has_gct) { 226 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 227 if (!mode) 228 return; 229 230 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; 231 mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo; 232 mode->hsync_start = mode->hdisplay + \ 233 ((ti->hsync_offset_hi << 8) | \ 234 ti->hsync_offset_lo); 235 mode->hsync_end = mode->hsync_start + \ 236 ((ti->hsync_pulse_width_hi << 8) | \ 237 ti->hsync_pulse_width_lo); 238 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ 239 ti->hblank_lo); 240 mode->vsync_start = \ 241 mode->vdisplay + ((ti->vsync_offset_hi << 4) | \ 242 ti->vsync_offset_lo); 243 mode->vsync_end = \ 244 mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \ 245 ti->vsync_pulse_width_lo); 246 mode->vtotal = mode->vdisplay + \ 247 ((ti->vblank_hi << 8) | ti->vblank_lo); 248 mode->clock = ti->pixel_clock * 10; 249 #if 0 250 pr_info("hdisplay is %d\n", mode->hdisplay); 251 pr_info("vdisplay is %d\n", mode->vdisplay); 252 pr_info("HSS is %d\n", mode->hsync_start); 253 pr_info("HSE is %d\n", mode->hsync_end); 254 pr_info("htotal is %d\n", mode->htotal); 255 pr_info("VSS is %d\n", mode->vsync_start); 256 pr_info("VSE is %d\n", mode->vsync_end); 257 pr_info("vtotal is %d\n", mode->vtotal); 258 pr_info("clock is %d\n", mode->clock); 259 #endif 260 mode_dev->panel_fixed_mode = mode; 261 } 262 263 /* Use the BIOS VBT mode if available */ 264 if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode) 265 mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, 266 mode_dev->vbt_mode); 267 268 /* Then try the LVDS VBT mode */ 269 if (mode_dev->panel_fixed_mode == NULL) 270 if (dev_priv->lfp_lvds_vbt_mode) 271 mode_dev->panel_fixed_mode = 272 drm_mode_duplicate(dev, 273 dev_priv->lfp_lvds_vbt_mode); 274 275 /* If we still got no mode then bail */ 276 if (mode_dev->panel_fixed_mode == NULL) 277 return; 278 279 drm_mode_set_name(mode_dev->panel_fixed_mode); 280 drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0); 281 } 282 283 /** 284 * oaktrail_lvds_init - setup LVDS connectors on this device 285 * @dev: drm device 286 * @mode_dev: PSB mode device 287 * 288 * Create the connector, register the LVDS DDC bus, and try to figure out what 289 * modes we can display on the LVDS panel (if present). 290 */ 291 void oaktrail_lvds_init(struct drm_device *dev, 292 struct psb_intel_mode_device *mode_dev) 293 { 294 struct gma_encoder *gma_encoder; 295 struct gma_connector *gma_connector; 296 struct gma_i2c_chan *ddc_bus; 297 struct drm_connector *connector; 298 struct drm_encoder *encoder; 299 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 300 struct edid *edid; 301 struct i2c_adapter *i2c_adap; 302 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 303 int ret; 304 305 gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); 306 if (!gma_encoder) 307 return; 308 309 gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); 310 if (!gma_connector) 311 goto err_free_encoder; 312 313 connector = &gma_connector->base; 314 encoder = &gma_encoder->base; 315 dev_priv->is_lvds_on = true; 316 ret = drm_connector_init(dev, connector, 317 &psb_intel_lvds_connector_funcs, 318 DRM_MODE_CONNECTOR_LVDS); 319 if (ret) 320 goto err_free_connector; 321 322 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS); 323 if (ret) 324 goto err_connector_cleanup; 325 326 gma_connector_attach_encoder(gma_connector, gma_encoder); 327 gma_encoder->type = INTEL_OUTPUT_LVDS; 328 329 drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs); 330 drm_connector_helper_add(connector, 331 &psb_intel_lvds_connector_helper_funcs); 332 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 333 connector->interlace_allowed = false; 334 connector->doublescan_allowed = false; 335 336 drm_object_attach_property(&connector->base, 337 dev->mode_config.scaling_mode_property, 338 DRM_MODE_SCALE_FULLSCREEN); 339 drm_object_attach_property(&connector->base, 340 dev_priv->backlight_property, 341 BRIGHTNESS_MAX_LEVEL); 342 343 mode_dev->panel_wants_dither = false; 344 if (dev_priv->has_gct) 345 mode_dev->panel_wants_dither = (dev_priv->gct_data. 346 Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE); 347 if (dev_priv->lvds_dither) 348 mode_dev->panel_wants_dither = 1; 349 350 /* 351 * LVDS discovery: 352 * 1) check for EDID on DDC 353 * 2) check for VBT data 354 * 3) check to see if LVDS is already on 355 * if none of the above, no panel 356 * 4) make sure lid is open 357 * if closed, act like it's not there for now 358 */ 359 360 edid = NULL; 361 mutex_lock(&dev->mode_config.mutex); 362 363 i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus); 364 if (i2c_adap) 365 edid = drm_get_edid(connector, i2c_adap); 366 367 if (edid == NULL && dev_priv->lpc_gpio_base) { 368 ddc_bus = oaktrail_lvds_i2c_init(dev); 369 if (!IS_ERR(ddc_bus)) { 370 i2c_adap = &ddc_bus->base; 371 edid = drm_get_edid(connector, i2c_adap); 372 } 373 } 374 375 /* 376 * Due to the logic in probing for i2c buses above we do not know the 377 * i2c_adap until now. Hence we cannot use drm_connector_init_with_ddc() 378 * but must instead set connector->ddc manually here. 379 */ 380 connector->ddc = i2c_adap; 381 382 /* 383 * Attempt to get the fixed panel mode from DDC. Assume that the 384 * preferred mode is the right one. 385 */ 386 if (edid) { 387 drm_connector_update_edid_property(connector, edid); 388 drm_add_edid_modes(connector, edid); 389 kfree(edid); 390 391 list_for_each_entry(scan, &connector->probed_modes, head) { 392 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 393 mode_dev->panel_fixed_mode = 394 drm_mode_duplicate(dev, scan); 395 goto out; /* FIXME: check for quirks */ 396 } 397 } 398 } else 399 dev_err(dev->dev, "No ddc adapter available!\n"); 400 /* 401 * If we didn't get EDID, try geting panel timing 402 * from configuration data 403 */ 404 oaktrail_lvds_get_configuration_mode(dev, mode_dev); 405 406 if (mode_dev->panel_fixed_mode) { 407 mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 408 goto out; /* FIXME: check for quirks */ 409 } 410 411 /* If we still don't have a mode after all that, give up. */ 412 if (!mode_dev->panel_fixed_mode) { 413 dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n"); 414 goto err_unlock; 415 } 416 417 out: 418 mutex_unlock(&dev->mode_config.mutex); 419 420 return; 421 422 err_unlock: 423 mutex_unlock(&dev->mode_config.mutex); 424 gma_i2c_destroy(to_gma_i2c_chan(connector->ddc)); 425 drm_encoder_cleanup(encoder); 426 err_connector_cleanup: 427 drm_connector_cleanup(connector); 428 err_free_connector: 429 kfree(gma_connector); 430 err_free_encoder: 431 kfree(gma_encoder); 432 } 433 434