1 /* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Li Peng <peng.li@intel.com> 25 */ 26 27 #include <drm/drmP.h> 28 #include <drm/drm.h> 29 #include "psb_intel_drv.h" 30 #include "psb_intel_reg.h" 31 #include "psb_drv.h" 32 33 #define HDMI_READ(reg) readl(hdmi_dev->regs + (reg)) 34 #define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg)) 35 36 #define HDMI_HCR 0x1000 37 #define HCR_ENABLE_HDCP (1 << 5) 38 #define HCR_ENABLE_AUDIO (1 << 2) 39 #define HCR_ENABLE_PIXEL (1 << 1) 40 #define HCR_ENABLE_TMDS (1 << 0) 41 42 #define HDMI_HICR 0x1004 43 #define HDMI_HSR 0x1008 44 #define HDMI_HISR 0x100C 45 #define HDMI_DETECT_HDP (1 << 0) 46 47 #define HDMI_VIDEO_REG 0x3000 48 #define HDMI_UNIT_EN (1 << 7) 49 #define HDMI_MODE_OUTPUT (1 << 0) 50 #define HDMI_HBLANK_A 0x3100 51 52 #define HDMI_AUDIO_CTRL 0x4000 53 #define HDMI_ENABLE_AUDIO (1 << 0) 54 55 #define PCH_HTOTAL_B 0x3100 56 #define PCH_HBLANK_B 0x3104 57 #define PCH_HSYNC_B 0x3108 58 #define PCH_VTOTAL_B 0x310C 59 #define PCH_VBLANK_B 0x3110 60 #define PCH_VSYNC_B 0x3114 61 #define PCH_PIPEBSRC 0x311C 62 63 #define PCH_PIPEB_DSL 0x3800 64 #define PCH_PIPEB_SLC 0x3804 65 #define PCH_PIPEBCONF 0x3808 66 #define PCH_PIPEBSTAT 0x3824 67 68 #define CDVO_DFT 0x5000 69 #define CDVO_SLEWRATE 0x5004 70 #define CDVO_STRENGTH 0x5008 71 #define CDVO_RCOMP 0x500C 72 73 #define DPLL_CTRL 0x6000 74 #define DPLL_PDIV_SHIFT 16 75 #define DPLL_PDIV_MASK (0xf << 16) 76 #define DPLL_PWRDN (1 << 4) 77 #define DPLL_RESET (1 << 3) 78 #define DPLL_FASTEN (1 << 2) 79 #define DPLL_ENSTAT (1 << 1) 80 #define DPLL_DITHEN (1 << 0) 81 82 #define DPLL_DIV_CTRL 0x6004 83 #define DPLL_CLKF_MASK 0xffffffc0 84 #define DPLL_CLKR_MASK (0x3f) 85 86 #define DPLL_CLK_ENABLE 0x6008 87 #define DPLL_EN_DISP (1 << 31) 88 #define DPLL_SEL_HDMI (1 << 8) 89 #define DPLL_EN_HDMI (1 << 1) 90 #define DPLL_EN_VGA (1 << 0) 91 92 #define DPLL_ADJUST 0x600C 93 #define DPLL_STATUS 0x6010 94 #define DPLL_UPDATE 0x6014 95 #define DPLL_DFT 0x6020 96 97 struct intel_range { 98 int min, max; 99 }; 100 101 struct oaktrail_hdmi_limit { 102 struct intel_range vco, np, nr, nf; 103 }; 104 105 struct oaktrail_hdmi_clock { 106 int np; 107 int nr; 108 int nf; 109 int dot; 110 }; 111 112 #define VCO_MIN 320000 113 #define VCO_MAX 1650000 114 #define NP_MIN 1 115 #define NP_MAX 15 116 #define NR_MIN 1 117 #define NR_MAX 64 118 #define NF_MIN 2 119 #define NF_MAX 4095 120 121 static const struct oaktrail_hdmi_limit oaktrail_hdmi_limit = { 122 .vco = { .min = VCO_MIN, .max = VCO_MAX }, 123 .np = { .min = NP_MIN, .max = NP_MAX }, 124 .nr = { .min = NR_MIN, .max = NR_MAX }, 125 .nf = { .min = NF_MIN, .max = NF_MAX }, 126 }; 127 128 static void oaktrail_hdmi_audio_enable(struct drm_device *dev) 129 { 130 struct drm_psb_private *dev_priv = dev->dev_private; 131 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 132 133 HDMI_WRITE(HDMI_HCR, 0x67); 134 HDMI_READ(HDMI_HCR); 135 136 HDMI_WRITE(0x51a8, 0x10); 137 HDMI_READ(0x51a8); 138 139 HDMI_WRITE(HDMI_AUDIO_CTRL, 0x1); 140 HDMI_READ(HDMI_AUDIO_CTRL); 141 } 142 143 static void oaktrail_hdmi_audio_disable(struct drm_device *dev) 144 { 145 struct drm_psb_private *dev_priv = dev->dev_private; 146 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 147 148 HDMI_WRITE(0x51a8, 0x0); 149 HDMI_READ(0x51a8); 150 151 HDMI_WRITE(HDMI_AUDIO_CTRL, 0x0); 152 HDMI_READ(HDMI_AUDIO_CTRL); 153 154 HDMI_WRITE(HDMI_HCR, 0x47); 155 HDMI_READ(HDMI_HCR); 156 } 157 158 static void wait_for_vblank(struct drm_device *dev) 159 { 160 /* Wait for 20ms, i.e. one cycle at 50hz. */ 161 mdelay(20); 162 } 163 164 static unsigned int htotal_calculate(struct drm_display_mode *mode) 165 { 166 u32 htotal, new_crtc_htotal; 167 168 htotal = (mode->crtc_hdisplay - 1) | ((mode->crtc_htotal - 1) << 16); 169 170 /* 171 * 1024 x 768 new_crtc_htotal = 0x1024; 172 * 1280 x 1024 new_crtc_htotal = 0x0c34; 173 */ 174 new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock; 175 176 DRM_DEBUG_KMS("new crtc htotal 0x%4x\n", new_crtc_htotal); 177 return (mode->crtc_hdisplay - 1) | (new_crtc_htotal << 16); 178 } 179 180 static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc, int target, 181 int refclk, struct oaktrail_hdmi_clock *best_clock) 182 { 183 int np_min, np_max, nr_min, nr_max; 184 int np, nr, nf; 185 186 np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10); 187 np_max = oaktrail_hdmi_limit.vco.max / (target * 10); 188 if (np_min < oaktrail_hdmi_limit.np.min) 189 np_min = oaktrail_hdmi_limit.np.min; 190 if (np_max > oaktrail_hdmi_limit.np.max) 191 np_max = oaktrail_hdmi_limit.np.max; 192 193 nr_min = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_max)); 194 nr_max = DIV_ROUND_UP((refclk * 1000), (target * 10 * np_min)); 195 if (nr_min < oaktrail_hdmi_limit.nr.min) 196 nr_min = oaktrail_hdmi_limit.nr.min; 197 if (nr_max > oaktrail_hdmi_limit.nr.max) 198 nr_max = oaktrail_hdmi_limit.nr.max; 199 200 np = DIV_ROUND_UP((refclk * 1000), (target * 10 * nr_max)); 201 nr = DIV_ROUND_UP((refclk * 1000), (target * 10 * np)); 202 nf = DIV_ROUND_CLOSEST((target * 10 * np * nr), refclk); 203 DRM_DEBUG_KMS("np, nr, nf %d %d %d\n", np, nr, nf); 204 205 /* 206 * 1024 x 768 np = 1; nr = 0x26; nf = 0x0fd8000; 207 * 1280 x 1024 np = 1; nr = 0x17; nf = 0x1034000; 208 */ 209 best_clock->np = np; 210 best_clock->nr = nr - 1; 211 best_clock->nf = (nf << 14); 212 } 213 214 static void scu_busy_loop(void __iomem *scu_base) 215 { 216 u32 status = 0; 217 u32 loop_count = 0; 218 219 status = readl(scu_base + 0x04); 220 while (status & 1) { 221 udelay(1); /* scu processing time is in few u secods */ 222 status = readl(scu_base + 0x04); 223 loop_count++; 224 /* break if scu doesn't reset busy bit after huge retry */ 225 if (loop_count > 1000) { 226 DRM_DEBUG_KMS("SCU IPC timed out"); 227 return; 228 } 229 } 230 } 231 232 /* 233 * You don't want to know, you really really don't want to know.... 234 * 235 * This is magic. However it's safe magic because of the way the platform 236 * works and it is necessary magic. 237 */ 238 static void oaktrail_hdmi_reset(struct drm_device *dev) 239 { 240 void __iomem *base; 241 unsigned long scu_ipc_mmio = 0xff11c000UL; 242 int scu_len = 1024; 243 244 base = ioremap((resource_size_t)scu_ipc_mmio, scu_len); 245 if (base == NULL) { 246 DRM_ERROR("failed to map scu mmio\n"); 247 return; 248 } 249 250 /* scu ipc: assert hdmi controller reset */ 251 writel(0xff11d118, base + 0x0c); 252 writel(0x7fffffdf, base + 0x80); 253 writel(0x42005, base + 0x0); 254 scu_busy_loop(base); 255 256 /* scu ipc: de-assert hdmi controller reset */ 257 writel(0xff11d118, base + 0x0c); 258 writel(0x7fffffff, base + 0x80); 259 writel(0x42005, base + 0x0); 260 scu_busy_loop(base); 261 262 iounmap(base); 263 } 264 265 int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, 266 struct drm_display_mode *mode, 267 struct drm_display_mode *adjusted_mode, 268 int x, int y, 269 struct drm_framebuffer *old_fb) 270 { 271 struct drm_device *dev = crtc->dev; 272 struct drm_psb_private *dev_priv = dev->dev_private; 273 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 274 int pipe = 1; 275 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 276 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 277 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 278 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; 279 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; 280 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; 281 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; 282 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; 283 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; 284 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 285 int refclk; 286 struct oaktrail_hdmi_clock clock; 287 u32 dspcntr, pipeconf, dpll, temp; 288 int dspcntr_reg = DSPBCNTR; 289 290 if (!gma_power_begin(dev, true)) 291 return 0; 292 293 /* Disable the VGA plane that we never use */ 294 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 295 296 /* Disable dpll if necessary */ 297 dpll = REG_READ(DPLL_CTRL); 298 if ((dpll & DPLL_PWRDN) == 0) { 299 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); 300 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); 301 REG_WRITE(DPLL_STATUS, 0x1); 302 } 303 udelay(150); 304 305 /* Reset controller */ 306 oaktrail_hdmi_reset(dev); 307 308 /* program and enable dpll */ 309 refclk = 25000; 310 oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock); 311 312 /* Set the DPLL */ 313 dpll = REG_READ(DPLL_CTRL); 314 dpll &= ~DPLL_PDIV_MASK; 315 dpll &= ~(DPLL_PWRDN | DPLL_RESET); 316 REG_WRITE(DPLL_CTRL, 0x00000008); 317 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); 318 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); 319 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); 320 REG_WRITE(DPLL_UPDATE, 0x80000000); 321 REG_WRITE(DPLL_CLK_ENABLE, 0x80050102); 322 udelay(150); 323 324 /* configure HDMI */ 325 HDMI_WRITE(0x1004, 0x1fd); 326 HDMI_WRITE(0x2000, 0x1); 327 HDMI_WRITE(0x2008, 0x0); 328 HDMI_WRITE(0x3130, 0x8); 329 HDMI_WRITE(0x101c, 0x1800810); 330 331 temp = htotal_calculate(adjusted_mode); 332 REG_WRITE(htot_reg, temp); 333 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 334 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 335 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); 336 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); 337 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 338 REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); 339 340 REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); 341 REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); 342 REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); 343 REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16)); 344 REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - 1) << 16)); 345 REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); 346 REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) | (mode->crtc_vdisplay - 1)); 347 348 temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; 349 HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp); 350 351 REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 352 REG_WRITE(dsppos_reg, 0); 353 354 /* Flush the plane changes */ 355 { 356 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 357 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 358 } 359 360 /* Set up the display plane register */ 361 dspcntr = REG_READ(dspcntr_reg); 362 dspcntr |= DISPPLANE_GAMMA_ENABLE; 363 dspcntr |= DISPPLANE_SEL_PIPE_B; 364 dspcntr |= DISPLAY_PLANE_ENABLE; 365 366 /* setup pipeconf */ 367 pipeconf = REG_READ(pipeconf_reg); 368 pipeconf |= PIPEACONF_ENABLE; 369 370 REG_WRITE(pipeconf_reg, pipeconf); 371 REG_READ(pipeconf_reg); 372 373 REG_WRITE(PCH_PIPEBCONF, pipeconf); 374 REG_READ(PCH_PIPEBCONF); 375 wait_for_vblank(dev); 376 377 REG_WRITE(dspcntr_reg, dspcntr); 378 wait_for_vblank(dev); 379 380 gma_power_end(dev); 381 382 return 0; 383 } 384 385 void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode) 386 { 387 struct drm_device *dev = crtc->dev; 388 u32 temp; 389 390 DRM_DEBUG_KMS("%s %d\n", __func__, mode); 391 392 switch (mode) { 393 case DRM_MODE_DPMS_OFF: 394 REG_WRITE(VGACNTRL, 0x80000000); 395 396 /* Disable plane */ 397 temp = REG_READ(DSPBCNTR); 398 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 399 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE); 400 REG_READ(DSPBCNTR); 401 /* Flush the plane changes */ 402 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); 403 REG_READ(DSPBSURF); 404 } 405 406 /* Disable pipe B */ 407 temp = REG_READ(PIPEBCONF); 408 if ((temp & PIPEACONF_ENABLE) != 0) { 409 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE); 410 REG_READ(PIPEBCONF); 411 } 412 413 /* Disable LNW Pipes, etc */ 414 temp = REG_READ(PCH_PIPEBCONF); 415 if ((temp & PIPEACONF_ENABLE) != 0) { 416 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE); 417 REG_READ(PCH_PIPEBCONF); 418 } 419 420 /* wait for pipe off */ 421 udelay(150); 422 423 /* Disable dpll */ 424 temp = REG_READ(DPLL_CTRL); 425 if ((temp & DPLL_PWRDN) == 0) { 426 REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET)); 427 REG_WRITE(DPLL_STATUS, 0x1); 428 } 429 430 /* wait for dpll off */ 431 udelay(150); 432 433 break; 434 case DRM_MODE_DPMS_ON: 435 case DRM_MODE_DPMS_STANDBY: 436 case DRM_MODE_DPMS_SUSPEND: 437 /* Enable dpll */ 438 temp = REG_READ(DPLL_CTRL); 439 if ((temp & DPLL_PWRDN) != 0) { 440 REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET)); 441 temp = REG_READ(DPLL_CLK_ENABLE); 442 REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI); 443 REG_READ(DPLL_CLK_ENABLE); 444 } 445 /* wait for dpll warm up */ 446 udelay(150); 447 448 /* Enable pipe B */ 449 temp = REG_READ(PIPEBCONF); 450 if ((temp & PIPEACONF_ENABLE) == 0) { 451 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE); 452 REG_READ(PIPEBCONF); 453 } 454 455 /* Enable LNW Pipe B */ 456 temp = REG_READ(PCH_PIPEBCONF); 457 if ((temp & PIPEACONF_ENABLE) == 0) { 458 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE); 459 REG_READ(PCH_PIPEBCONF); 460 } 461 462 wait_for_vblank(dev); 463 464 /* Enable plane */ 465 temp = REG_READ(DSPBCNTR); 466 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 467 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE); 468 /* Flush the plane changes */ 469 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); 470 REG_READ(DSPBSURF); 471 } 472 473 psb_intel_crtc_load_lut(crtc); 474 } 475 476 /* DSPARB */ 477 REG_WRITE(DSPARB, 0x00003fbf); 478 479 /* FW1 */ 480 REG_WRITE(0x70034, 0x3f880a0a); 481 482 /* FW2 */ 483 REG_WRITE(0x70038, 0x0b060808); 484 485 /* FW4 */ 486 REG_WRITE(0x70050, 0x08030404); 487 488 /* FW5 */ 489 REG_WRITE(0x70054, 0x04040404); 490 491 /* LNC Chicken Bits - Squawk! */ 492 REG_WRITE(0x70400, 0x4000); 493 494 return; 495 } 496 497 static void oaktrail_hdmi_dpms(struct drm_encoder *encoder, int mode) 498 { 499 static int dpms_mode = -1; 500 501 struct drm_device *dev = encoder->dev; 502 struct drm_psb_private *dev_priv = dev->dev_private; 503 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 504 u32 temp; 505 506 if (dpms_mode == mode) 507 return; 508 509 if (mode != DRM_MODE_DPMS_ON) 510 temp = 0x0; 511 else 512 temp = 0x99; 513 514 dpms_mode = mode; 515 HDMI_WRITE(HDMI_VIDEO_REG, temp); 516 } 517 518 static int oaktrail_hdmi_mode_valid(struct drm_connector *connector, 519 struct drm_display_mode *mode) 520 { 521 if (mode->clock > 165000) 522 return MODE_CLOCK_HIGH; 523 if (mode->clock < 20000) 524 return MODE_CLOCK_LOW; 525 526 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 527 return MODE_NO_DBLESCAN; 528 529 return MODE_OK; 530 } 531 532 static bool oaktrail_hdmi_mode_fixup(struct drm_encoder *encoder, 533 const struct drm_display_mode *mode, 534 struct drm_display_mode *adjusted_mode) 535 { 536 return true; 537 } 538 539 static enum drm_connector_status 540 oaktrail_hdmi_detect(struct drm_connector *connector, bool force) 541 { 542 enum drm_connector_status status; 543 struct drm_device *dev = connector->dev; 544 struct drm_psb_private *dev_priv = dev->dev_private; 545 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 546 u32 temp; 547 548 temp = HDMI_READ(HDMI_HSR); 549 DRM_DEBUG_KMS("HDMI_HSR %x\n", temp); 550 551 if ((temp & HDMI_DETECT_HDP) != 0) 552 status = connector_status_connected; 553 else 554 status = connector_status_disconnected; 555 556 return status; 557 } 558 559 static const unsigned char raw_edid[] = { 560 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x10, 0xac, 0x2f, 0xa0, 561 0x53, 0x55, 0x33, 0x30, 0x16, 0x13, 0x01, 0x03, 0x0e, 0x3a, 0x24, 0x78, 562 0xea, 0xe9, 0xf5, 0xac, 0x51, 0x30, 0xb4, 0x25, 0x11, 0x50, 0x54, 0xa5, 563 0x4b, 0x00, 0x81, 0x80, 0xa9, 0x40, 0x71, 0x4f, 0xb3, 0x00, 0x01, 0x01, 564 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0, 565 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x46, 0x6c, 0x21, 0x00, 0x00, 0x1a, 566 0x00, 0x00, 0x00, 0xff, 0x00, 0x47, 0x4e, 0x37, 0x32, 0x31, 0x39, 0x35, 567 0x52, 0x30, 0x33, 0x55, 0x53, 0x0a, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x44, 568 0x45, 0x4c, 0x4c, 0x20, 0x32, 0x37, 0x30, 0x39, 0x57, 0x0a, 0x20, 0x20, 569 0x00, 0x00, 0x00, 0xfd, 0x00, 0x38, 0x4c, 0x1e, 0x53, 0x11, 0x00, 0x0a, 570 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x8d 571 }; 572 573 static int oaktrail_hdmi_get_modes(struct drm_connector *connector) 574 { 575 struct i2c_adapter *i2c_adap; 576 struct edid *edid; 577 int ret = 0; 578 579 /* 580 * FIXME: We need to figure this lot out. In theory we can 581 * read the EDID somehow but I've yet to find working reference 582 * code. 583 */ 584 i2c_adap = i2c_get_adapter(3); 585 if (i2c_adap == NULL) { 586 DRM_ERROR("No ddc adapter available!\n"); 587 edid = (struct edid *)raw_edid; 588 } else { 589 edid = (struct edid *)raw_edid; 590 /* FIXME ? edid = drm_get_edid(connector, i2c_adap); */ 591 } 592 593 if (edid) { 594 drm_mode_connector_update_edid_property(connector, edid); 595 ret = drm_add_edid_modes(connector, edid); 596 } 597 return ret; 598 } 599 600 static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder, 601 struct drm_display_mode *mode, 602 struct drm_display_mode *adjusted_mode) 603 { 604 struct drm_device *dev = encoder->dev; 605 606 oaktrail_hdmi_audio_enable(dev); 607 return; 608 } 609 610 static void oaktrail_hdmi_destroy(struct drm_connector *connector) 611 { 612 return; 613 } 614 615 static const struct drm_encoder_helper_funcs oaktrail_hdmi_helper_funcs = { 616 .dpms = oaktrail_hdmi_dpms, 617 .mode_fixup = oaktrail_hdmi_mode_fixup, 618 .prepare = psb_intel_encoder_prepare, 619 .mode_set = oaktrail_hdmi_mode_set, 620 .commit = psb_intel_encoder_commit, 621 }; 622 623 static const struct drm_connector_helper_funcs 624 oaktrail_hdmi_connector_helper_funcs = { 625 .get_modes = oaktrail_hdmi_get_modes, 626 .mode_valid = oaktrail_hdmi_mode_valid, 627 .best_encoder = psb_intel_best_encoder, 628 }; 629 630 static const struct drm_connector_funcs oaktrail_hdmi_connector_funcs = { 631 .dpms = drm_helper_connector_dpms, 632 .detect = oaktrail_hdmi_detect, 633 .fill_modes = drm_helper_probe_single_connector_modes, 634 .destroy = oaktrail_hdmi_destroy, 635 }; 636 637 static void oaktrail_hdmi_enc_destroy(struct drm_encoder *encoder) 638 { 639 drm_encoder_cleanup(encoder); 640 } 641 642 static const struct drm_encoder_funcs oaktrail_hdmi_enc_funcs = { 643 .destroy = oaktrail_hdmi_enc_destroy, 644 }; 645 646 void oaktrail_hdmi_init(struct drm_device *dev, 647 struct psb_intel_mode_device *mode_dev) 648 { 649 struct psb_intel_encoder *psb_intel_encoder; 650 struct psb_intel_connector *psb_intel_connector; 651 struct drm_connector *connector; 652 struct drm_encoder *encoder; 653 654 psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL); 655 if (!psb_intel_encoder) 656 return; 657 658 psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL); 659 if (!psb_intel_connector) 660 goto failed_connector; 661 662 connector = &psb_intel_connector->base; 663 encoder = &psb_intel_encoder->base; 664 drm_connector_init(dev, connector, 665 &oaktrail_hdmi_connector_funcs, 666 DRM_MODE_CONNECTOR_DVID); 667 668 drm_encoder_init(dev, encoder, 669 &oaktrail_hdmi_enc_funcs, 670 DRM_MODE_ENCODER_TMDS); 671 672 psb_intel_connector_attach_encoder(psb_intel_connector, 673 psb_intel_encoder); 674 675 psb_intel_encoder->type = INTEL_OUTPUT_HDMI; 676 drm_encoder_helper_add(encoder, &oaktrail_hdmi_helper_funcs); 677 drm_connector_helper_add(connector, &oaktrail_hdmi_connector_helper_funcs); 678 679 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 680 connector->interlace_allowed = false; 681 connector->doublescan_allowed = false; 682 drm_sysfs_connector_add(connector); 683 dev_info(dev->dev, "HDMI initialised.\n"); 684 685 return; 686 687 failed_connector: 688 kfree(psb_intel_encoder); 689 } 690 691 static DEFINE_PCI_DEVICE_TABLE(hdmi_ids) = { 692 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080d) }, 693 { 0 } 694 }; 695 696 void oaktrail_hdmi_setup(struct drm_device *dev) 697 { 698 struct drm_psb_private *dev_priv = dev->dev_private; 699 struct pci_dev *pdev; 700 struct oaktrail_hdmi_dev *hdmi_dev; 701 int ret; 702 703 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x080d, NULL); 704 if (!pdev) 705 return; 706 707 hdmi_dev = kzalloc(sizeof(struct oaktrail_hdmi_dev), GFP_KERNEL); 708 if (!hdmi_dev) { 709 dev_err(dev->dev, "failed to allocate memory\n"); 710 goto out; 711 } 712 713 714 ret = pci_enable_device(pdev); 715 if (ret) { 716 dev_err(dev->dev, "failed to enable hdmi controller\n"); 717 goto free; 718 } 719 720 hdmi_dev->mmio = pci_resource_start(pdev, 0); 721 hdmi_dev->mmio_len = pci_resource_len(pdev, 0); 722 hdmi_dev->regs = ioremap(hdmi_dev->mmio, hdmi_dev->mmio_len); 723 if (!hdmi_dev->regs) { 724 dev_err(dev->dev, "failed to map hdmi mmio\n"); 725 goto free; 726 } 727 728 hdmi_dev->dev = pdev; 729 pci_set_drvdata(pdev, hdmi_dev); 730 731 /* Initialize i2c controller */ 732 ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev); 733 if (ret) 734 dev_err(dev->dev, "HDMI I2C initialization failed\n"); 735 736 dev_priv->hdmi_priv = hdmi_dev; 737 oaktrail_hdmi_audio_disable(dev); 738 739 dev_info(dev->dev, "HDMI hardware present.\n"); 740 741 return; 742 743 free: 744 kfree(hdmi_dev); 745 out: 746 return; 747 } 748 749 void oaktrail_hdmi_teardown(struct drm_device *dev) 750 { 751 struct drm_psb_private *dev_priv = dev->dev_private; 752 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 753 struct pci_dev *pdev; 754 755 if (hdmi_dev) { 756 pdev = hdmi_dev->dev; 757 pci_set_drvdata(pdev, NULL); 758 oaktrail_hdmi_i2c_exit(pdev); 759 iounmap(hdmi_dev->regs); 760 kfree(hdmi_dev); 761 pci_dev_put(pdev); 762 } 763 } 764 765 /* save HDMI register state */ 766 void oaktrail_hdmi_save(struct drm_device *dev) 767 { 768 struct drm_psb_private *dev_priv = dev->dev_private; 769 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 770 struct psb_state *regs = &dev_priv->regs.psb; 771 struct psb_pipe *pipeb = &dev_priv->regs.pipe[1]; 772 int i; 773 774 /* dpll */ 775 hdmi_dev->saveDPLL_CTRL = PSB_RVDC32(DPLL_CTRL); 776 hdmi_dev->saveDPLL_DIV_CTRL = PSB_RVDC32(DPLL_DIV_CTRL); 777 hdmi_dev->saveDPLL_ADJUST = PSB_RVDC32(DPLL_ADJUST); 778 hdmi_dev->saveDPLL_UPDATE = PSB_RVDC32(DPLL_UPDATE); 779 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); 780 781 /* pipe B */ 782 pipeb->conf = PSB_RVDC32(PIPEBCONF); 783 pipeb->src = PSB_RVDC32(PIPEBSRC); 784 pipeb->htotal = PSB_RVDC32(HTOTAL_B); 785 pipeb->hblank = PSB_RVDC32(HBLANK_B); 786 pipeb->hsync = PSB_RVDC32(HSYNC_B); 787 pipeb->vtotal = PSB_RVDC32(VTOTAL_B); 788 pipeb->vblank = PSB_RVDC32(VBLANK_B); 789 pipeb->vsync = PSB_RVDC32(VSYNC_B); 790 791 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF); 792 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC); 793 hdmi_dev->savePCH_HTOTAL_B = PSB_RVDC32(PCH_HTOTAL_B); 794 hdmi_dev->savePCH_HBLANK_B = PSB_RVDC32(PCH_HBLANK_B); 795 hdmi_dev->savePCH_HSYNC_B = PSB_RVDC32(PCH_HSYNC_B); 796 hdmi_dev->savePCH_VTOTAL_B = PSB_RVDC32(PCH_VTOTAL_B); 797 hdmi_dev->savePCH_VBLANK_B = PSB_RVDC32(PCH_VBLANK_B); 798 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B); 799 800 /* plane */ 801 pipeb->cntr = PSB_RVDC32(DSPBCNTR); 802 pipeb->stride = PSB_RVDC32(DSPBSTRIDE); 803 pipeb->addr = PSB_RVDC32(DSPBBASE); 804 pipeb->surf = PSB_RVDC32(DSPBSURF); 805 pipeb->linoff = PSB_RVDC32(DSPBLINOFF); 806 pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF); 807 808 /* cursor B */ 809 regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR); 810 regs->saveDSPBCURSOR_BASE = PSB_RVDC32(CURBBASE); 811 regs->saveDSPBCURSOR_POS = PSB_RVDC32(CURBPOS); 812 813 /* save palette */ 814 for (i = 0; i < 256; i++) 815 pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2)); 816 } 817 818 /* restore HDMI register state */ 819 void oaktrail_hdmi_restore(struct drm_device *dev) 820 { 821 struct drm_psb_private *dev_priv = dev->dev_private; 822 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 823 struct psb_state *regs = &dev_priv->regs.psb; 824 struct psb_pipe *pipeb = &dev_priv->regs.pipe[1]; 825 int i; 826 827 /* dpll */ 828 PSB_WVDC32(hdmi_dev->saveDPLL_CTRL, DPLL_CTRL); 829 PSB_WVDC32(hdmi_dev->saveDPLL_DIV_CTRL, DPLL_DIV_CTRL); 830 PSB_WVDC32(hdmi_dev->saveDPLL_ADJUST, DPLL_ADJUST); 831 PSB_WVDC32(hdmi_dev->saveDPLL_UPDATE, DPLL_UPDATE); 832 PSB_WVDC32(hdmi_dev->saveDPLL_CLK_ENABLE, DPLL_CLK_ENABLE); 833 DRM_UDELAY(150); 834 835 /* pipe */ 836 PSB_WVDC32(pipeb->src, PIPEBSRC); 837 PSB_WVDC32(pipeb->htotal, HTOTAL_B); 838 PSB_WVDC32(pipeb->hblank, HBLANK_B); 839 PSB_WVDC32(pipeb->hsync, HSYNC_B); 840 PSB_WVDC32(pipeb->vtotal, VTOTAL_B); 841 PSB_WVDC32(pipeb->vblank, VBLANK_B); 842 PSB_WVDC32(pipeb->vsync, VSYNC_B); 843 844 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); 845 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); 846 PSB_WVDC32(hdmi_dev->savePCH_HBLANK_B, PCH_HBLANK_B); 847 PSB_WVDC32(hdmi_dev->savePCH_HSYNC_B, PCH_HSYNC_B); 848 PSB_WVDC32(hdmi_dev->savePCH_VTOTAL_B, PCH_VTOTAL_B); 849 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); 850 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); 851 852 PSB_WVDC32(pipeb->conf, PIPEBCONF); 853 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); 854 855 /* plane */ 856 PSB_WVDC32(pipeb->linoff, DSPBLINOFF); 857 PSB_WVDC32(pipeb->stride, DSPBSTRIDE); 858 PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF); 859 PSB_WVDC32(pipeb->cntr, DSPBCNTR); 860 PSB_WVDC32(pipeb->surf, DSPBSURF); 861 862 /* cursor B */ 863 PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR); 864 PSB_WVDC32(regs->saveDSPBCURSOR_POS, CURBPOS); 865 PSB_WVDC32(regs->saveDSPBCURSOR_BASE, CURBBASE); 866 867 /* restore palette */ 868 for (i = 0; i < 256; i++) 869 PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2)); 870 } 871