1 /************************************************************************** 2 * Copyright (c) 2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 #include <linux/backlight.h> 21 #include <linux/delay.h> 22 #include <linux/dmi.h> 23 #include <linux/module.h> 24 25 #include <asm/intel-mid.h> 26 #include <asm/intel_scu_ipc.h> 27 28 #include <drm/drm.h> 29 30 #include "intel_bios.h" 31 #include "mid_bios.h" 32 #include "psb_drv.h" 33 #include "psb_intel_reg.h" 34 #include "psb_reg.h" 35 36 static int oaktrail_output_init(struct drm_device *dev) 37 { 38 struct drm_psb_private *dev_priv = dev->dev_private; 39 if (dev_priv->iLVDS_enable) 40 oaktrail_lvds_init(dev, &dev_priv->mode_dev); 41 else 42 dev_err(dev->dev, "DSI is not supported\n"); 43 if (dev_priv->hdmi_priv) 44 oaktrail_hdmi_init(dev, &dev_priv->mode_dev); 45 46 psb_intel_sdvo_init(dev, SDVOB); 47 48 return 0; 49 } 50 51 /* 52 * Provide the low level interfaces for the Moorestown backlight 53 */ 54 55 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 56 57 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 58 #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */ 59 #define BLC_PWM_FREQ_CALC_CONSTANT 32 60 #define MHz 1000000 61 #define BLC_ADJUSTMENT_MAX 100 62 63 static struct backlight_device *oaktrail_backlight_device; 64 static int oaktrail_brightness; 65 66 static int oaktrail_set_brightness(struct backlight_device *bd) 67 { 68 struct drm_device *dev = bl_get_data(oaktrail_backlight_device); 69 struct drm_psb_private *dev_priv = dev->dev_private; 70 int level = bd->props.brightness; 71 u32 blc_pwm_ctl; 72 u32 max_pwm_blc; 73 74 /* Percentage 1-100% being valid */ 75 if (level < 1) 76 level = 1; 77 78 if (gma_power_begin(dev, 0)) { 79 /* Calculate and set the brightness value */ 80 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 81 blc_pwm_ctl = level * max_pwm_blc / 100; 82 83 /* Adjust the backlight level with the percent in 84 * dev_priv->blc_adj1; 85 */ 86 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; 87 blc_pwm_ctl = blc_pwm_ctl / 100; 88 89 /* Adjust the backlight level with the percent in 90 * dev_priv->blc_adj2; 91 */ 92 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; 93 blc_pwm_ctl = blc_pwm_ctl / 100; 94 95 /* force PWM bit on */ 96 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 97 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 98 gma_power_end(dev); 99 } 100 oaktrail_brightness = level; 101 return 0; 102 } 103 104 static int oaktrail_get_brightness(struct backlight_device *bd) 105 { 106 /* return locally cached var instead of HW read (due to DPST etc.) */ 107 /* FIXME: ideally return actual value in case firmware fiddled with 108 it */ 109 return oaktrail_brightness; 110 } 111 112 static int device_backlight_init(struct drm_device *dev) 113 { 114 struct drm_psb_private *dev_priv = dev->dev_private; 115 unsigned long core_clock; 116 u16 bl_max_freq; 117 uint32_t value; 118 uint32_t blc_pwm_precision_factor; 119 120 dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; 121 dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; 122 bl_max_freq = 256; 123 /* this needs to be set elsewhere */ 124 blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; 125 126 core_clock = dev_priv->core_freq; 127 128 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; 129 value *= blc_pwm_precision_factor; 130 value /= bl_max_freq; 131 value /= blc_pwm_precision_factor; 132 133 if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ) 134 return -ERANGE; 135 136 if (gma_power_begin(dev, false)) { 137 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 138 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 139 gma_power_end(dev); 140 } 141 return 0; 142 } 143 144 static const struct backlight_ops oaktrail_ops = { 145 .get_brightness = oaktrail_get_brightness, 146 .update_status = oaktrail_set_brightness, 147 }; 148 149 static int oaktrail_backlight_init(struct drm_device *dev) 150 { 151 struct drm_psb_private *dev_priv = dev->dev_private; 152 int ret; 153 struct backlight_properties props; 154 155 memset(&props, 0, sizeof(struct backlight_properties)); 156 props.max_brightness = 100; 157 props.type = BACKLIGHT_PLATFORM; 158 159 oaktrail_backlight_device = backlight_device_register("oaktrail-bl", 160 NULL, (void *)dev, &oaktrail_ops, &props); 161 162 if (IS_ERR(oaktrail_backlight_device)) 163 return PTR_ERR(oaktrail_backlight_device); 164 165 ret = device_backlight_init(dev); 166 if (ret < 0) { 167 backlight_device_unregister(oaktrail_backlight_device); 168 return ret; 169 } 170 oaktrail_backlight_device->props.brightness = 100; 171 oaktrail_backlight_device->props.max_brightness = 100; 172 backlight_update_status(oaktrail_backlight_device); 173 dev_priv->backlight_device = oaktrail_backlight_device; 174 return 0; 175 } 176 177 #endif 178 179 /* 180 * Provide the Moorestown specific chip logic and low level methods 181 * for power management 182 */ 183 184 /** 185 * oaktrail_save_display_registers - save registers lost on suspend 186 * @dev: our DRM device 187 * 188 * Save the state we need in order to be able to restore the interface 189 * upon resume from suspend 190 */ 191 static int oaktrail_save_display_registers(struct drm_device *dev) 192 { 193 struct drm_psb_private *dev_priv = dev->dev_private; 194 struct psb_save_area *regs = &dev_priv->regs; 195 struct psb_pipe *p = ®s->pipe[0]; 196 int i; 197 u32 pp_stat; 198 199 /* Display arbitration control + watermarks */ 200 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB); 201 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1); 202 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2); 203 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); 204 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4); 205 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5); 206 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6); 207 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 208 209 /* Pipe & plane A info */ 210 p->conf = PSB_RVDC32(PIPEACONF); 211 p->src = PSB_RVDC32(PIPEASRC); 212 p->fp0 = PSB_RVDC32(MRST_FPA0); 213 p->fp1 = PSB_RVDC32(MRST_FPA1); 214 p->dpll = PSB_RVDC32(MRST_DPLL_A); 215 p->htotal = PSB_RVDC32(HTOTAL_A); 216 p->hblank = PSB_RVDC32(HBLANK_A); 217 p->hsync = PSB_RVDC32(HSYNC_A); 218 p->vtotal = PSB_RVDC32(VTOTAL_A); 219 p->vblank = PSB_RVDC32(VBLANK_A); 220 p->vsync = PSB_RVDC32(VSYNC_A); 221 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 222 p->cntr = PSB_RVDC32(DSPACNTR); 223 p->stride = PSB_RVDC32(DSPASTRIDE); 224 p->addr = PSB_RVDC32(DSPABASE); 225 p->surf = PSB_RVDC32(DSPASURF); 226 p->linoff = PSB_RVDC32(DSPALINOFF); 227 p->tileoff = PSB_RVDC32(DSPATILEOFF); 228 229 /* Save cursor regs */ 230 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 231 regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 232 regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 233 234 /* Save palette (gamma) */ 235 for (i = 0; i < 256; i++) 236 p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 237 238 if (dev_priv->hdmi_priv) 239 oaktrail_hdmi_save(dev); 240 241 /* Save performance state */ 242 regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 243 244 /* LVDS state */ 245 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 246 regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 247 regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 248 regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 249 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 250 regs->psb.saveLVDS = PSB_RVDC32(LVDS); 251 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 252 regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 253 regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 254 regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 255 256 /* HW overlay */ 257 regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD); 258 regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 259 regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 260 regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 261 regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 262 regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 263 regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 264 265 /* DPST registers */ 266 regs->psb.saveHISTOGRAM_INT_CONTROL_REG = 267 PSB_RVDC32(HISTOGRAM_INT_CONTROL); 268 regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG = 269 PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 270 regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 271 272 if (dev_priv->iLVDS_enable) { 273 /* Shut down the panel */ 274 PSB_WVDC32(0, PP_CONTROL); 275 276 do { 277 pp_stat = PSB_RVDC32(PP_STATUS); 278 } while (pp_stat & 0x80000000); 279 280 /* Turn off the plane */ 281 PSB_WVDC32(0x58000000, DSPACNTR); 282 /* Trigger the plane disable */ 283 PSB_WVDC32(0, DSPASURF); 284 285 /* Wait ~4 ticks */ 286 msleep(4); 287 288 /* Turn off pipe */ 289 PSB_WVDC32(0x0, PIPEACONF); 290 /* Wait ~8 ticks */ 291 msleep(8); 292 293 /* Turn off PLLs */ 294 PSB_WVDC32(0, MRST_DPLL_A); 295 } 296 return 0; 297 } 298 299 /** 300 * oaktrail_restore_display_registers - restore lost register state 301 * @dev: our DRM device 302 * 303 * Restore register state that was lost during suspend and resume. 304 */ 305 static int oaktrail_restore_display_registers(struct drm_device *dev) 306 { 307 struct drm_psb_private *dev_priv = dev->dev_private; 308 struct psb_save_area *regs = &dev_priv->regs; 309 struct psb_pipe *p = ®s->pipe[0]; 310 u32 pp_stat; 311 int i; 312 313 /* Display arbitration + watermarks */ 314 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB); 315 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1); 316 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2); 317 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3); 318 PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4); 319 PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5); 320 PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6); 321 PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT); 322 323 /* Make sure VGA plane is off. it initializes to on after reset!*/ 324 PSB_WVDC32(0x80000000, VGACNTRL); 325 326 /* set the plls */ 327 PSB_WVDC32(p->fp0, MRST_FPA0); 328 PSB_WVDC32(p->fp1, MRST_FPA1); 329 330 /* Actually enable it */ 331 PSB_WVDC32(p->dpll, MRST_DPLL_A); 332 udelay(150); 333 334 /* Restore mode */ 335 PSB_WVDC32(p->htotal, HTOTAL_A); 336 PSB_WVDC32(p->hblank, HBLANK_A); 337 PSB_WVDC32(p->hsync, HSYNC_A); 338 PSB_WVDC32(p->vtotal, VTOTAL_A); 339 PSB_WVDC32(p->vblank, VBLANK_A); 340 PSB_WVDC32(p->vsync, VSYNC_A); 341 PSB_WVDC32(p->src, PIPEASRC); 342 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A); 343 344 /* Restore performance mode*/ 345 PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE); 346 347 /* Enable the pipe*/ 348 if (dev_priv->iLVDS_enable) 349 PSB_WVDC32(p->conf, PIPEACONF); 350 351 /* Set up the plane*/ 352 PSB_WVDC32(p->linoff, DSPALINOFF); 353 PSB_WVDC32(p->stride, DSPASTRIDE); 354 PSB_WVDC32(p->tileoff, DSPATILEOFF); 355 356 /* Enable the plane */ 357 PSB_WVDC32(p->cntr, DSPACNTR); 358 PSB_WVDC32(p->surf, DSPASURF); 359 360 /* Enable Cursor A */ 361 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR); 362 PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS); 363 PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE); 364 365 /* Restore palette (gamma) */ 366 for (i = 0; i < 256; i++) 367 PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2)); 368 369 if (dev_priv->hdmi_priv) 370 oaktrail_hdmi_restore(dev); 371 372 if (dev_priv->iLVDS_enable) { 373 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 374 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/ 375 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL); 376 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 377 PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 378 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); 379 PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON); 380 PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF); 381 PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE); 382 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); 383 } 384 385 /* Wait for cycle delay */ 386 do { 387 pp_stat = PSB_RVDC32(PP_STATUS); 388 } while (pp_stat & 0x08000000); 389 390 /* Wait for panel power up */ 391 do { 392 pp_stat = PSB_RVDC32(PP_STATUS); 393 } while (pp_stat & 0x10000000); 394 395 /* Restore HW overlay */ 396 PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD); 397 PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0); 398 PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1); 399 PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2); 400 PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3); 401 PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4); 402 PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5); 403 404 /* DPST registers */ 405 PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG, 406 HISTOGRAM_INT_CONTROL); 407 PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG, 408 HISTOGRAM_LOGIC_CONTROL); 409 PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 410 411 return 0; 412 } 413 414 /** 415 * oaktrail_power_down - power down the display island 416 * @dev: our DRM device 417 * 418 * Power down the display interface of our device 419 */ 420 static int oaktrail_power_down(struct drm_device *dev) 421 { 422 struct drm_psb_private *dev_priv = dev->dev_private; 423 u32 pwr_mask ; 424 u32 pwr_sts; 425 426 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 427 outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); 428 429 while (true) { 430 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 431 if ((pwr_sts & pwr_mask) == pwr_mask) 432 break; 433 else 434 udelay(10); 435 } 436 return 0; 437 } 438 439 /* 440 * oaktrail_power_up 441 * 442 * Restore power to the specified island(s) (powergating) 443 */ 444 static int oaktrail_power_up(struct drm_device *dev) 445 { 446 struct drm_psb_private *dev_priv = dev->dev_private; 447 u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 448 u32 pwr_sts, pwr_cnt; 449 450 pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); 451 pwr_cnt &= ~pwr_mask; 452 outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); 453 454 while (true) { 455 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 456 if ((pwr_sts & pwr_mask) == 0) 457 break; 458 else 459 udelay(10); 460 } 461 return 0; 462 } 463 464 /* Oaktrail */ 465 static const struct psb_offset oaktrail_regmap[2] = { 466 { 467 .fp0 = MRST_FPA0, 468 .fp1 = MRST_FPA1, 469 .cntr = DSPACNTR, 470 .conf = PIPEACONF, 471 .src = PIPEASRC, 472 .dpll = MRST_DPLL_A, 473 .htotal = HTOTAL_A, 474 .hblank = HBLANK_A, 475 .hsync = HSYNC_A, 476 .vtotal = VTOTAL_A, 477 .vblank = VBLANK_A, 478 .vsync = VSYNC_A, 479 .stride = DSPASTRIDE, 480 .size = DSPASIZE, 481 .pos = DSPAPOS, 482 .surf = DSPASURF, 483 .addr = MRST_DSPABASE, 484 .base = MRST_DSPABASE, 485 .status = PIPEASTAT, 486 .linoff = DSPALINOFF, 487 .tileoff = DSPATILEOFF, 488 .palette = PALETTE_A, 489 }, 490 { 491 .fp0 = FPB0, 492 .fp1 = FPB1, 493 .cntr = DSPBCNTR, 494 .conf = PIPEBCONF, 495 .src = PIPEBSRC, 496 .dpll = DPLL_B, 497 .htotal = HTOTAL_B, 498 .hblank = HBLANK_B, 499 .hsync = HSYNC_B, 500 .vtotal = VTOTAL_B, 501 .vblank = VBLANK_B, 502 .vsync = VSYNC_B, 503 .stride = DSPBSTRIDE, 504 .size = DSPBSIZE, 505 .pos = DSPBPOS, 506 .surf = DSPBSURF, 507 .addr = DSPBBASE, 508 .base = DSPBBASE, 509 .status = PIPEBSTAT, 510 .linoff = DSPBLINOFF, 511 .tileoff = DSPBTILEOFF, 512 .palette = PALETTE_B, 513 }, 514 }; 515 516 static int oaktrail_chip_setup(struct drm_device *dev) 517 { 518 struct drm_psb_private *dev_priv = dev->dev_private; 519 int ret; 520 521 if (pci_enable_msi(dev->pdev)) 522 dev_warn(dev->dev, "Enabling MSI failed!\n"); 523 524 dev_priv->regmap = oaktrail_regmap; 525 526 ret = mid_chip_setup(dev); 527 if (ret < 0) 528 return ret; 529 if (!dev_priv->has_gct) { 530 /* Now pull the BIOS data */ 531 psb_intel_opregion_init(dev); 532 psb_intel_init_bios(dev); 533 } 534 gma_intel_setup_gmbus(dev); 535 oaktrail_hdmi_setup(dev); 536 return 0; 537 } 538 539 static void oaktrail_teardown(struct drm_device *dev) 540 { 541 struct drm_psb_private *dev_priv = dev->dev_private; 542 543 gma_intel_teardown_gmbus(dev); 544 oaktrail_hdmi_teardown(dev); 545 if (!dev_priv->has_gct) 546 psb_intel_destroy_bios(dev); 547 } 548 549 const struct psb_ops oaktrail_chip_ops = { 550 .name = "Oaktrail", 551 .accel_2d = 1, 552 .pipes = 2, 553 .crtcs = 2, 554 .hdmi_mask = (1 << 1), 555 .lvds_mask = (1 << 0), 556 .sdvo_mask = (1 << 1), 557 .cursor_needs_phys = 0, 558 .sgx_offset = MRST_SGX_OFFSET, 559 560 .chip_setup = oaktrail_chip_setup, 561 .chip_teardown = oaktrail_teardown, 562 .crtc_helper = &oaktrail_helper_funcs, 563 .crtc_funcs = &psb_intel_crtc_funcs, 564 565 .output_init = oaktrail_output_init, 566 567 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 568 .backlight_init = oaktrail_backlight_init, 569 #endif 570 571 .save_regs = oaktrail_save_display_registers, 572 .restore_regs = oaktrail_restore_display_registers, 573 .save_crtc = gma_crtc_save, 574 .restore_crtc = gma_crtc_restore, 575 .power_down = oaktrail_power_down, 576 .power_up = oaktrail_power_up, 577 578 .i2c_bus = 1, 579 }; 580