1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 #include <linux/backlight.h> 9 #include <linux/module.h> 10 #include <linux/dmi.h> 11 #include <drm/drmP.h> 12 #include <drm/drm.h> 13 #include <drm/gma_drm.h> 14 #include "psb_drv.h" 15 #include "psb_reg.h" 16 #include "psb_intel_reg.h" 17 #include <asm/intel-mid.h> 18 #include <asm/intel_scu_ipc.h> 19 #include "mid_bios.h" 20 #include "intel_bios.h" 21 22 static int oaktrail_output_init(struct drm_device *dev) 23 { 24 struct drm_psb_private *dev_priv = dev->dev_private; 25 if (dev_priv->iLVDS_enable) 26 oaktrail_lvds_init(dev, &dev_priv->mode_dev); 27 else 28 dev_err(dev->dev, "DSI is not supported\n"); 29 if (dev_priv->hdmi_priv) 30 oaktrail_hdmi_init(dev, &dev_priv->mode_dev); 31 32 psb_intel_sdvo_init(dev, SDVOB); 33 34 return 0; 35 } 36 37 /* 38 * Provide the low level interfaces for the Moorestown backlight 39 */ 40 41 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 42 43 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 44 #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */ 45 #define BLC_PWM_FREQ_CALC_CONSTANT 32 46 #define MHz 1000000 47 #define BLC_ADJUSTMENT_MAX 100 48 49 static struct backlight_device *oaktrail_backlight_device; 50 static int oaktrail_brightness; 51 52 static int oaktrail_set_brightness(struct backlight_device *bd) 53 { 54 struct drm_device *dev = bl_get_data(oaktrail_backlight_device); 55 struct drm_psb_private *dev_priv = dev->dev_private; 56 int level = bd->props.brightness; 57 u32 blc_pwm_ctl; 58 u32 max_pwm_blc; 59 60 /* Percentage 1-100% being valid */ 61 if (level < 1) 62 level = 1; 63 64 if (gma_power_begin(dev, 0)) { 65 /* Calculate and set the brightness value */ 66 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 67 blc_pwm_ctl = level * max_pwm_blc / 100; 68 69 /* Adjust the backlight level with the percent in 70 * dev_priv->blc_adj1; 71 */ 72 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; 73 blc_pwm_ctl = blc_pwm_ctl / 100; 74 75 /* Adjust the backlight level with the percent in 76 * dev_priv->blc_adj2; 77 */ 78 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; 79 blc_pwm_ctl = blc_pwm_ctl / 100; 80 81 /* force PWM bit on */ 82 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 83 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 84 gma_power_end(dev); 85 } 86 oaktrail_brightness = level; 87 return 0; 88 } 89 90 static int oaktrail_get_brightness(struct backlight_device *bd) 91 { 92 /* return locally cached var instead of HW read (due to DPST etc.) */ 93 /* FIXME: ideally return actual value in case firmware fiddled with 94 it */ 95 return oaktrail_brightness; 96 } 97 98 static int device_backlight_init(struct drm_device *dev) 99 { 100 struct drm_psb_private *dev_priv = dev->dev_private; 101 unsigned long core_clock; 102 u16 bl_max_freq; 103 uint32_t value; 104 uint32_t blc_pwm_precision_factor; 105 106 dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; 107 dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; 108 bl_max_freq = 256; 109 /* this needs to be set elsewhere */ 110 blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; 111 112 core_clock = dev_priv->core_freq; 113 114 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; 115 value *= blc_pwm_precision_factor; 116 value /= bl_max_freq; 117 value /= blc_pwm_precision_factor; 118 119 if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ) 120 return -ERANGE; 121 122 if (gma_power_begin(dev, false)) { 123 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 124 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 125 gma_power_end(dev); 126 } 127 return 0; 128 } 129 130 static const struct backlight_ops oaktrail_ops = { 131 .get_brightness = oaktrail_get_brightness, 132 .update_status = oaktrail_set_brightness, 133 }; 134 135 static int oaktrail_backlight_init(struct drm_device *dev) 136 { 137 struct drm_psb_private *dev_priv = dev->dev_private; 138 int ret; 139 struct backlight_properties props; 140 141 memset(&props, 0, sizeof(struct backlight_properties)); 142 props.max_brightness = 100; 143 props.type = BACKLIGHT_PLATFORM; 144 145 oaktrail_backlight_device = backlight_device_register("oaktrail-bl", 146 NULL, (void *)dev, &oaktrail_ops, &props); 147 148 if (IS_ERR(oaktrail_backlight_device)) 149 return PTR_ERR(oaktrail_backlight_device); 150 151 ret = device_backlight_init(dev); 152 if (ret < 0) { 153 backlight_device_unregister(oaktrail_backlight_device); 154 return ret; 155 } 156 oaktrail_backlight_device->props.brightness = 100; 157 oaktrail_backlight_device->props.max_brightness = 100; 158 backlight_update_status(oaktrail_backlight_device); 159 dev_priv->backlight_device = oaktrail_backlight_device; 160 return 0; 161 } 162 163 #endif 164 165 /* 166 * Provide the Moorestown specific chip logic and low level methods 167 * for power management 168 */ 169 170 /** 171 * oaktrail_save_display_registers - save registers lost on suspend 172 * @dev: our DRM device 173 * 174 * Save the state we need in order to be able to restore the interface 175 * upon resume from suspend 176 */ 177 static int oaktrail_save_display_registers(struct drm_device *dev) 178 { 179 struct drm_psb_private *dev_priv = dev->dev_private; 180 struct psb_save_area *regs = &dev_priv->regs; 181 struct psb_pipe *p = ®s->pipe[0]; 182 int i; 183 u32 pp_stat; 184 185 /* Display arbitration control + watermarks */ 186 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB); 187 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1); 188 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2); 189 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); 190 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4); 191 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5); 192 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6); 193 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 194 195 /* Pipe & plane A info */ 196 p->conf = PSB_RVDC32(PIPEACONF); 197 p->src = PSB_RVDC32(PIPEASRC); 198 p->fp0 = PSB_RVDC32(MRST_FPA0); 199 p->fp1 = PSB_RVDC32(MRST_FPA1); 200 p->dpll = PSB_RVDC32(MRST_DPLL_A); 201 p->htotal = PSB_RVDC32(HTOTAL_A); 202 p->hblank = PSB_RVDC32(HBLANK_A); 203 p->hsync = PSB_RVDC32(HSYNC_A); 204 p->vtotal = PSB_RVDC32(VTOTAL_A); 205 p->vblank = PSB_RVDC32(VBLANK_A); 206 p->vsync = PSB_RVDC32(VSYNC_A); 207 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 208 p->cntr = PSB_RVDC32(DSPACNTR); 209 p->stride = PSB_RVDC32(DSPASTRIDE); 210 p->addr = PSB_RVDC32(DSPABASE); 211 p->surf = PSB_RVDC32(DSPASURF); 212 p->linoff = PSB_RVDC32(DSPALINOFF); 213 p->tileoff = PSB_RVDC32(DSPATILEOFF); 214 215 /* Save cursor regs */ 216 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 217 regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 218 regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 219 220 /* Save palette (gamma) */ 221 for (i = 0; i < 256; i++) 222 p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 223 224 if (dev_priv->hdmi_priv) 225 oaktrail_hdmi_save(dev); 226 227 /* Save performance state */ 228 regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 229 230 /* LVDS state */ 231 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 232 regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 233 regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 234 regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 235 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 236 regs->psb.saveLVDS = PSB_RVDC32(LVDS); 237 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 238 regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 239 regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 240 regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 241 242 /* HW overlay */ 243 regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD); 244 regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 245 regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 246 regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 247 regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 248 regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 249 regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 250 251 /* DPST registers */ 252 regs->psb.saveHISTOGRAM_INT_CONTROL_REG = 253 PSB_RVDC32(HISTOGRAM_INT_CONTROL); 254 regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG = 255 PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 256 regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 257 258 if (dev_priv->iLVDS_enable) { 259 /* Shut down the panel */ 260 PSB_WVDC32(0, PP_CONTROL); 261 262 do { 263 pp_stat = PSB_RVDC32(PP_STATUS); 264 } while (pp_stat & 0x80000000); 265 266 /* Turn off the plane */ 267 PSB_WVDC32(0x58000000, DSPACNTR); 268 /* Trigger the plane disable */ 269 PSB_WVDC32(0, DSPASURF); 270 271 /* Wait ~4 ticks */ 272 msleep(4); 273 274 /* Turn off pipe */ 275 PSB_WVDC32(0x0, PIPEACONF); 276 /* Wait ~8 ticks */ 277 msleep(8); 278 279 /* Turn off PLLs */ 280 PSB_WVDC32(0, MRST_DPLL_A); 281 } 282 return 0; 283 } 284 285 /** 286 * oaktrail_restore_display_registers - restore lost register state 287 * @dev: our DRM device 288 * 289 * Restore register state that was lost during suspend and resume. 290 */ 291 static int oaktrail_restore_display_registers(struct drm_device *dev) 292 { 293 struct drm_psb_private *dev_priv = dev->dev_private; 294 struct psb_save_area *regs = &dev_priv->regs; 295 struct psb_pipe *p = ®s->pipe[0]; 296 u32 pp_stat; 297 int i; 298 299 /* Display arbitration + watermarks */ 300 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB); 301 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1); 302 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2); 303 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3); 304 PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4); 305 PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5); 306 PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6); 307 PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT); 308 309 /* Make sure VGA plane is off. it initializes to on after reset!*/ 310 PSB_WVDC32(0x80000000, VGACNTRL); 311 312 /* set the plls */ 313 PSB_WVDC32(p->fp0, MRST_FPA0); 314 PSB_WVDC32(p->fp1, MRST_FPA1); 315 316 /* Actually enable it */ 317 PSB_WVDC32(p->dpll, MRST_DPLL_A); 318 DRM_UDELAY(150); 319 320 /* Restore mode */ 321 PSB_WVDC32(p->htotal, HTOTAL_A); 322 PSB_WVDC32(p->hblank, HBLANK_A); 323 PSB_WVDC32(p->hsync, HSYNC_A); 324 PSB_WVDC32(p->vtotal, VTOTAL_A); 325 PSB_WVDC32(p->vblank, VBLANK_A); 326 PSB_WVDC32(p->vsync, VSYNC_A); 327 PSB_WVDC32(p->src, PIPEASRC); 328 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A); 329 330 /* Restore performance mode*/ 331 PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE); 332 333 /* Enable the pipe*/ 334 if (dev_priv->iLVDS_enable) 335 PSB_WVDC32(p->conf, PIPEACONF); 336 337 /* Set up the plane*/ 338 PSB_WVDC32(p->linoff, DSPALINOFF); 339 PSB_WVDC32(p->stride, DSPASTRIDE); 340 PSB_WVDC32(p->tileoff, DSPATILEOFF); 341 342 /* Enable the plane */ 343 PSB_WVDC32(p->cntr, DSPACNTR); 344 PSB_WVDC32(p->surf, DSPASURF); 345 346 /* Enable Cursor A */ 347 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR); 348 PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS); 349 PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE); 350 351 /* Restore palette (gamma) */ 352 for (i = 0; i < 256; i++) 353 PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2)); 354 355 if (dev_priv->hdmi_priv) 356 oaktrail_hdmi_restore(dev); 357 358 if (dev_priv->iLVDS_enable) { 359 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 360 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/ 361 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL); 362 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 363 PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 364 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); 365 PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON); 366 PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF); 367 PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE); 368 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); 369 } 370 371 /* Wait for cycle delay */ 372 do { 373 pp_stat = PSB_RVDC32(PP_STATUS); 374 } while (pp_stat & 0x08000000); 375 376 /* Wait for panel power up */ 377 do { 378 pp_stat = PSB_RVDC32(PP_STATUS); 379 } while (pp_stat & 0x10000000); 380 381 /* Restore HW overlay */ 382 PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD); 383 PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0); 384 PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1); 385 PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2); 386 PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3); 387 PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4); 388 PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5); 389 390 /* DPST registers */ 391 PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG, 392 HISTOGRAM_INT_CONTROL); 393 PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG, 394 HISTOGRAM_LOGIC_CONTROL); 395 PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 396 397 return 0; 398 } 399 400 /** 401 * oaktrail_power_down - power down the display island 402 * @dev: our DRM device 403 * 404 * Power down the display interface of our device 405 */ 406 static int oaktrail_power_down(struct drm_device *dev) 407 { 408 struct drm_psb_private *dev_priv = dev->dev_private; 409 u32 pwr_mask ; 410 u32 pwr_sts; 411 412 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 413 outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); 414 415 while (true) { 416 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 417 if ((pwr_sts & pwr_mask) == pwr_mask) 418 break; 419 else 420 udelay(10); 421 } 422 return 0; 423 } 424 425 /* 426 * oaktrail_power_up 427 * 428 * Restore power to the specified island(s) (powergating) 429 */ 430 static int oaktrail_power_up(struct drm_device *dev) 431 { 432 struct drm_psb_private *dev_priv = dev->dev_private; 433 u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 434 u32 pwr_sts, pwr_cnt; 435 436 pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); 437 pwr_cnt &= ~pwr_mask; 438 outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); 439 440 while (true) { 441 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 442 if ((pwr_sts & pwr_mask) == 0) 443 break; 444 else 445 udelay(10); 446 } 447 return 0; 448 } 449 450 /* Oaktrail */ 451 static const struct psb_offset oaktrail_regmap[2] = { 452 { 453 .fp0 = MRST_FPA0, 454 .fp1 = MRST_FPA1, 455 .cntr = DSPACNTR, 456 .conf = PIPEACONF, 457 .src = PIPEASRC, 458 .dpll = MRST_DPLL_A, 459 .htotal = HTOTAL_A, 460 .hblank = HBLANK_A, 461 .hsync = HSYNC_A, 462 .vtotal = VTOTAL_A, 463 .vblank = VBLANK_A, 464 .vsync = VSYNC_A, 465 .stride = DSPASTRIDE, 466 .size = DSPASIZE, 467 .pos = DSPAPOS, 468 .surf = DSPASURF, 469 .addr = MRST_DSPABASE, 470 .base = MRST_DSPABASE, 471 .status = PIPEASTAT, 472 .linoff = DSPALINOFF, 473 .tileoff = DSPATILEOFF, 474 .palette = PALETTE_A, 475 }, 476 { 477 .fp0 = FPB0, 478 .fp1 = FPB1, 479 .cntr = DSPBCNTR, 480 .conf = PIPEBCONF, 481 .src = PIPEBSRC, 482 .dpll = DPLL_B, 483 .htotal = HTOTAL_B, 484 .hblank = HBLANK_B, 485 .hsync = HSYNC_B, 486 .vtotal = VTOTAL_B, 487 .vblank = VBLANK_B, 488 .vsync = VSYNC_B, 489 .stride = DSPBSTRIDE, 490 .size = DSPBSIZE, 491 .pos = DSPBPOS, 492 .surf = DSPBSURF, 493 .addr = DSPBBASE, 494 .base = DSPBBASE, 495 .status = PIPEBSTAT, 496 .linoff = DSPBLINOFF, 497 .tileoff = DSPBTILEOFF, 498 .palette = PALETTE_B, 499 }, 500 }; 501 502 static int oaktrail_chip_setup(struct drm_device *dev) 503 { 504 struct drm_psb_private *dev_priv = dev->dev_private; 505 int ret; 506 507 if (pci_enable_msi(dev->pdev)) 508 dev_warn(dev->dev, "Enabling MSI failed!\n"); 509 510 dev_priv->regmap = oaktrail_regmap; 511 512 ret = mid_chip_setup(dev); 513 if (ret < 0) 514 return ret; 515 if (!dev_priv->has_gct) { 516 /* Now pull the BIOS data */ 517 psb_intel_opregion_init(dev); 518 psb_intel_init_bios(dev); 519 } 520 gma_intel_setup_gmbus(dev); 521 oaktrail_hdmi_setup(dev); 522 return 0; 523 } 524 525 static void oaktrail_teardown(struct drm_device *dev) 526 { 527 struct drm_psb_private *dev_priv = dev->dev_private; 528 529 gma_intel_teardown_gmbus(dev); 530 oaktrail_hdmi_teardown(dev); 531 if (!dev_priv->has_gct) 532 psb_intel_destroy_bios(dev); 533 } 534 535 const struct psb_ops oaktrail_chip_ops = { 536 .name = "Oaktrail", 537 .accel_2d = 1, 538 .pipes = 2, 539 .crtcs = 2, 540 .hdmi_mask = (1 << 1), 541 .lvds_mask = (1 << 0), 542 .sdvo_mask = (1 << 1), 543 .cursor_needs_phys = 0, 544 .sgx_offset = MRST_SGX_OFFSET, 545 546 .chip_setup = oaktrail_chip_setup, 547 .chip_teardown = oaktrail_teardown, 548 .crtc_helper = &oaktrail_helper_funcs, 549 .crtc_funcs = &psb_intel_crtc_funcs, 550 551 .output_init = oaktrail_output_init, 552 553 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 554 .backlight_init = oaktrail_backlight_init, 555 #endif 556 557 .save_regs = oaktrail_save_display_registers, 558 .restore_regs = oaktrail_restore_display_registers, 559 .save_crtc = gma_crtc_save, 560 .restore_crtc = gma_crtc_restore, 561 .power_down = oaktrail_power_down, 562 .power_up = oaktrail_power_up, 563 564 .i2c_bus = 1, 565 }; 566