1 /************************************************************************** 2 * Copyright (c) 2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 #include <linux/backlight.h> 21 #include <linux/module.h> 22 #include <linux/dmi.h> 23 #include <drm/drmP.h> 24 #include <drm/drm.h> 25 #include "psb_drm.h" 26 #include "psb_drv.h" 27 #include "psb_reg.h" 28 #include "psb_intel_reg.h" 29 #include <asm/mrst.h> 30 #include <asm/intel_scu_ipc.h> 31 #include "mid_bios.h" 32 33 static int oaktrail_output_init(struct drm_device *dev) 34 { 35 struct drm_psb_private *dev_priv = dev->dev_private; 36 if (dev_priv->iLVDS_enable) 37 oaktrail_lvds_init(dev, &dev_priv->mode_dev); 38 else 39 dev_err(dev->dev, "DSI is not supported\n"); 40 if (dev_priv->hdmi_priv) 41 oaktrail_hdmi_init(dev, &dev_priv->mode_dev); 42 return 0; 43 } 44 45 /* 46 * Provide the low level interfaces for the Moorestown backlight 47 */ 48 49 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 50 51 #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 52 #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */ 53 #define BLC_PWM_FREQ_CALC_CONSTANT 32 54 #define MHz 1000000 55 #define BLC_ADJUSTMENT_MAX 100 56 57 static struct backlight_device *oaktrail_backlight_device; 58 static int oaktrail_brightness; 59 60 static int oaktrail_set_brightness(struct backlight_device *bd) 61 { 62 struct drm_device *dev = bl_get_data(oaktrail_backlight_device); 63 struct drm_psb_private *dev_priv = dev->dev_private; 64 int level = bd->props.brightness; 65 u32 blc_pwm_ctl; 66 u32 max_pwm_blc; 67 68 /* Percentage 1-100% being valid */ 69 if (level < 1) 70 level = 1; 71 72 if (gma_power_begin(dev, 0)) { 73 /* Calculate and set the brightness value */ 74 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 75 blc_pwm_ctl = level * max_pwm_blc / 100; 76 77 /* Adjust the backlight level with the percent in 78 * dev_priv->blc_adj1; 79 */ 80 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; 81 blc_pwm_ctl = blc_pwm_ctl / 100; 82 83 /* Adjust the backlight level with the percent in 84 * dev_priv->blc_adj2; 85 */ 86 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; 87 blc_pwm_ctl = blc_pwm_ctl / 100; 88 89 /* force PWM bit on */ 90 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 91 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 92 gma_power_end(dev); 93 } 94 oaktrail_brightness = level; 95 return 0; 96 } 97 98 static int oaktrail_get_brightness(struct backlight_device *bd) 99 { 100 /* return locally cached var instead of HW read (due to DPST etc.) */ 101 /* FIXME: ideally return actual value in case firmware fiddled with 102 it */ 103 return oaktrail_brightness; 104 } 105 106 static int device_backlight_init(struct drm_device *dev) 107 { 108 struct drm_psb_private *dev_priv = dev->dev_private; 109 unsigned long core_clock; 110 u16 bl_max_freq; 111 uint32_t value; 112 uint32_t blc_pwm_precision_factor; 113 114 dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; 115 dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; 116 bl_max_freq = 256; 117 /* this needs to be set elsewhere */ 118 blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; 119 120 core_clock = dev_priv->core_freq; 121 122 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; 123 value *= blc_pwm_precision_factor; 124 value /= bl_max_freq; 125 value /= blc_pwm_precision_factor; 126 127 if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ) 128 return -ERANGE; 129 130 if (gma_power_begin(dev, false)) { 131 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 132 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 133 gma_power_end(dev); 134 } 135 return 0; 136 } 137 138 static const struct backlight_ops oaktrail_ops = { 139 .get_brightness = oaktrail_get_brightness, 140 .update_status = oaktrail_set_brightness, 141 }; 142 143 int oaktrail_backlight_init(struct drm_device *dev) 144 { 145 struct drm_psb_private *dev_priv = dev->dev_private; 146 int ret; 147 struct backlight_properties props; 148 149 memset(&props, 0, sizeof(struct backlight_properties)); 150 props.max_brightness = 100; 151 props.type = BACKLIGHT_PLATFORM; 152 153 oaktrail_backlight_device = backlight_device_register("oaktrail-bl", 154 NULL, (void *)dev, &oaktrail_ops, &props); 155 156 if (IS_ERR(oaktrail_backlight_device)) 157 return PTR_ERR(oaktrail_backlight_device); 158 159 ret = device_backlight_init(dev); 160 if (ret < 0) { 161 backlight_device_unregister(oaktrail_backlight_device); 162 return ret; 163 } 164 oaktrail_backlight_device->props.brightness = 100; 165 oaktrail_backlight_device->props.max_brightness = 100; 166 backlight_update_status(oaktrail_backlight_device); 167 dev_priv->backlight_device = oaktrail_backlight_device; 168 return 0; 169 } 170 171 #endif 172 173 /* 174 * Provide the Moorestown specific chip logic and low level methods 175 * for power management 176 */ 177 178 static void oaktrail_init_pm(struct drm_device *dev) 179 { 180 } 181 182 /** 183 * oaktrail_save_display_registers - save registers lost on suspend 184 * @dev: our DRM device 185 * 186 * Save the state we need in order to be able to restore the interface 187 * upon resume from suspend 188 */ 189 static int oaktrail_save_display_registers(struct drm_device *dev) 190 { 191 struct drm_psb_private *dev_priv = dev->dev_private; 192 int i; 193 u32 pp_stat; 194 195 /* Display arbitration control + watermarks */ 196 dev_priv->saveDSPARB = PSB_RVDC32(DSPARB); 197 dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1); 198 dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2); 199 dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3); 200 dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4); 201 dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5); 202 dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6); 203 dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 204 205 /* Pipe & plane A info */ 206 dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF); 207 dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC); 208 dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0); 209 dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1); 210 dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A); 211 dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A); 212 dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A); 213 dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A); 214 dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A); 215 dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A); 216 dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A); 217 dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 218 dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR); 219 dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE); 220 dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE); 221 dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF); 222 dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF); 223 dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF); 224 225 /* Save cursor regs */ 226 dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 227 dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 228 dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 229 230 /* Save palette (gamma) */ 231 for (i = 0; i < 256; i++) 232 dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 233 234 if (dev_priv->hdmi_priv) 235 oaktrail_hdmi_save(dev); 236 237 /* Save performance state */ 238 dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 239 240 /* LVDS state */ 241 dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 242 dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 243 dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 244 dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 245 dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 246 dev_priv->saveLVDS = PSB_RVDC32(LVDS); 247 dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 248 dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 249 dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 250 dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 251 252 /* HW overlay */ 253 dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD); 254 dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 255 dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 256 dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 257 dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 258 dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 259 dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 260 261 /* DPST registers */ 262 dev_priv->saveHISTOGRAM_INT_CONTROL_REG = 263 PSB_RVDC32(HISTOGRAM_INT_CONTROL); 264 dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG = 265 PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 266 dev_priv->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 267 268 if (dev_priv->iLVDS_enable) { 269 /* Shut down the panel */ 270 PSB_WVDC32(0, PP_CONTROL); 271 272 do { 273 pp_stat = PSB_RVDC32(PP_STATUS); 274 } while (pp_stat & 0x80000000); 275 276 /* Turn off the plane */ 277 PSB_WVDC32(0x58000000, DSPACNTR); 278 /* Trigger the plane disable */ 279 PSB_WVDC32(0, DSPASURF); 280 281 /* Wait ~4 ticks */ 282 msleep(4); 283 284 /* Turn off pipe */ 285 PSB_WVDC32(0x0, PIPEACONF); 286 /* Wait ~8 ticks */ 287 msleep(8); 288 289 /* Turn off PLLs */ 290 PSB_WVDC32(0, MRST_DPLL_A); 291 } 292 return 0; 293 } 294 295 /** 296 * oaktrail_restore_display_registers - restore lost register state 297 * @dev: our DRM device 298 * 299 * Restore register state that was lost during suspend and resume. 300 */ 301 static int oaktrail_restore_display_registers(struct drm_device *dev) 302 { 303 struct drm_psb_private *dev_priv = dev->dev_private; 304 u32 pp_stat; 305 int i; 306 307 /* Display arbitration + watermarks */ 308 PSB_WVDC32(dev_priv->saveDSPARB, DSPARB); 309 PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1); 310 PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2); 311 PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3); 312 PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4); 313 PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5); 314 PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6); 315 PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT); 316 317 /* Make sure VGA plane is off. it initializes to on after reset!*/ 318 PSB_WVDC32(0x80000000, VGACNTRL); 319 320 /* set the plls */ 321 PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0); 322 PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1); 323 324 /* Actually enable it */ 325 PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A); 326 DRM_UDELAY(150); 327 328 /* Restore mode */ 329 PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A); 330 PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A); 331 PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A); 332 PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A); 333 PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A); 334 PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A); 335 PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC); 336 PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A); 337 338 /* Restore performance mode*/ 339 PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE); 340 341 /* Enable the pipe*/ 342 if (dev_priv->iLVDS_enable) 343 PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF); 344 345 /* Set up the plane*/ 346 PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF); 347 PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE); 348 PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF); 349 350 /* Enable the plane */ 351 PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR); 352 PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF); 353 354 /* Enable Cursor A */ 355 PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR); 356 PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS); 357 PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE); 358 359 /* Restore palette (gamma) */ 360 for (i = 0; i < 256; i++) 361 PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i << 2)); 362 363 if (dev_priv->hdmi_priv) 364 oaktrail_hdmi_restore(dev); 365 366 if (dev_priv->iLVDS_enable) { 367 PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 368 PSB_WVDC32(dev_priv->saveLVDS, LVDS); /*port 61180h*/ 369 PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL); 370 PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 371 PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 372 PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL); 373 PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON); 374 PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF); 375 PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE); 376 PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL); 377 } 378 379 /* Wait for cycle delay */ 380 do { 381 pp_stat = PSB_RVDC32(PP_STATUS); 382 } while (pp_stat & 0x08000000); 383 384 /* Wait for panel power up */ 385 do { 386 pp_stat = PSB_RVDC32(PP_STATUS); 387 } while (pp_stat & 0x10000000); 388 389 /* Restore HW overlay */ 390 PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD); 391 PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0); 392 PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1); 393 PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2); 394 PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3); 395 PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4); 396 PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5); 397 398 /* DPST registers */ 399 PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG, 400 HISTOGRAM_INT_CONTROL); 401 PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG, 402 HISTOGRAM_LOGIC_CONTROL); 403 PSB_WVDC32(dev_priv->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 404 405 return 0; 406 } 407 408 /** 409 * oaktrail_power_down - power down the display island 410 * @dev: our DRM device 411 * 412 * Power down the display interface of our device 413 */ 414 static int oaktrail_power_down(struct drm_device *dev) 415 { 416 struct drm_psb_private *dev_priv = dev->dev_private; 417 u32 pwr_mask ; 418 u32 pwr_sts; 419 420 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 421 outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); 422 423 while (true) { 424 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 425 if ((pwr_sts & pwr_mask) == pwr_mask) 426 break; 427 else 428 udelay(10); 429 } 430 return 0; 431 } 432 433 /* 434 * oaktrail_power_up 435 * 436 * Restore power to the specified island(s) (powergating) 437 */ 438 static int oaktrail_power_up(struct drm_device *dev) 439 { 440 struct drm_psb_private *dev_priv = dev->dev_private; 441 u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 442 u32 pwr_sts, pwr_cnt; 443 444 pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); 445 pwr_cnt &= ~pwr_mask; 446 outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); 447 448 while (true) { 449 pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 450 if ((pwr_sts & pwr_mask) == 0) 451 break; 452 else 453 udelay(10); 454 } 455 return 0; 456 } 457 458 459 static void oaktrail_teardown(struct drm_device *dev) 460 { 461 oaktrail_hdmi_teardown(dev); 462 } 463 464 const struct psb_ops oaktrail_chip_ops = { 465 .name = "Oaktrail", 466 .accel_2d = 1, 467 .pipes = 2, 468 .crtcs = 2, 469 .sgx_offset = MRST_SGX_OFFSET, 470 471 .chip_setup = mid_chip_setup, 472 .chip_teardown = oaktrail_teardown, 473 .crtc_helper = &oaktrail_helper_funcs, 474 .crtc_funcs = &psb_intel_crtc_funcs, 475 476 .output_init = oaktrail_output_init, 477 478 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 479 .backlight_init = oaktrail_backlight_init, 480 #endif 481 482 .init_pm = oaktrail_init_pm, 483 .save_regs = oaktrail_save_display_registers, 484 .restore_regs = oaktrail_restore_display_registers, 485 .power_down = oaktrail_power_down, 486 .power_up = oaktrail_power_up, 487 488 .i2c_bus = 1, 489 }; 490