11b082ccfSAlan Cox /************************************************************************** 21b082ccfSAlan Cox * Copyright (c) 2011, Intel Corporation. 31b082ccfSAlan Cox * All Rights Reserved. 41b082ccfSAlan Cox * 51b082ccfSAlan Cox * This program is free software; you can redistribute it and/or modify it 61b082ccfSAlan Cox * under the terms and conditions of the GNU General Public License, 71b082ccfSAlan Cox * version 2, as published by the Free Software Foundation. 81b082ccfSAlan Cox * 91b082ccfSAlan Cox * This program is distributed in the hope it will be useful, but WITHOUT 101b082ccfSAlan Cox * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 111b082ccfSAlan Cox * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 121b082ccfSAlan Cox * more details. 131b082ccfSAlan Cox * 141b082ccfSAlan Cox * You should have received a copy of the GNU General Public License along with 151b082ccfSAlan Cox * this program; if not, write to the Free Software Foundation, Inc., 161b082ccfSAlan Cox * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 171b082ccfSAlan Cox * 181b082ccfSAlan Cox **************************************************************************/ 191b082ccfSAlan Cox 201b082ccfSAlan Cox #include <linux/backlight.h> 211b082ccfSAlan Cox #include <linux/module.h> 221b082ccfSAlan Cox #include <linux/dmi.h> 231b082ccfSAlan Cox #include <drm/drmP.h> 241b082ccfSAlan Cox #include <drm/drm.h> 25760285e7SDavid Howells #include <drm/gma_drm.h> 261b082ccfSAlan Cox #include "psb_drv.h" 271b082ccfSAlan Cox #include "psb_reg.h" 281b082ccfSAlan Cox #include "psb_intel_reg.h" 291b082ccfSAlan Cox #include <asm/mrst.h> 301b082ccfSAlan Cox #include <asm/intel_scu_ipc.h> 311b082ccfSAlan Cox #include "mid_bios.h" 32aa0c45fdSAlan Cox #include "intel_bios.h" 331b082ccfSAlan Cox 341b082ccfSAlan Cox static int oaktrail_output_init(struct drm_device *dev) 351b082ccfSAlan Cox { 361b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 371b082ccfSAlan Cox if (dev_priv->iLVDS_enable) 381b082ccfSAlan Cox oaktrail_lvds_init(dev, &dev_priv->mode_dev); 391b082ccfSAlan Cox else 401b082ccfSAlan Cox dev_err(dev->dev, "DSI is not supported\n"); 411b082ccfSAlan Cox if (dev_priv->hdmi_priv) 421b082ccfSAlan Cox oaktrail_hdmi_init(dev, &dev_priv->mode_dev); 43cd3fdbe8SPatrik Jakobsson 44cd3fdbe8SPatrik Jakobsson psb_intel_sdvo_init(dev, SDVOB); 45cd3fdbe8SPatrik Jakobsson 461b082ccfSAlan Cox return 0; 471b082ccfSAlan Cox } 481b082ccfSAlan Cox 491b082ccfSAlan Cox /* 501b082ccfSAlan Cox * Provide the low level interfaces for the Moorestown backlight 511b082ccfSAlan Cox */ 521b082ccfSAlan Cox 531b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 541b082ccfSAlan Cox 551b082ccfSAlan Cox #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 561b082ccfSAlan Cox #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */ 571b082ccfSAlan Cox #define BLC_PWM_FREQ_CALC_CONSTANT 32 581b082ccfSAlan Cox #define MHz 1000000 591b082ccfSAlan Cox #define BLC_ADJUSTMENT_MAX 100 601b082ccfSAlan Cox 611b082ccfSAlan Cox static struct backlight_device *oaktrail_backlight_device; 621b082ccfSAlan Cox static int oaktrail_brightness; 631b082ccfSAlan Cox 641b082ccfSAlan Cox static int oaktrail_set_brightness(struct backlight_device *bd) 651b082ccfSAlan Cox { 661b082ccfSAlan Cox struct drm_device *dev = bl_get_data(oaktrail_backlight_device); 671b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 681b082ccfSAlan Cox int level = bd->props.brightness; 691b082ccfSAlan Cox u32 blc_pwm_ctl; 701b082ccfSAlan Cox u32 max_pwm_blc; 711b082ccfSAlan Cox 721b082ccfSAlan Cox /* Percentage 1-100% being valid */ 731b082ccfSAlan Cox if (level < 1) 741b082ccfSAlan Cox level = 1; 751b082ccfSAlan Cox 761b082ccfSAlan Cox if (gma_power_begin(dev, 0)) { 771b082ccfSAlan Cox /* Calculate and set the brightness value */ 781b082ccfSAlan Cox max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 791b082ccfSAlan Cox blc_pwm_ctl = level * max_pwm_blc / 100; 801b082ccfSAlan Cox 811b082ccfSAlan Cox /* Adjust the backlight level with the percent in 821b082ccfSAlan Cox * dev_priv->blc_adj1; 831b082ccfSAlan Cox */ 841b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; 851b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100; 861b082ccfSAlan Cox 871b082ccfSAlan Cox /* Adjust the backlight level with the percent in 881b082ccfSAlan Cox * dev_priv->blc_adj2; 891b082ccfSAlan Cox */ 901b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; 911b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100; 921b082ccfSAlan Cox 931b082ccfSAlan Cox /* force PWM bit on */ 941b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 951b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 961b082ccfSAlan Cox gma_power_end(dev); 971b082ccfSAlan Cox } 981b082ccfSAlan Cox oaktrail_brightness = level; 991b082ccfSAlan Cox return 0; 1001b082ccfSAlan Cox } 1011b082ccfSAlan Cox 1021b082ccfSAlan Cox static int oaktrail_get_brightness(struct backlight_device *bd) 1031b082ccfSAlan Cox { 1041b082ccfSAlan Cox /* return locally cached var instead of HW read (due to DPST etc.) */ 1051b082ccfSAlan Cox /* FIXME: ideally return actual value in case firmware fiddled with 1061b082ccfSAlan Cox it */ 1071b082ccfSAlan Cox return oaktrail_brightness; 1081b082ccfSAlan Cox } 1091b082ccfSAlan Cox 1101b082ccfSAlan Cox static int device_backlight_init(struct drm_device *dev) 1111b082ccfSAlan Cox { 1121b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1131b082ccfSAlan Cox unsigned long core_clock; 1141b082ccfSAlan Cox u16 bl_max_freq; 1151b082ccfSAlan Cox uint32_t value; 1161b082ccfSAlan Cox uint32_t blc_pwm_precision_factor; 1171b082ccfSAlan Cox 1181b082ccfSAlan Cox dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; 1191b082ccfSAlan Cox dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; 1201b082ccfSAlan Cox bl_max_freq = 256; 1211b082ccfSAlan Cox /* this needs to be set elsewhere */ 1221b082ccfSAlan Cox blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; 1231b082ccfSAlan Cox 1241b082ccfSAlan Cox core_clock = dev_priv->core_freq; 1251b082ccfSAlan Cox 1261b082ccfSAlan Cox value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; 1271b082ccfSAlan Cox value *= blc_pwm_precision_factor; 1281b082ccfSAlan Cox value /= bl_max_freq; 1291b082ccfSAlan Cox value /= blc_pwm_precision_factor; 1301b082ccfSAlan Cox 1311b082ccfSAlan Cox if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ) 1321b082ccfSAlan Cox return -ERANGE; 1331b082ccfSAlan Cox 1341b082ccfSAlan Cox if (gma_power_begin(dev, false)) { 1351b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 1361b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 1371b082ccfSAlan Cox gma_power_end(dev); 1381b082ccfSAlan Cox } 1391b082ccfSAlan Cox return 0; 1401b082ccfSAlan Cox } 1411b082ccfSAlan Cox 1421b082ccfSAlan Cox static const struct backlight_ops oaktrail_ops = { 1431b082ccfSAlan Cox .get_brightness = oaktrail_get_brightness, 1441b082ccfSAlan Cox .update_status = oaktrail_set_brightness, 1451b082ccfSAlan Cox }; 1461b082ccfSAlan Cox 147771f64d0SKirill A. Shutemov static int oaktrail_backlight_init(struct drm_device *dev) 1481b082ccfSAlan Cox { 1491b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1501b082ccfSAlan Cox int ret; 1511b082ccfSAlan Cox struct backlight_properties props; 1521b082ccfSAlan Cox 1531b082ccfSAlan Cox memset(&props, 0, sizeof(struct backlight_properties)); 1541b082ccfSAlan Cox props.max_brightness = 100; 1551b082ccfSAlan Cox props.type = BACKLIGHT_PLATFORM; 1561b082ccfSAlan Cox 1571b082ccfSAlan Cox oaktrail_backlight_device = backlight_device_register("oaktrail-bl", 1581b082ccfSAlan Cox NULL, (void *)dev, &oaktrail_ops, &props); 1591b082ccfSAlan Cox 1601b082ccfSAlan Cox if (IS_ERR(oaktrail_backlight_device)) 1611b082ccfSAlan Cox return PTR_ERR(oaktrail_backlight_device); 1621b082ccfSAlan Cox 1631b082ccfSAlan Cox ret = device_backlight_init(dev); 1641b082ccfSAlan Cox if (ret < 0) { 1651b082ccfSAlan Cox backlight_device_unregister(oaktrail_backlight_device); 1661b082ccfSAlan Cox return ret; 1671b082ccfSAlan Cox } 1681b082ccfSAlan Cox oaktrail_backlight_device->props.brightness = 100; 1691b082ccfSAlan Cox oaktrail_backlight_device->props.max_brightness = 100; 1701b082ccfSAlan Cox backlight_update_status(oaktrail_backlight_device); 1711b082ccfSAlan Cox dev_priv->backlight_device = oaktrail_backlight_device; 1721b082ccfSAlan Cox return 0; 1731b082ccfSAlan Cox } 1741b082ccfSAlan Cox 1751b082ccfSAlan Cox #endif 1761b082ccfSAlan Cox 1771b082ccfSAlan Cox /* 1781b082ccfSAlan Cox * Provide the Moorestown specific chip logic and low level methods 1791b082ccfSAlan Cox * for power management 1801b082ccfSAlan Cox */ 1811b082ccfSAlan Cox 1821b082ccfSAlan Cox /** 1831b082ccfSAlan Cox * oaktrail_save_display_registers - save registers lost on suspend 1841b082ccfSAlan Cox * @dev: our DRM device 1851b082ccfSAlan Cox * 1861b082ccfSAlan Cox * Save the state we need in order to be able to restore the interface 1871b082ccfSAlan Cox * upon resume from suspend 1881b082ccfSAlan Cox */ 1891b082ccfSAlan Cox static int oaktrail_save_display_registers(struct drm_device *dev) 1901b082ccfSAlan Cox { 1911b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 192c6265ff5SAlan Cox struct psb_save_area *regs = &dev_priv->regs; 1936256304bSAlan Cox struct psb_pipe *p = ®s->pipe[0]; 1941b082ccfSAlan Cox int i; 1951b082ccfSAlan Cox u32 pp_stat; 1961b082ccfSAlan Cox 1971b082ccfSAlan Cox /* Display arbitration control + watermarks */ 198c6265ff5SAlan Cox regs->psb.saveDSPARB = PSB_RVDC32(DSPARB); 199c6265ff5SAlan Cox regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1); 200c6265ff5SAlan Cox regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2); 201c6265ff5SAlan Cox regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3); 202c6265ff5SAlan Cox regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4); 203c6265ff5SAlan Cox regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5); 204c6265ff5SAlan Cox regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6); 205c6265ff5SAlan Cox regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 2061b082ccfSAlan Cox 2071b082ccfSAlan Cox /* Pipe & plane A info */ 2086256304bSAlan Cox p->conf = PSB_RVDC32(PIPEACONF); 2096256304bSAlan Cox p->src = PSB_RVDC32(PIPEASRC); 2106256304bSAlan Cox p->fp0 = PSB_RVDC32(MRST_FPA0); 2116256304bSAlan Cox p->fp1 = PSB_RVDC32(MRST_FPA1); 2126256304bSAlan Cox p->dpll = PSB_RVDC32(MRST_DPLL_A); 2136256304bSAlan Cox p->htotal = PSB_RVDC32(HTOTAL_A); 2146256304bSAlan Cox p->hblank = PSB_RVDC32(HBLANK_A); 2156256304bSAlan Cox p->hsync = PSB_RVDC32(HSYNC_A); 2166256304bSAlan Cox p->vtotal = PSB_RVDC32(VTOTAL_A); 2176256304bSAlan Cox p->vblank = PSB_RVDC32(VBLANK_A); 2186256304bSAlan Cox p->vsync = PSB_RVDC32(VSYNC_A); 219c6265ff5SAlan Cox regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 2206256304bSAlan Cox p->cntr = PSB_RVDC32(DSPACNTR); 2216256304bSAlan Cox p->stride = PSB_RVDC32(DSPASTRIDE); 2226256304bSAlan Cox p->addr = PSB_RVDC32(DSPABASE); 2236256304bSAlan Cox p->surf = PSB_RVDC32(DSPASURF); 2246256304bSAlan Cox p->linoff = PSB_RVDC32(DSPALINOFF); 2256256304bSAlan Cox p->tileoff = PSB_RVDC32(DSPATILEOFF); 2261b082ccfSAlan Cox 2271b082ccfSAlan Cox /* Save cursor regs */ 228c6265ff5SAlan Cox regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 229c6265ff5SAlan Cox regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 230c6265ff5SAlan Cox regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 2311b082ccfSAlan Cox 2321b082ccfSAlan Cox /* Save palette (gamma) */ 2331b082ccfSAlan Cox for (i = 0; i < 256; i++) 2346256304bSAlan Cox p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 2351b082ccfSAlan Cox 2361b082ccfSAlan Cox if (dev_priv->hdmi_priv) 2371b082ccfSAlan Cox oaktrail_hdmi_save(dev); 2381b082ccfSAlan Cox 2391b082ccfSAlan Cox /* Save performance state */ 240c6265ff5SAlan Cox regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 2411b082ccfSAlan Cox 2421b082ccfSAlan Cox /* LVDS state */ 243c6265ff5SAlan Cox regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 244c6265ff5SAlan Cox regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 245c6265ff5SAlan Cox regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 246648a8e34SAlan Cox regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 247648a8e34SAlan Cox regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 248c6265ff5SAlan Cox regs->psb.saveLVDS = PSB_RVDC32(LVDS); 249c6265ff5SAlan Cox regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 250c6265ff5SAlan Cox regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 251c6265ff5SAlan Cox regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 252c6265ff5SAlan Cox regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 2531b082ccfSAlan Cox 2541b082ccfSAlan Cox /* HW overlay */ 255c6265ff5SAlan Cox regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD); 256c6265ff5SAlan Cox regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 257c6265ff5SAlan Cox regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 258c6265ff5SAlan Cox regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 259c6265ff5SAlan Cox regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 260c6265ff5SAlan Cox regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 261c6265ff5SAlan Cox regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 2621b082ccfSAlan Cox 2631b082ccfSAlan Cox /* DPST registers */ 264c6265ff5SAlan Cox regs->psb.saveHISTOGRAM_INT_CONTROL_REG = 2651b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_INT_CONTROL); 266c6265ff5SAlan Cox regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG = 2671b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 268c6265ff5SAlan Cox regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 2691b082ccfSAlan Cox 2701b082ccfSAlan Cox if (dev_priv->iLVDS_enable) { 2711b082ccfSAlan Cox /* Shut down the panel */ 2721b082ccfSAlan Cox PSB_WVDC32(0, PP_CONTROL); 2731b082ccfSAlan Cox 2741b082ccfSAlan Cox do { 2751b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 2761b082ccfSAlan Cox } while (pp_stat & 0x80000000); 2771b082ccfSAlan Cox 2781b082ccfSAlan Cox /* Turn off the plane */ 2791b082ccfSAlan Cox PSB_WVDC32(0x58000000, DSPACNTR); 2801b082ccfSAlan Cox /* Trigger the plane disable */ 2811b082ccfSAlan Cox PSB_WVDC32(0, DSPASURF); 2821b082ccfSAlan Cox 2831b082ccfSAlan Cox /* Wait ~4 ticks */ 2841b082ccfSAlan Cox msleep(4); 2851b082ccfSAlan Cox 2861b082ccfSAlan Cox /* Turn off pipe */ 2871b082ccfSAlan Cox PSB_WVDC32(0x0, PIPEACONF); 2881b082ccfSAlan Cox /* Wait ~8 ticks */ 2891b082ccfSAlan Cox msleep(8); 2901b082ccfSAlan Cox 2911b082ccfSAlan Cox /* Turn off PLLs */ 2921b082ccfSAlan Cox PSB_WVDC32(0, MRST_DPLL_A); 2931b082ccfSAlan Cox } 2941b082ccfSAlan Cox return 0; 2951b082ccfSAlan Cox } 2961b082ccfSAlan Cox 2971b082ccfSAlan Cox /** 2981b082ccfSAlan Cox * oaktrail_restore_display_registers - restore lost register state 2991b082ccfSAlan Cox * @dev: our DRM device 3001b082ccfSAlan Cox * 3011b082ccfSAlan Cox * Restore register state that was lost during suspend and resume. 3021b082ccfSAlan Cox */ 3031b082ccfSAlan Cox static int oaktrail_restore_display_registers(struct drm_device *dev) 3041b082ccfSAlan Cox { 3051b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 306c6265ff5SAlan Cox struct psb_save_area *regs = &dev_priv->regs; 3076256304bSAlan Cox struct psb_pipe *p = ®s->pipe[0]; 3081b082ccfSAlan Cox u32 pp_stat; 3091b082ccfSAlan Cox int i; 3101b082ccfSAlan Cox 3111b082ccfSAlan Cox /* Display arbitration + watermarks */ 312c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPARB, DSPARB); 313c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1); 314c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2); 315c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3); 316c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4); 317c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5); 318c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6); 319c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT); 3201b082ccfSAlan Cox 3211b082ccfSAlan Cox /* Make sure VGA plane is off. it initializes to on after reset!*/ 3221b082ccfSAlan Cox PSB_WVDC32(0x80000000, VGACNTRL); 3231b082ccfSAlan Cox 3241b082ccfSAlan Cox /* set the plls */ 3256256304bSAlan Cox PSB_WVDC32(p->fp0, MRST_FPA0); 3266256304bSAlan Cox PSB_WVDC32(p->fp1, MRST_FPA1); 3271b082ccfSAlan Cox 3281b082ccfSAlan Cox /* Actually enable it */ 3296256304bSAlan Cox PSB_WVDC32(p->dpll, MRST_DPLL_A); 3301b082ccfSAlan Cox DRM_UDELAY(150); 3311b082ccfSAlan Cox 3321b082ccfSAlan Cox /* Restore mode */ 3336256304bSAlan Cox PSB_WVDC32(p->htotal, HTOTAL_A); 3346256304bSAlan Cox PSB_WVDC32(p->hblank, HBLANK_A); 3356256304bSAlan Cox PSB_WVDC32(p->hsync, HSYNC_A); 3366256304bSAlan Cox PSB_WVDC32(p->vtotal, VTOTAL_A); 3376256304bSAlan Cox PSB_WVDC32(p->vblank, VBLANK_A); 3386256304bSAlan Cox PSB_WVDC32(p->vsync, VSYNC_A); 3396256304bSAlan Cox PSB_WVDC32(p->src, PIPEASRC); 340c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A); 3411b082ccfSAlan Cox 3421b082ccfSAlan Cox /* Restore performance mode*/ 343c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE); 3441b082ccfSAlan Cox 3451b082ccfSAlan Cox /* Enable the pipe*/ 3461b082ccfSAlan Cox if (dev_priv->iLVDS_enable) 3476256304bSAlan Cox PSB_WVDC32(p->conf, PIPEACONF); 3481b082ccfSAlan Cox 3491b082ccfSAlan Cox /* Set up the plane*/ 3506256304bSAlan Cox PSB_WVDC32(p->linoff, DSPALINOFF); 3516256304bSAlan Cox PSB_WVDC32(p->stride, DSPASTRIDE); 3526256304bSAlan Cox PSB_WVDC32(p->tileoff, DSPATILEOFF); 3531b082ccfSAlan Cox 3541b082ccfSAlan Cox /* Enable the plane */ 3556256304bSAlan Cox PSB_WVDC32(p->cntr, DSPACNTR); 3566256304bSAlan Cox PSB_WVDC32(p->surf, DSPASURF); 3571b082ccfSAlan Cox 3581b082ccfSAlan Cox /* Enable Cursor A */ 359c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR); 360c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS); 361c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE); 3621b082ccfSAlan Cox 3631b082ccfSAlan Cox /* Restore palette (gamma) */ 3641b082ccfSAlan Cox for (i = 0; i < 256; i++) 3656256304bSAlan Cox PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2)); 3661b082ccfSAlan Cox 3671b082ccfSAlan Cox if (dev_priv->hdmi_priv) 3681b082ccfSAlan Cox oaktrail_hdmi_restore(dev); 3691b082ccfSAlan Cox 3701b082ccfSAlan Cox if (dev_priv->iLVDS_enable) { 371648a8e34SAlan Cox PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 372c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/ 373c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL); 374c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 375c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 376648a8e34SAlan Cox PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); 377c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON); 378c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF); 379c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE); 380c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL); 3811b082ccfSAlan Cox } 3821b082ccfSAlan Cox 3831b082ccfSAlan Cox /* Wait for cycle delay */ 3841b082ccfSAlan Cox do { 3851b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 3861b082ccfSAlan Cox } while (pp_stat & 0x08000000); 3871b082ccfSAlan Cox 3881b082ccfSAlan Cox /* Wait for panel power up */ 3891b082ccfSAlan Cox do { 3901b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 3911b082ccfSAlan Cox } while (pp_stat & 0x10000000); 3921b082ccfSAlan Cox 3931b082ccfSAlan Cox /* Restore HW overlay */ 394c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD); 395c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0); 396c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1); 397c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2); 398c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3); 399c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4); 400c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5); 4011b082ccfSAlan Cox 4021b082ccfSAlan Cox /* DPST registers */ 403c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG, 4041b082ccfSAlan Cox HISTOGRAM_INT_CONTROL); 405c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG, 4061b082ccfSAlan Cox HISTOGRAM_LOGIC_CONTROL); 407c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 4081b082ccfSAlan Cox 4091b082ccfSAlan Cox return 0; 4101b082ccfSAlan Cox } 4111b082ccfSAlan Cox 4121b082ccfSAlan Cox /** 4131b082ccfSAlan Cox * oaktrail_power_down - power down the display island 4141b082ccfSAlan Cox * @dev: our DRM device 4151b082ccfSAlan Cox * 4161b082ccfSAlan Cox * Power down the display interface of our device 4171b082ccfSAlan Cox */ 4181b082ccfSAlan Cox static int oaktrail_power_down(struct drm_device *dev) 4191b082ccfSAlan Cox { 4201b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4211b082ccfSAlan Cox u32 pwr_mask ; 4221b082ccfSAlan Cox u32 pwr_sts; 4231b082ccfSAlan Cox 4241b082ccfSAlan Cox pwr_mask = PSB_PWRGT_DISPLAY_MASK; 4251b082ccfSAlan Cox outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); 4261b082ccfSAlan Cox 4271b082ccfSAlan Cox while (true) { 4281b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 4291b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == pwr_mask) 4301b082ccfSAlan Cox break; 4311b082ccfSAlan Cox else 4321b082ccfSAlan Cox udelay(10); 4331b082ccfSAlan Cox } 4341b082ccfSAlan Cox return 0; 4351b082ccfSAlan Cox } 4361b082ccfSAlan Cox 4371b082ccfSAlan Cox /* 4381b082ccfSAlan Cox * oaktrail_power_up 4391b082ccfSAlan Cox * 4401b082ccfSAlan Cox * Restore power to the specified island(s) (powergating) 4411b082ccfSAlan Cox */ 4421b082ccfSAlan Cox static int oaktrail_power_up(struct drm_device *dev) 4431b082ccfSAlan Cox { 4441b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4451b082ccfSAlan Cox u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 4461b082ccfSAlan Cox u32 pwr_sts, pwr_cnt; 4471b082ccfSAlan Cox 4481b082ccfSAlan Cox pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); 4491b082ccfSAlan Cox pwr_cnt &= ~pwr_mask; 4501b082ccfSAlan Cox outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); 4511b082ccfSAlan Cox 4521b082ccfSAlan Cox while (true) { 4531b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 4541b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == 0) 4551b082ccfSAlan Cox break; 4561b082ccfSAlan Cox else 4571b082ccfSAlan Cox udelay(10); 4581b082ccfSAlan Cox } 4591b082ccfSAlan Cox return 0; 4601b082ccfSAlan Cox } 4611b082ccfSAlan Cox 4628512e074SAlan Cox /* Oaktrail */ 4638512e074SAlan Cox static const struct psb_offset oaktrail_regmap[2] = { 4648512e074SAlan Cox { 4658512e074SAlan Cox .fp0 = MRST_FPA0, 4668512e074SAlan Cox .fp1 = MRST_FPA1, 4678512e074SAlan Cox .cntr = DSPACNTR, 4688512e074SAlan Cox .conf = PIPEACONF, 4698512e074SAlan Cox .src = PIPEASRC, 4708512e074SAlan Cox .dpll = MRST_DPLL_A, 4718512e074SAlan Cox .htotal = HTOTAL_A, 4728512e074SAlan Cox .hblank = HBLANK_A, 4738512e074SAlan Cox .hsync = HSYNC_A, 4748512e074SAlan Cox .vtotal = VTOTAL_A, 4758512e074SAlan Cox .vblank = VBLANK_A, 4768512e074SAlan Cox .vsync = VSYNC_A, 4778512e074SAlan Cox .stride = DSPASTRIDE, 4788512e074SAlan Cox .size = DSPASIZE, 4798512e074SAlan Cox .pos = DSPAPOS, 4808512e074SAlan Cox .surf = DSPASURF, 481213a8434SAlan Cox .addr = MRST_DSPABASE, 48226df641eSAlan Cox .base = MRST_DSPABASE, 4838512e074SAlan Cox .status = PIPEASTAT, 4848512e074SAlan Cox .linoff = DSPALINOFF, 4858512e074SAlan Cox .tileoff = DSPATILEOFF, 4868512e074SAlan Cox .palette = PALETTE_A, 4878512e074SAlan Cox }, 4888512e074SAlan Cox { 4898512e074SAlan Cox .fp0 = FPB0, 4908512e074SAlan Cox .fp1 = FPB1, 4918512e074SAlan Cox .cntr = DSPBCNTR, 4928512e074SAlan Cox .conf = PIPEBCONF, 4938512e074SAlan Cox .src = PIPEBSRC, 4948512e074SAlan Cox .dpll = DPLL_B, 4958512e074SAlan Cox .htotal = HTOTAL_B, 4968512e074SAlan Cox .hblank = HBLANK_B, 4978512e074SAlan Cox .hsync = HSYNC_B, 4988512e074SAlan Cox .vtotal = VTOTAL_B, 4998512e074SAlan Cox .vblank = VBLANK_B, 5008512e074SAlan Cox .vsync = VSYNC_B, 5018512e074SAlan Cox .stride = DSPBSTRIDE, 5028512e074SAlan Cox .size = DSPBSIZE, 5038512e074SAlan Cox .pos = DSPBPOS, 5048512e074SAlan Cox .surf = DSPBSURF, 5058512e074SAlan Cox .addr = DSPBBASE, 50626df641eSAlan Cox .base = DSPBBASE, 5078512e074SAlan Cox .status = PIPEBSTAT, 5088512e074SAlan Cox .linoff = DSPBLINOFF, 5098512e074SAlan Cox .tileoff = DSPBTILEOFF, 5108512e074SAlan Cox .palette = PALETTE_B, 5118512e074SAlan Cox }, 5128512e074SAlan Cox }; 5131b082ccfSAlan Cox 5141b22edfdSAlan Cox static int oaktrail_chip_setup(struct drm_device *dev) 515aa0c45fdSAlan Cox { 5161b22edfdSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 5171b22edfdSAlan Cox int ret; 5181b22edfdSAlan Cox 5199c0b6fcdSAlan Cox if (pci_enable_msi(dev->pdev)) 5209c0b6fcdSAlan Cox dev_warn(dev->dev, "Enabling MSI failed!\n"); 5219c0b6fcdSAlan Cox 5228512e074SAlan Cox dev_priv->regmap = oaktrail_regmap; 5238512e074SAlan Cox 5241b22edfdSAlan Cox ret = mid_chip_setup(dev); 525aa0c45fdSAlan Cox if (ret < 0) 526aa0c45fdSAlan Cox return ret; 5274086b1e2SKirill A. Shutemov if (!dev_priv->has_gct) { 528aa0c45fdSAlan Cox /* Now pull the BIOS data */ 529d839ede4SAlan Cox psb_intel_opregion_init(dev); 530aa0c45fdSAlan Cox psb_intel_init_bios(dev); 531aa0c45fdSAlan Cox } 5326528c897SPatrik Jakobsson gma_intel_setup_gmbus(dev); 5335f503148SAlan Cox oaktrail_hdmi_setup(dev); 534aa0c45fdSAlan Cox return 0; 535aa0c45fdSAlan Cox } 536aa0c45fdSAlan Cox 5371b082ccfSAlan Cox static void oaktrail_teardown(struct drm_device *dev) 5381b082ccfSAlan Cox { 5391b22edfdSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 5401b22edfdSAlan Cox 5416528c897SPatrik Jakobsson gma_intel_teardown_gmbus(dev); 5421b082ccfSAlan Cox oaktrail_hdmi_teardown(dev); 5434086b1e2SKirill A. Shutemov if (!dev_priv->has_gct) 544aa0c45fdSAlan Cox psb_intel_destroy_bios(dev); 5451b082ccfSAlan Cox } 5461b082ccfSAlan Cox 5471b082ccfSAlan Cox const struct psb_ops oaktrail_chip_ops = { 5481b082ccfSAlan Cox .name = "Oaktrail", 5491b082ccfSAlan Cox .accel_2d = 1, 5501b082ccfSAlan Cox .pipes = 2, 5511b082ccfSAlan Cox .crtcs = 2, 55239ec748fSAlan Cox .hdmi_mask = (1 << 1), 553d235e64aSAlan Cox .lvds_mask = (1 << 0), 554cf8efd3aSPatrik Jakobsson .sdvo_mask = (1 << 1), 555bc794829SPatrik Jakobsson .cursor_needs_phys = 0, 5561b082ccfSAlan Cox .sgx_offset = MRST_SGX_OFFSET, 5571b082ccfSAlan Cox 558aa0c45fdSAlan Cox .chip_setup = oaktrail_chip_setup, 5591b082ccfSAlan Cox .chip_teardown = oaktrail_teardown, 5601b082ccfSAlan Cox .crtc_helper = &oaktrail_helper_funcs, 5611b082ccfSAlan Cox .crtc_funcs = &psb_intel_crtc_funcs, 5621b082ccfSAlan Cox 5631b082ccfSAlan Cox .output_init = oaktrail_output_init, 5641b082ccfSAlan Cox 5651b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 5661b082ccfSAlan Cox .backlight_init = oaktrail_backlight_init, 5671b082ccfSAlan Cox #endif 5681b082ccfSAlan Cox 5691b082ccfSAlan Cox .save_regs = oaktrail_save_display_registers, 5701b082ccfSAlan Cox .restore_regs = oaktrail_restore_display_registers, 5711b082ccfSAlan Cox .power_down = oaktrail_power_down, 5721b082ccfSAlan Cox .power_up = oaktrail_power_up, 5731b082ccfSAlan Cox 5741b082ccfSAlan Cox .i2c_bus = 1, 5751b082ccfSAlan Cox }; 576