11b082ccfSAlan Cox /************************************************************************** 21b082ccfSAlan Cox * Copyright (c) 2011, Intel Corporation. 31b082ccfSAlan Cox * All Rights Reserved. 41b082ccfSAlan Cox * 51b082ccfSAlan Cox * This program is free software; you can redistribute it and/or modify it 61b082ccfSAlan Cox * under the terms and conditions of the GNU General Public License, 71b082ccfSAlan Cox * version 2, as published by the Free Software Foundation. 81b082ccfSAlan Cox * 91b082ccfSAlan Cox * This program is distributed in the hope it will be useful, but WITHOUT 101b082ccfSAlan Cox * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 111b082ccfSAlan Cox * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 121b082ccfSAlan Cox * more details. 131b082ccfSAlan Cox * 141b082ccfSAlan Cox * You should have received a copy of the GNU General Public License along with 151b082ccfSAlan Cox * this program; if not, write to the Free Software Foundation, Inc., 161b082ccfSAlan Cox * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 171b082ccfSAlan Cox * 181b082ccfSAlan Cox **************************************************************************/ 191b082ccfSAlan Cox 201b082ccfSAlan Cox #include <linux/backlight.h> 211b082ccfSAlan Cox #include <linux/module.h> 221b082ccfSAlan Cox #include <linux/dmi.h> 231b082ccfSAlan Cox #include <drm/drmP.h> 241b082ccfSAlan Cox #include <drm/drm.h> 25838fa588SAlan Cox #include "gma_drm.h" 261b082ccfSAlan Cox #include "psb_drv.h" 271b082ccfSAlan Cox #include "psb_reg.h" 281b082ccfSAlan Cox #include "psb_intel_reg.h" 291b082ccfSAlan Cox #include <asm/mrst.h> 301b082ccfSAlan Cox #include <asm/intel_scu_ipc.h> 311b082ccfSAlan Cox #include "mid_bios.h" 321b082ccfSAlan Cox 331b082ccfSAlan Cox static int oaktrail_output_init(struct drm_device *dev) 341b082ccfSAlan Cox { 351b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 361b082ccfSAlan Cox if (dev_priv->iLVDS_enable) 371b082ccfSAlan Cox oaktrail_lvds_init(dev, &dev_priv->mode_dev); 381b082ccfSAlan Cox else 391b082ccfSAlan Cox dev_err(dev->dev, "DSI is not supported\n"); 401b082ccfSAlan Cox if (dev_priv->hdmi_priv) 411b082ccfSAlan Cox oaktrail_hdmi_init(dev, &dev_priv->mode_dev); 421b082ccfSAlan Cox return 0; 431b082ccfSAlan Cox } 441b082ccfSAlan Cox 451b082ccfSAlan Cox /* 461b082ccfSAlan Cox * Provide the low level interfaces for the Moorestown backlight 471b082ccfSAlan Cox */ 481b082ccfSAlan Cox 491b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 501b082ccfSAlan Cox 511b082ccfSAlan Cox #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 521b082ccfSAlan Cox #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */ 531b082ccfSAlan Cox #define BLC_PWM_FREQ_CALC_CONSTANT 32 541b082ccfSAlan Cox #define MHz 1000000 551b082ccfSAlan Cox #define BLC_ADJUSTMENT_MAX 100 561b082ccfSAlan Cox 571b082ccfSAlan Cox static struct backlight_device *oaktrail_backlight_device; 581b082ccfSAlan Cox static int oaktrail_brightness; 591b082ccfSAlan Cox 601b082ccfSAlan Cox static int oaktrail_set_brightness(struct backlight_device *bd) 611b082ccfSAlan Cox { 621b082ccfSAlan Cox struct drm_device *dev = bl_get_data(oaktrail_backlight_device); 631b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 641b082ccfSAlan Cox int level = bd->props.brightness; 651b082ccfSAlan Cox u32 blc_pwm_ctl; 661b082ccfSAlan Cox u32 max_pwm_blc; 671b082ccfSAlan Cox 681b082ccfSAlan Cox /* Percentage 1-100% being valid */ 691b082ccfSAlan Cox if (level < 1) 701b082ccfSAlan Cox level = 1; 711b082ccfSAlan Cox 721b082ccfSAlan Cox if (gma_power_begin(dev, 0)) { 731b082ccfSAlan Cox /* Calculate and set the brightness value */ 741b082ccfSAlan Cox max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 751b082ccfSAlan Cox blc_pwm_ctl = level * max_pwm_blc / 100; 761b082ccfSAlan Cox 771b082ccfSAlan Cox /* Adjust the backlight level with the percent in 781b082ccfSAlan Cox * dev_priv->blc_adj1; 791b082ccfSAlan Cox */ 801b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; 811b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100; 821b082ccfSAlan Cox 831b082ccfSAlan Cox /* Adjust the backlight level with the percent in 841b082ccfSAlan Cox * dev_priv->blc_adj2; 851b082ccfSAlan Cox */ 861b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; 871b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100; 881b082ccfSAlan Cox 891b082ccfSAlan Cox /* force PWM bit on */ 901b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 911b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 921b082ccfSAlan Cox gma_power_end(dev); 931b082ccfSAlan Cox } 941b082ccfSAlan Cox oaktrail_brightness = level; 951b082ccfSAlan Cox return 0; 961b082ccfSAlan Cox } 971b082ccfSAlan Cox 981b082ccfSAlan Cox static int oaktrail_get_brightness(struct backlight_device *bd) 991b082ccfSAlan Cox { 1001b082ccfSAlan Cox /* return locally cached var instead of HW read (due to DPST etc.) */ 1011b082ccfSAlan Cox /* FIXME: ideally return actual value in case firmware fiddled with 1021b082ccfSAlan Cox it */ 1031b082ccfSAlan Cox return oaktrail_brightness; 1041b082ccfSAlan Cox } 1051b082ccfSAlan Cox 1061b082ccfSAlan Cox static int device_backlight_init(struct drm_device *dev) 1071b082ccfSAlan Cox { 1081b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1091b082ccfSAlan Cox unsigned long core_clock; 1101b082ccfSAlan Cox u16 bl_max_freq; 1111b082ccfSAlan Cox uint32_t value; 1121b082ccfSAlan Cox uint32_t blc_pwm_precision_factor; 1131b082ccfSAlan Cox 1141b082ccfSAlan Cox dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; 1151b082ccfSAlan Cox dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; 1161b082ccfSAlan Cox bl_max_freq = 256; 1171b082ccfSAlan Cox /* this needs to be set elsewhere */ 1181b082ccfSAlan Cox blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; 1191b082ccfSAlan Cox 1201b082ccfSAlan Cox core_clock = dev_priv->core_freq; 1211b082ccfSAlan Cox 1221b082ccfSAlan Cox value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; 1231b082ccfSAlan Cox value *= blc_pwm_precision_factor; 1241b082ccfSAlan Cox value /= bl_max_freq; 1251b082ccfSAlan Cox value /= blc_pwm_precision_factor; 1261b082ccfSAlan Cox 1271b082ccfSAlan Cox if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ) 1281b082ccfSAlan Cox return -ERANGE; 1291b082ccfSAlan Cox 1301b082ccfSAlan Cox if (gma_power_begin(dev, false)) { 1311b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 1321b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 1331b082ccfSAlan Cox gma_power_end(dev); 1341b082ccfSAlan Cox } 1351b082ccfSAlan Cox return 0; 1361b082ccfSAlan Cox } 1371b082ccfSAlan Cox 1381b082ccfSAlan Cox static const struct backlight_ops oaktrail_ops = { 1391b082ccfSAlan Cox .get_brightness = oaktrail_get_brightness, 1401b082ccfSAlan Cox .update_status = oaktrail_set_brightness, 1411b082ccfSAlan Cox }; 1421b082ccfSAlan Cox 1431b082ccfSAlan Cox int oaktrail_backlight_init(struct drm_device *dev) 1441b082ccfSAlan Cox { 1451b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1461b082ccfSAlan Cox int ret; 1471b082ccfSAlan Cox struct backlight_properties props; 1481b082ccfSAlan Cox 1491b082ccfSAlan Cox memset(&props, 0, sizeof(struct backlight_properties)); 1501b082ccfSAlan Cox props.max_brightness = 100; 1511b082ccfSAlan Cox props.type = BACKLIGHT_PLATFORM; 1521b082ccfSAlan Cox 1531b082ccfSAlan Cox oaktrail_backlight_device = backlight_device_register("oaktrail-bl", 1541b082ccfSAlan Cox NULL, (void *)dev, &oaktrail_ops, &props); 1551b082ccfSAlan Cox 1561b082ccfSAlan Cox if (IS_ERR(oaktrail_backlight_device)) 1571b082ccfSAlan Cox return PTR_ERR(oaktrail_backlight_device); 1581b082ccfSAlan Cox 1591b082ccfSAlan Cox ret = device_backlight_init(dev); 1601b082ccfSAlan Cox if (ret < 0) { 1611b082ccfSAlan Cox backlight_device_unregister(oaktrail_backlight_device); 1621b082ccfSAlan Cox return ret; 1631b082ccfSAlan Cox } 1641b082ccfSAlan Cox oaktrail_backlight_device->props.brightness = 100; 1651b082ccfSAlan Cox oaktrail_backlight_device->props.max_brightness = 100; 1661b082ccfSAlan Cox backlight_update_status(oaktrail_backlight_device); 1671b082ccfSAlan Cox dev_priv->backlight_device = oaktrail_backlight_device; 1681b082ccfSAlan Cox return 0; 1691b082ccfSAlan Cox } 1701b082ccfSAlan Cox 1711b082ccfSAlan Cox #endif 1721b082ccfSAlan Cox 1731b082ccfSAlan Cox /* 1741b082ccfSAlan Cox * Provide the Moorestown specific chip logic and low level methods 1751b082ccfSAlan Cox * for power management 1761b082ccfSAlan Cox */ 1771b082ccfSAlan Cox 1781b082ccfSAlan Cox static void oaktrail_init_pm(struct drm_device *dev) 1791b082ccfSAlan Cox { 1801b082ccfSAlan Cox } 1811b082ccfSAlan Cox 1821b082ccfSAlan Cox /** 1831b082ccfSAlan Cox * oaktrail_save_display_registers - save registers lost on suspend 1841b082ccfSAlan Cox * @dev: our DRM device 1851b082ccfSAlan Cox * 1861b082ccfSAlan Cox * Save the state we need in order to be able to restore the interface 1871b082ccfSAlan Cox * upon resume from suspend 1881b082ccfSAlan Cox */ 1891b082ccfSAlan Cox static int oaktrail_save_display_registers(struct drm_device *dev) 1901b082ccfSAlan Cox { 1911b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1921b082ccfSAlan Cox int i; 1931b082ccfSAlan Cox u32 pp_stat; 1941b082ccfSAlan Cox 1951b082ccfSAlan Cox /* Display arbitration control + watermarks */ 1961b082ccfSAlan Cox dev_priv->saveDSPARB = PSB_RVDC32(DSPARB); 1971b082ccfSAlan Cox dev_priv->saveDSPFW1 = PSB_RVDC32(DSPFW1); 1981b082ccfSAlan Cox dev_priv->saveDSPFW2 = PSB_RVDC32(DSPFW2); 1991b082ccfSAlan Cox dev_priv->saveDSPFW3 = PSB_RVDC32(DSPFW3); 2001b082ccfSAlan Cox dev_priv->saveDSPFW4 = PSB_RVDC32(DSPFW4); 2011b082ccfSAlan Cox dev_priv->saveDSPFW5 = PSB_RVDC32(DSPFW5); 2021b082ccfSAlan Cox dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6); 2031b082ccfSAlan Cox dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 2041b082ccfSAlan Cox 2051b082ccfSAlan Cox /* Pipe & plane A info */ 2061b082ccfSAlan Cox dev_priv->savePIPEACONF = PSB_RVDC32(PIPEACONF); 2071b082ccfSAlan Cox dev_priv->savePIPEASRC = PSB_RVDC32(PIPEASRC); 2081b082ccfSAlan Cox dev_priv->saveFPA0 = PSB_RVDC32(MRST_FPA0); 2091b082ccfSAlan Cox dev_priv->saveFPA1 = PSB_RVDC32(MRST_FPA1); 2101b082ccfSAlan Cox dev_priv->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A); 2111b082ccfSAlan Cox dev_priv->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A); 2121b082ccfSAlan Cox dev_priv->saveHBLANK_A = PSB_RVDC32(HBLANK_A); 2131b082ccfSAlan Cox dev_priv->saveHSYNC_A = PSB_RVDC32(HSYNC_A); 2141b082ccfSAlan Cox dev_priv->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A); 2151b082ccfSAlan Cox dev_priv->saveVBLANK_A = PSB_RVDC32(VBLANK_A); 2161b082ccfSAlan Cox dev_priv->saveVSYNC_A = PSB_RVDC32(VSYNC_A); 2171b082ccfSAlan Cox dev_priv->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 2181b082ccfSAlan Cox dev_priv->saveDSPACNTR = PSB_RVDC32(DSPACNTR); 2191b082ccfSAlan Cox dev_priv->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE); 2201b082ccfSAlan Cox dev_priv->saveDSPAADDR = PSB_RVDC32(DSPABASE); 2211b082ccfSAlan Cox dev_priv->saveDSPASURF = PSB_RVDC32(DSPASURF); 2221b082ccfSAlan Cox dev_priv->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF); 2231b082ccfSAlan Cox dev_priv->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF); 2241b082ccfSAlan Cox 2251b082ccfSAlan Cox /* Save cursor regs */ 2261b082ccfSAlan Cox dev_priv->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 2271b082ccfSAlan Cox dev_priv->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 2281b082ccfSAlan Cox dev_priv->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 2291b082ccfSAlan Cox 2301b082ccfSAlan Cox /* Save palette (gamma) */ 2311b082ccfSAlan Cox for (i = 0; i < 256; i++) 2321b082ccfSAlan Cox dev_priv->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 2331b082ccfSAlan Cox 2341b082ccfSAlan Cox if (dev_priv->hdmi_priv) 2351b082ccfSAlan Cox oaktrail_hdmi_save(dev); 2361b082ccfSAlan Cox 2371b082ccfSAlan Cox /* Save performance state */ 2381b082ccfSAlan Cox dev_priv->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 2391b082ccfSAlan Cox 2401b082ccfSAlan Cox /* LVDS state */ 2411b082ccfSAlan Cox dev_priv->savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 2421b082ccfSAlan Cox dev_priv->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 2431b082ccfSAlan Cox dev_priv->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 2441b082ccfSAlan Cox dev_priv->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 2451b082ccfSAlan Cox dev_priv->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 2461b082ccfSAlan Cox dev_priv->saveLVDS = PSB_RVDC32(LVDS); 2471b082ccfSAlan Cox dev_priv->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 2481b082ccfSAlan Cox dev_priv->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 2491b082ccfSAlan Cox dev_priv->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 2501b082ccfSAlan Cox dev_priv->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 2511b082ccfSAlan Cox 2521b082ccfSAlan Cox /* HW overlay */ 2531b082ccfSAlan Cox dev_priv->saveOV_OVADD = PSB_RVDC32(OV_OVADD); 2541b082ccfSAlan Cox dev_priv->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 2551b082ccfSAlan Cox dev_priv->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 2561b082ccfSAlan Cox dev_priv->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 2571b082ccfSAlan Cox dev_priv->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 2581b082ccfSAlan Cox dev_priv->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 2591b082ccfSAlan Cox dev_priv->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 2601b082ccfSAlan Cox 2611b082ccfSAlan Cox /* DPST registers */ 2621b082ccfSAlan Cox dev_priv->saveHISTOGRAM_INT_CONTROL_REG = 2631b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_INT_CONTROL); 2641b082ccfSAlan Cox dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG = 2651b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 2661b082ccfSAlan Cox dev_priv->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 2671b082ccfSAlan Cox 2681b082ccfSAlan Cox if (dev_priv->iLVDS_enable) { 2691b082ccfSAlan Cox /* Shut down the panel */ 2701b082ccfSAlan Cox PSB_WVDC32(0, PP_CONTROL); 2711b082ccfSAlan Cox 2721b082ccfSAlan Cox do { 2731b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 2741b082ccfSAlan Cox } while (pp_stat & 0x80000000); 2751b082ccfSAlan Cox 2761b082ccfSAlan Cox /* Turn off the plane */ 2771b082ccfSAlan Cox PSB_WVDC32(0x58000000, DSPACNTR); 2781b082ccfSAlan Cox /* Trigger the plane disable */ 2791b082ccfSAlan Cox PSB_WVDC32(0, DSPASURF); 2801b082ccfSAlan Cox 2811b082ccfSAlan Cox /* Wait ~4 ticks */ 2821b082ccfSAlan Cox msleep(4); 2831b082ccfSAlan Cox 2841b082ccfSAlan Cox /* Turn off pipe */ 2851b082ccfSAlan Cox PSB_WVDC32(0x0, PIPEACONF); 2861b082ccfSAlan Cox /* Wait ~8 ticks */ 2871b082ccfSAlan Cox msleep(8); 2881b082ccfSAlan Cox 2891b082ccfSAlan Cox /* Turn off PLLs */ 2901b082ccfSAlan Cox PSB_WVDC32(0, MRST_DPLL_A); 2911b082ccfSAlan Cox } 2921b082ccfSAlan Cox return 0; 2931b082ccfSAlan Cox } 2941b082ccfSAlan Cox 2951b082ccfSAlan Cox /** 2961b082ccfSAlan Cox * oaktrail_restore_display_registers - restore lost register state 2971b082ccfSAlan Cox * @dev: our DRM device 2981b082ccfSAlan Cox * 2991b082ccfSAlan Cox * Restore register state that was lost during suspend and resume. 3001b082ccfSAlan Cox */ 3011b082ccfSAlan Cox static int oaktrail_restore_display_registers(struct drm_device *dev) 3021b082ccfSAlan Cox { 3031b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 3041b082ccfSAlan Cox u32 pp_stat; 3051b082ccfSAlan Cox int i; 3061b082ccfSAlan Cox 3071b082ccfSAlan Cox /* Display arbitration + watermarks */ 3081b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPARB, DSPARB); 3091b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPFW1, DSPFW1); 3101b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPFW2, DSPFW2); 3111b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPFW3, DSPFW3); 3121b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPFW4, DSPFW4); 3131b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPFW5, DSPFW5); 3141b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPFW6, DSPFW6); 3151b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveCHICKENBIT, DSPCHICKENBIT); 3161b082ccfSAlan Cox 3171b082ccfSAlan Cox /* Make sure VGA plane is off. it initializes to on after reset!*/ 3181b082ccfSAlan Cox PSB_WVDC32(0x80000000, VGACNTRL); 3191b082ccfSAlan Cox 3201b082ccfSAlan Cox /* set the plls */ 3211b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveFPA0, MRST_FPA0); 3221b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveFPA1, MRST_FPA1); 3231b082ccfSAlan Cox 3241b082ccfSAlan Cox /* Actually enable it */ 3251b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDPLL_A, MRST_DPLL_A); 3261b082ccfSAlan Cox DRM_UDELAY(150); 3271b082ccfSAlan Cox 3281b082ccfSAlan Cox /* Restore mode */ 3291b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveHTOTAL_A, HTOTAL_A); 3301b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveHBLANK_A, HBLANK_A); 3311b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveHSYNC_A, HSYNC_A); 3321b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveVTOTAL_A, VTOTAL_A); 3331b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveVBLANK_A, VBLANK_A); 3341b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveVSYNC_A, VSYNC_A); 3351b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePIPEASRC, PIPEASRC); 3361b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveBCLRPAT_A, BCLRPAT_A); 3371b082ccfSAlan Cox 3381b082ccfSAlan Cox /* Restore performance mode*/ 3391b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePERF_MODE, MRST_PERF_MODE); 3401b082ccfSAlan Cox 3411b082ccfSAlan Cox /* Enable the pipe*/ 3421b082ccfSAlan Cox if (dev_priv->iLVDS_enable) 3431b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePIPEACONF, PIPEACONF); 3441b082ccfSAlan Cox 3451b082ccfSAlan Cox /* Set up the plane*/ 3461b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPALINOFF, DSPALINOFF); 3471b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPASTRIDE, DSPASTRIDE); 3481b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPATILEOFF, DSPATILEOFF); 3491b082ccfSAlan Cox 3501b082ccfSAlan Cox /* Enable the plane */ 3511b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPACNTR, DSPACNTR); 3521b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPASURF, DSPASURF); 3531b082ccfSAlan Cox 3541b082ccfSAlan Cox /* Enable Cursor A */ 3551b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPACURSOR_CTRL, CURACNTR); 3561b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPACURSOR_POS, CURAPOS); 3571b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveDSPACURSOR_BASE, CURABASE); 3581b082ccfSAlan Cox 3591b082ccfSAlan Cox /* Restore palette (gamma) */ 3601b082ccfSAlan Cox for (i = 0; i < 256; i++) 3611b082ccfSAlan Cox PSB_WVDC32(dev_priv->save_palette_a[i], PALETTE_A + (i << 2)); 3621b082ccfSAlan Cox 3631b082ccfSAlan Cox if (dev_priv->hdmi_priv) 3641b082ccfSAlan Cox oaktrail_hdmi_restore(dev); 3651b082ccfSAlan Cox 3661b082ccfSAlan Cox if (dev_priv->iLVDS_enable) { 3671b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 3681b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveLVDS, LVDS); /*port 61180h*/ 3691b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePFIT_CONTROL, PFIT_CONTROL); 3701b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 3711b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 3721b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveBLC_PWM_CTL, BLC_PWM_CTL); 3731b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePP_ON_DELAYS, LVDSPP_ON); 3741b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePP_OFF_DELAYS, LVDSPP_OFF); 3751b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePP_DIVISOR, PP_CYCLE); 3761b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePP_CONTROL, PP_CONTROL); 3771b082ccfSAlan Cox } 3781b082ccfSAlan Cox 3791b082ccfSAlan Cox /* Wait for cycle delay */ 3801b082ccfSAlan Cox do { 3811b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 3821b082ccfSAlan Cox } while (pp_stat & 0x08000000); 3831b082ccfSAlan Cox 3841b082ccfSAlan Cox /* Wait for panel power up */ 3851b082ccfSAlan Cox do { 3861b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 3871b082ccfSAlan Cox } while (pp_stat & 0x10000000); 3881b082ccfSAlan Cox 3891b082ccfSAlan Cox /* Restore HW overlay */ 3901b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OVADD, OV_OVADD); 3911b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OGAMC0, OV_OGAMC0); 3921b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OGAMC1, OV_OGAMC1); 3931b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OGAMC2, OV_OGAMC2); 3941b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OGAMC3, OV_OGAMC3); 3951b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OGAMC4, OV_OGAMC4); 3961b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveOV_OGAMC5, OV_OGAMC5); 3971b082ccfSAlan Cox 3981b082ccfSAlan Cox /* DPST registers */ 3991b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveHISTOGRAM_INT_CONTROL_REG, 4001b082ccfSAlan Cox HISTOGRAM_INT_CONTROL); 4011b082ccfSAlan Cox PSB_WVDC32(dev_priv->saveHISTOGRAM_LOGIC_CONTROL_REG, 4021b082ccfSAlan Cox HISTOGRAM_LOGIC_CONTROL); 4031b082ccfSAlan Cox PSB_WVDC32(dev_priv->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 4041b082ccfSAlan Cox 4051b082ccfSAlan Cox return 0; 4061b082ccfSAlan Cox } 4071b082ccfSAlan Cox 4081b082ccfSAlan Cox /** 4091b082ccfSAlan Cox * oaktrail_power_down - power down the display island 4101b082ccfSAlan Cox * @dev: our DRM device 4111b082ccfSAlan Cox * 4121b082ccfSAlan Cox * Power down the display interface of our device 4131b082ccfSAlan Cox */ 4141b082ccfSAlan Cox static int oaktrail_power_down(struct drm_device *dev) 4151b082ccfSAlan Cox { 4161b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4171b082ccfSAlan Cox u32 pwr_mask ; 4181b082ccfSAlan Cox u32 pwr_sts; 4191b082ccfSAlan Cox 4201b082ccfSAlan Cox pwr_mask = PSB_PWRGT_DISPLAY_MASK; 4211b082ccfSAlan Cox outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); 4221b082ccfSAlan Cox 4231b082ccfSAlan Cox while (true) { 4241b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 4251b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == pwr_mask) 4261b082ccfSAlan Cox break; 4271b082ccfSAlan Cox else 4281b082ccfSAlan Cox udelay(10); 4291b082ccfSAlan Cox } 4301b082ccfSAlan Cox return 0; 4311b082ccfSAlan Cox } 4321b082ccfSAlan Cox 4331b082ccfSAlan Cox /* 4341b082ccfSAlan Cox * oaktrail_power_up 4351b082ccfSAlan Cox * 4361b082ccfSAlan Cox * Restore power to the specified island(s) (powergating) 4371b082ccfSAlan Cox */ 4381b082ccfSAlan Cox static int oaktrail_power_up(struct drm_device *dev) 4391b082ccfSAlan Cox { 4401b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4411b082ccfSAlan Cox u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 4421b082ccfSAlan Cox u32 pwr_sts, pwr_cnt; 4431b082ccfSAlan Cox 4441b082ccfSAlan Cox pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); 4451b082ccfSAlan Cox pwr_cnt &= ~pwr_mask; 4461b082ccfSAlan Cox outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); 4471b082ccfSAlan Cox 4481b082ccfSAlan Cox while (true) { 4491b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 4501b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == 0) 4511b082ccfSAlan Cox break; 4521b082ccfSAlan Cox else 4531b082ccfSAlan Cox udelay(10); 4541b082ccfSAlan Cox } 4551b082ccfSAlan Cox return 0; 4561b082ccfSAlan Cox } 4571b082ccfSAlan Cox 4581b082ccfSAlan Cox 4591b082ccfSAlan Cox static void oaktrail_teardown(struct drm_device *dev) 4601b082ccfSAlan Cox { 4611b082ccfSAlan Cox oaktrail_hdmi_teardown(dev); 4621b082ccfSAlan Cox } 4631b082ccfSAlan Cox 4641b082ccfSAlan Cox const struct psb_ops oaktrail_chip_ops = { 4651b082ccfSAlan Cox .name = "Oaktrail", 4661b082ccfSAlan Cox .accel_2d = 1, 4671b082ccfSAlan Cox .pipes = 2, 4681b082ccfSAlan Cox .crtcs = 2, 4691b082ccfSAlan Cox .sgx_offset = MRST_SGX_OFFSET, 4701b082ccfSAlan Cox 4711b082ccfSAlan Cox .chip_setup = mid_chip_setup, 4721b082ccfSAlan Cox .chip_teardown = oaktrail_teardown, 4731b082ccfSAlan Cox .crtc_helper = &oaktrail_helper_funcs, 4741b082ccfSAlan Cox .crtc_funcs = &psb_intel_crtc_funcs, 4751b082ccfSAlan Cox 4761b082ccfSAlan Cox .output_init = oaktrail_output_init, 4771b082ccfSAlan Cox 4781b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 4791b082ccfSAlan Cox .backlight_init = oaktrail_backlight_init, 4801b082ccfSAlan Cox #endif 4811b082ccfSAlan Cox 4821b082ccfSAlan Cox .init_pm = oaktrail_init_pm, 4831b082ccfSAlan Cox .save_regs = oaktrail_save_display_registers, 4841b082ccfSAlan Cox .restore_regs = oaktrail_restore_display_registers, 4851b082ccfSAlan Cox .power_down = oaktrail_power_down, 4861b082ccfSAlan Cox .power_up = oaktrail_power_up, 4871b082ccfSAlan Cox 4881b082ccfSAlan Cox .i2c_bus = 1, 4891b082ccfSAlan Cox }; 490