11b082ccfSAlan Cox /************************************************************************** 21b082ccfSAlan Cox * Copyright (c) 2011, Intel Corporation. 31b082ccfSAlan Cox * All Rights Reserved. 41b082ccfSAlan Cox * 51b082ccfSAlan Cox * This program is free software; you can redistribute it and/or modify it 61b082ccfSAlan Cox * under the terms and conditions of the GNU General Public License, 71b082ccfSAlan Cox * version 2, as published by the Free Software Foundation. 81b082ccfSAlan Cox * 91b082ccfSAlan Cox * This program is distributed in the hope it will be useful, but WITHOUT 101b082ccfSAlan Cox * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 111b082ccfSAlan Cox * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 121b082ccfSAlan Cox * more details. 131b082ccfSAlan Cox * 141b082ccfSAlan Cox * You should have received a copy of the GNU General Public License along with 151b082ccfSAlan Cox * this program; if not, write to the Free Software Foundation, Inc., 161b082ccfSAlan Cox * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 171b082ccfSAlan Cox * 181b082ccfSAlan Cox **************************************************************************/ 191b082ccfSAlan Cox 201b082ccfSAlan Cox #include <linux/backlight.h> 211b082ccfSAlan Cox #include <linux/module.h> 221b082ccfSAlan Cox #include <linux/dmi.h> 231b082ccfSAlan Cox #include <drm/drmP.h> 241b082ccfSAlan Cox #include <drm/drm.h> 25838fa588SAlan Cox #include "gma_drm.h" 261b082ccfSAlan Cox #include "psb_drv.h" 271b082ccfSAlan Cox #include "psb_reg.h" 281b082ccfSAlan Cox #include "psb_intel_reg.h" 291b082ccfSAlan Cox #include <asm/mrst.h> 301b082ccfSAlan Cox #include <asm/intel_scu_ipc.h> 311b082ccfSAlan Cox #include "mid_bios.h" 32aa0c45fdSAlan Cox #include "intel_bios.h" 331b082ccfSAlan Cox 341b082ccfSAlan Cox static int oaktrail_output_init(struct drm_device *dev) 351b082ccfSAlan Cox { 361b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 371b082ccfSAlan Cox if (dev_priv->iLVDS_enable) 381b082ccfSAlan Cox oaktrail_lvds_init(dev, &dev_priv->mode_dev); 391b082ccfSAlan Cox else 401b082ccfSAlan Cox dev_err(dev->dev, "DSI is not supported\n"); 411b082ccfSAlan Cox if (dev_priv->hdmi_priv) 421b082ccfSAlan Cox oaktrail_hdmi_init(dev, &dev_priv->mode_dev); 431b082ccfSAlan Cox return 0; 441b082ccfSAlan Cox } 451b082ccfSAlan Cox 461b082ccfSAlan Cox /* 471b082ccfSAlan Cox * Provide the low level interfaces for the Moorestown backlight 481b082ccfSAlan Cox */ 491b082ccfSAlan Cox 501b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 511b082ccfSAlan Cox 521b082ccfSAlan Cox #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF 531b082ccfSAlan Cox #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */ 541b082ccfSAlan Cox #define BLC_PWM_FREQ_CALC_CONSTANT 32 551b082ccfSAlan Cox #define MHz 1000000 561b082ccfSAlan Cox #define BLC_ADJUSTMENT_MAX 100 571b082ccfSAlan Cox 581b082ccfSAlan Cox static struct backlight_device *oaktrail_backlight_device; 591b082ccfSAlan Cox static int oaktrail_brightness; 601b082ccfSAlan Cox 611b082ccfSAlan Cox static int oaktrail_set_brightness(struct backlight_device *bd) 621b082ccfSAlan Cox { 631b082ccfSAlan Cox struct drm_device *dev = bl_get_data(oaktrail_backlight_device); 641b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 651b082ccfSAlan Cox int level = bd->props.brightness; 661b082ccfSAlan Cox u32 blc_pwm_ctl; 671b082ccfSAlan Cox u32 max_pwm_blc; 681b082ccfSAlan Cox 691b082ccfSAlan Cox /* Percentage 1-100% being valid */ 701b082ccfSAlan Cox if (level < 1) 711b082ccfSAlan Cox level = 1; 721b082ccfSAlan Cox 731b082ccfSAlan Cox if (gma_power_begin(dev, 0)) { 741b082ccfSAlan Cox /* Calculate and set the brightness value */ 751b082ccfSAlan Cox max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; 761b082ccfSAlan Cox blc_pwm_ctl = level * max_pwm_blc / 100; 771b082ccfSAlan Cox 781b082ccfSAlan Cox /* Adjust the backlight level with the percent in 791b082ccfSAlan Cox * dev_priv->blc_adj1; 801b082ccfSAlan Cox */ 811b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; 821b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100; 831b082ccfSAlan Cox 841b082ccfSAlan Cox /* Adjust the backlight level with the percent in 851b082ccfSAlan Cox * dev_priv->blc_adj2; 861b082ccfSAlan Cox */ 871b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; 881b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100; 891b082ccfSAlan Cox 901b082ccfSAlan Cox /* force PWM bit on */ 911b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 921b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); 931b082ccfSAlan Cox gma_power_end(dev); 941b082ccfSAlan Cox } 951b082ccfSAlan Cox oaktrail_brightness = level; 961b082ccfSAlan Cox return 0; 971b082ccfSAlan Cox } 981b082ccfSAlan Cox 991b082ccfSAlan Cox static int oaktrail_get_brightness(struct backlight_device *bd) 1001b082ccfSAlan Cox { 1011b082ccfSAlan Cox /* return locally cached var instead of HW read (due to DPST etc.) */ 1021b082ccfSAlan Cox /* FIXME: ideally return actual value in case firmware fiddled with 1031b082ccfSAlan Cox it */ 1041b082ccfSAlan Cox return oaktrail_brightness; 1051b082ccfSAlan Cox } 1061b082ccfSAlan Cox 1071b082ccfSAlan Cox static int device_backlight_init(struct drm_device *dev) 1081b082ccfSAlan Cox { 1091b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1101b082ccfSAlan Cox unsigned long core_clock; 1111b082ccfSAlan Cox u16 bl_max_freq; 1121b082ccfSAlan Cox uint32_t value; 1131b082ccfSAlan Cox uint32_t blc_pwm_precision_factor; 1141b082ccfSAlan Cox 1151b082ccfSAlan Cox dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; 1161b082ccfSAlan Cox dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX; 1171b082ccfSAlan Cox bl_max_freq = 256; 1181b082ccfSAlan Cox /* this needs to be set elsewhere */ 1191b082ccfSAlan Cox blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR; 1201b082ccfSAlan Cox 1211b082ccfSAlan Cox core_clock = dev_priv->core_freq; 1221b082ccfSAlan Cox 1231b082ccfSAlan Cox value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; 1241b082ccfSAlan Cox value *= blc_pwm_precision_factor; 1251b082ccfSAlan Cox value /= bl_max_freq; 1261b082ccfSAlan Cox value /= blc_pwm_precision_factor; 1271b082ccfSAlan Cox 1281b082ccfSAlan Cox if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ) 1291b082ccfSAlan Cox return -ERANGE; 1301b082ccfSAlan Cox 1311b082ccfSAlan Cox if (gma_power_begin(dev, false)) { 1321b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); 1331b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, value | (value << 16)); 1341b082ccfSAlan Cox gma_power_end(dev); 1351b082ccfSAlan Cox } 1361b082ccfSAlan Cox return 0; 1371b082ccfSAlan Cox } 1381b082ccfSAlan Cox 1391b082ccfSAlan Cox static const struct backlight_ops oaktrail_ops = { 1401b082ccfSAlan Cox .get_brightness = oaktrail_get_brightness, 1411b082ccfSAlan Cox .update_status = oaktrail_set_brightness, 1421b082ccfSAlan Cox }; 1431b082ccfSAlan Cox 1441b082ccfSAlan Cox int oaktrail_backlight_init(struct drm_device *dev) 1451b082ccfSAlan Cox { 1461b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 1471b082ccfSAlan Cox int ret; 1481b082ccfSAlan Cox struct backlight_properties props; 1491b082ccfSAlan Cox 1501b082ccfSAlan Cox memset(&props, 0, sizeof(struct backlight_properties)); 1511b082ccfSAlan Cox props.max_brightness = 100; 1521b082ccfSAlan Cox props.type = BACKLIGHT_PLATFORM; 1531b082ccfSAlan Cox 1541b082ccfSAlan Cox oaktrail_backlight_device = backlight_device_register("oaktrail-bl", 1551b082ccfSAlan Cox NULL, (void *)dev, &oaktrail_ops, &props); 1561b082ccfSAlan Cox 1571b082ccfSAlan Cox if (IS_ERR(oaktrail_backlight_device)) 1581b082ccfSAlan Cox return PTR_ERR(oaktrail_backlight_device); 1591b082ccfSAlan Cox 1601b082ccfSAlan Cox ret = device_backlight_init(dev); 1611b082ccfSAlan Cox if (ret < 0) { 1621b082ccfSAlan Cox backlight_device_unregister(oaktrail_backlight_device); 1631b082ccfSAlan Cox return ret; 1641b082ccfSAlan Cox } 1651b082ccfSAlan Cox oaktrail_backlight_device->props.brightness = 100; 1661b082ccfSAlan Cox oaktrail_backlight_device->props.max_brightness = 100; 1671b082ccfSAlan Cox backlight_update_status(oaktrail_backlight_device); 1681b082ccfSAlan Cox dev_priv->backlight_device = oaktrail_backlight_device; 1691b082ccfSAlan Cox return 0; 1701b082ccfSAlan Cox } 1711b082ccfSAlan Cox 1721b082ccfSAlan Cox #endif 1731b082ccfSAlan Cox 1741b082ccfSAlan Cox /* 1751b082ccfSAlan Cox * Provide the Moorestown specific chip logic and low level methods 1761b082ccfSAlan Cox * for power management 1771b082ccfSAlan Cox */ 1781b082ccfSAlan Cox 1791b082ccfSAlan Cox static void oaktrail_init_pm(struct drm_device *dev) 1801b082ccfSAlan Cox { 1811b082ccfSAlan Cox } 1821b082ccfSAlan Cox 1831b082ccfSAlan Cox /** 1841b082ccfSAlan Cox * oaktrail_save_display_registers - save registers lost on suspend 1851b082ccfSAlan Cox * @dev: our DRM device 1861b082ccfSAlan Cox * 1871b082ccfSAlan Cox * Save the state we need in order to be able to restore the interface 1881b082ccfSAlan Cox * upon resume from suspend 1891b082ccfSAlan Cox */ 1901b082ccfSAlan Cox static int oaktrail_save_display_registers(struct drm_device *dev) 1911b082ccfSAlan Cox { 1921b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 193648a8e34SAlan Cox struct psb_state *regs = &dev_priv->regs; 1941b082ccfSAlan Cox int i; 1951b082ccfSAlan Cox u32 pp_stat; 1961b082ccfSAlan Cox 1971b082ccfSAlan Cox /* Display arbitration control + watermarks */ 198648a8e34SAlan Cox regs->saveDSPARB = PSB_RVDC32(DSPARB); 199648a8e34SAlan Cox regs->saveDSPFW1 = PSB_RVDC32(DSPFW1); 200648a8e34SAlan Cox regs->saveDSPFW2 = PSB_RVDC32(DSPFW2); 201648a8e34SAlan Cox regs->saveDSPFW3 = PSB_RVDC32(DSPFW3); 202648a8e34SAlan Cox regs->saveDSPFW4 = PSB_RVDC32(DSPFW4); 203648a8e34SAlan Cox regs->saveDSPFW5 = PSB_RVDC32(DSPFW5); 204648a8e34SAlan Cox regs->saveDSPFW6 = PSB_RVDC32(DSPFW6); 205648a8e34SAlan Cox regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 2061b082ccfSAlan Cox 2071b082ccfSAlan Cox /* Pipe & plane A info */ 208648a8e34SAlan Cox regs->savePIPEACONF = PSB_RVDC32(PIPEACONF); 209648a8e34SAlan Cox regs->savePIPEASRC = PSB_RVDC32(PIPEASRC); 210648a8e34SAlan Cox regs->saveFPA0 = PSB_RVDC32(MRST_FPA0); 211648a8e34SAlan Cox regs->saveFPA1 = PSB_RVDC32(MRST_FPA1); 212648a8e34SAlan Cox regs->saveDPLL_A = PSB_RVDC32(MRST_DPLL_A); 213648a8e34SAlan Cox regs->saveHTOTAL_A = PSB_RVDC32(HTOTAL_A); 214648a8e34SAlan Cox regs->saveHBLANK_A = PSB_RVDC32(HBLANK_A); 215648a8e34SAlan Cox regs->saveHSYNC_A = PSB_RVDC32(HSYNC_A); 216648a8e34SAlan Cox regs->saveVTOTAL_A = PSB_RVDC32(VTOTAL_A); 217648a8e34SAlan Cox regs->saveVBLANK_A = PSB_RVDC32(VBLANK_A); 218648a8e34SAlan Cox regs->saveVSYNC_A = PSB_RVDC32(VSYNC_A); 219648a8e34SAlan Cox regs->saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 220648a8e34SAlan Cox regs->saveDSPACNTR = PSB_RVDC32(DSPACNTR); 221648a8e34SAlan Cox regs->saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE); 222648a8e34SAlan Cox regs->saveDSPAADDR = PSB_RVDC32(DSPABASE); 223648a8e34SAlan Cox regs->saveDSPASURF = PSB_RVDC32(DSPASURF); 224648a8e34SAlan Cox regs->saveDSPALINOFF = PSB_RVDC32(DSPALINOFF); 225648a8e34SAlan Cox regs->saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF); 2261b082ccfSAlan Cox 2271b082ccfSAlan Cox /* Save cursor regs */ 228648a8e34SAlan Cox regs->saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 229648a8e34SAlan Cox regs->saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE); 230648a8e34SAlan Cox regs->saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS); 2311b082ccfSAlan Cox 2321b082ccfSAlan Cox /* Save palette (gamma) */ 2331b082ccfSAlan Cox for (i = 0; i < 256; i++) 234648a8e34SAlan Cox regs->save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 2351b082ccfSAlan Cox 2361b082ccfSAlan Cox if (dev_priv->hdmi_priv) 2371b082ccfSAlan Cox oaktrail_hdmi_save(dev); 2381b082ccfSAlan Cox 2391b082ccfSAlan Cox /* Save performance state */ 240648a8e34SAlan Cox regs->savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE); 2411b082ccfSAlan Cox 2421b082ccfSAlan Cox /* LVDS state */ 243648a8e34SAlan Cox regs->savePP_CONTROL = PSB_RVDC32(PP_CONTROL); 244648a8e34SAlan Cox regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 245648a8e34SAlan Cox regs->savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS); 246648a8e34SAlan Cox regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); 247648a8e34SAlan Cox regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); 248648a8e34SAlan Cox regs->saveLVDS = PSB_RVDC32(LVDS); 249648a8e34SAlan Cox regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 250648a8e34SAlan Cox regs->savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON); 251648a8e34SAlan Cox regs->savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF); 252648a8e34SAlan Cox regs->savePP_DIVISOR = PSB_RVDC32(PP_CYCLE); 2531b082ccfSAlan Cox 2541b082ccfSAlan Cox /* HW overlay */ 255648a8e34SAlan Cox regs->saveOV_OVADD = PSB_RVDC32(OV_OVADD); 256648a8e34SAlan Cox regs->saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0); 257648a8e34SAlan Cox regs->saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1); 258648a8e34SAlan Cox regs->saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2); 259648a8e34SAlan Cox regs->saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3); 260648a8e34SAlan Cox regs->saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4); 261648a8e34SAlan Cox regs->saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5); 2621b082ccfSAlan Cox 2631b082ccfSAlan Cox /* DPST registers */ 264648a8e34SAlan Cox regs->saveHISTOGRAM_INT_CONTROL_REG = 2651b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_INT_CONTROL); 266648a8e34SAlan Cox regs->saveHISTOGRAM_LOGIC_CONTROL_REG = 2671b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL); 268648a8e34SAlan Cox regs->savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC); 2691b082ccfSAlan Cox 2701b082ccfSAlan Cox if (dev_priv->iLVDS_enable) { 2711b082ccfSAlan Cox /* Shut down the panel */ 2721b082ccfSAlan Cox PSB_WVDC32(0, PP_CONTROL); 2731b082ccfSAlan Cox 2741b082ccfSAlan Cox do { 2751b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 2761b082ccfSAlan Cox } while (pp_stat & 0x80000000); 2771b082ccfSAlan Cox 2781b082ccfSAlan Cox /* Turn off the plane */ 2791b082ccfSAlan Cox PSB_WVDC32(0x58000000, DSPACNTR); 2801b082ccfSAlan Cox /* Trigger the plane disable */ 2811b082ccfSAlan Cox PSB_WVDC32(0, DSPASURF); 2821b082ccfSAlan Cox 2831b082ccfSAlan Cox /* Wait ~4 ticks */ 2841b082ccfSAlan Cox msleep(4); 2851b082ccfSAlan Cox 2861b082ccfSAlan Cox /* Turn off pipe */ 2871b082ccfSAlan Cox PSB_WVDC32(0x0, PIPEACONF); 2881b082ccfSAlan Cox /* Wait ~8 ticks */ 2891b082ccfSAlan Cox msleep(8); 2901b082ccfSAlan Cox 2911b082ccfSAlan Cox /* Turn off PLLs */ 2921b082ccfSAlan Cox PSB_WVDC32(0, MRST_DPLL_A); 2931b082ccfSAlan Cox } 2941b082ccfSAlan Cox return 0; 2951b082ccfSAlan Cox } 2961b082ccfSAlan Cox 2971b082ccfSAlan Cox /** 2981b082ccfSAlan Cox * oaktrail_restore_display_registers - restore lost register state 2991b082ccfSAlan Cox * @dev: our DRM device 3001b082ccfSAlan Cox * 3011b082ccfSAlan Cox * Restore register state that was lost during suspend and resume. 3021b082ccfSAlan Cox */ 3031b082ccfSAlan Cox static int oaktrail_restore_display_registers(struct drm_device *dev) 3041b082ccfSAlan Cox { 3051b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 306648a8e34SAlan Cox struct psb_state *regs = &dev_priv->regs; 3071b082ccfSAlan Cox u32 pp_stat; 3081b082ccfSAlan Cox int i; 3091b082ccfSAlan Cox 3101b082ccfSAlan Cox /* Display arbitration + watermarks */ 311648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPARB, DSPARB); 312648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPFW1, DSPFW1); 313648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPFW2, DSPFW2); 314648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPFW3, DSPFW3); 315648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPFW4, DSPFW4); 316648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPFW5, DSPFW5); 317648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPFW6, DSPFW6); 318648a8e34SAlan Cox PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT); 3191b082ccfSAlan Cox 3201b082ccfSAlan Cox /* Make sure VGA plane is off. it initializes to on after reset!*/ 3211b082ccfSAlan Cox PSB_WVDC32(0x80000000, VGACNTRL); 3221b082ccfSAlan Cox 3231b082ccfSAlan Cox /* set the plls */ 324648a8e34SAlan Cox PSB_WVDC32(regs->saveFPA0, MRST_FPA0); 325648a8e34SAlan Cox PSB_WVDC32(regs->saveFPA1, MRST_FPA1); 3261b082ccfSAlan Cox 3271b082ccfSAlan Cox /* Actually enable it */ 328648a8e34SAlan Cox PSB_WVDC32(regs->saveDPLL_A, MRST_DPLL_A); 3291b082ccfSAlan Cox DRM_UDELAY(150); 3301b082ccfSAlan Cox 3311b082ccfSAlan Cox /* Restore mode */ 332648a8e34SAlan Cox PSB_WVDC32(regs->saveHTOTAL_A, HTOTAL_A); 333648a8e34SAlan Cox PSB_WVDC32(regs->saveHBLANK_A, HBLANK_A); 334648a8e34SAlan Cox PSB_WVDC32(regs->saveHSYNC_A, HSYNC_A); 335648a8e34SAlan Cox PSB_WVDC32(regs->saveVTOTAL_A, VTOTAL_A); 336648a8e34SAlan Cox PSB_WVDC32(regs->saveVBLANK_A, VBLANK_A); 337648a8e34SAlan Cox PSB_WVDC32(regs->saveVSYNC_A, VSYNC_A); 338648a8e34SAlan Cox PSB_WVDC32(regs->savePIPEASRC, PIPEASRC); 339648a8e34SAlan Cox PSB_WVDC32(regs->saveBCLRPAT_A, BCLRPAT_A); 3401b082ccfSAlan Cox 3411b082ccfSAlan Cox /* Restore performance mode*/ 342648a8e34SAlan Cox PSB_WVDC32(regs->savePERF_MODE, MRST_PERF_MODE); 3431b082ccfSAlan Cox 3441b082ccfSAlan Cox /* Enable the pipe*/ 3451b082ccfSAlan Cox if (dev_priv->iLVDS_enable) 346648a8e34SAlan Cox PSB_WVDC32(regs->savePIPEACONF, PIPEACONF); 3471b082ccfSAlan Cox 3481b082ccfSAlan Cox /* Set up the plane*/ 349648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPALINOFF, DSPALINOFF); 350648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPASTRIDE, DSPASTRIDE); 351648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPATILEOFF, DSPATILEOFF); 3521b082ccfSAlan Cox 3531b082ccfSAlan Cox /* Enable the plane */ 354648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPACNTR, DSPACNTR); 355648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPASURF, DSPASURF); 3561b082ccfSAlan Cox 3571b082ccfSAlan Cox /* Enable Cursor A */ 358648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPACURSOR_CTRL, CURACNTR); 359648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPACURSOR_POS, CURAPOS); 360648a8e34SAlan Cox PSB_WVDC32(regs->saveDSPACURSOR_BASE, CURABASE); 3611b082ccfSAlan Cox 3621b082ccfSAlan Cox /* Restore palette (gamma) */ 3631b082ccfSAlan Cox for (i = 0; i < 256; i++) 364648a8e34SAlan Cox PSB_WVDC32(regs->save_palette_a[i], PALETTE_A + (i << 2)); 3651b082ccfSAlan Cox 3661b082ccfSAlan Cox if (dev_priv->hdmi_priv) 3671b082ccfSAlan Cox oaktrail_hdmi_restore(dev); 3681b082ccfSAlan Cox 3691b082ccfSAlan Cox if (dev_priv->iLVDS_enable) { 370648a8e34SAlan Cox PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); 371648a8e34SAlan Cox PSB_WVDC32(regs->saveLVDS, LVDS); /*port 61180h*/ 372648a8e34SAlan Cox PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL); 373648a8e34SAlan Cox PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS); 374648a8e34SAlan Cox PSB_WVDC32(regs->savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS); 375648a8e34SAlan Cox PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); 376648a8e34SAlan Cox PSB_WVDC32(regs->savePP_ON_DELAYS, LVDSPP_ON); 377648a8e34SAlan Cox PSB_WVDC32(regs->savePP_OFF_DELAYS, LVDSPP_OFF); 378648a8e34SAlan Cox PSB_WVDC32(regs->savePP_DIVISOR, PP_CYCLE); 379648a8e34SAlan Cox PSB_WVDC32(regs->savePP_CONTROL, PP_CONTROL); 3801b082ccfSAlan Cox } 3811b082ccfSAlan Cox 3821b082ccfSAlan Cox /* Wait for cycle delay */ 3831b082ccfSAlan Cox do { 3841b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 3851b082ccfSAlan Cox } while (pp_stat & 0x08000000); 3861b082ccfSAlan Cox 3871b082ccfSAlan Cox /* Wait for panel power up */ 3881b082ccfSAlan Cox do { 3891b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS); 3901b082ccfSAlan Cox } while (pp_stat & 0x10000000); 3911b082ccfSAlan Cox 3921b082ccfSAlan Cox /* Restore HW overlay */ 393648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OVADD, OV_OVADD); 394648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OGAMC0, OV_OGAMC0); 395648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OGAMC1, OV_OGAMC1); 396648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OGAMC2, OV_OGAMC2); 397648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OGAMC3, OV_OGAMC3); 398648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OGAMC4, OV_OGAMC4); 399648a8e34SAlan Cox PSB_WVDC32(regs->saveOV_OGAMC5, OV_OGAMC5); 4001b082ccfSAlan Cox 4011b082ccfSAlan Cox /* DPST registers */ 402648a8e34SAlan Cox PSB_WVDC32(regs->saveHISTOGRAM_INT_CONTROL_REG, 4031b082ccfSAlan Cox HISTOGRAM_INT_CONTROL); 404648a8e34SAlan Cox PSB_WVDC32(regs->saveHISTOGRAM_LOGIC_CONTROL_REG, 4051b082ccfSAlan Cox HISTOGRAM_LOGIC_CONTROL); 406648a8e34SAlan Cox PSB_WVDC32(regs->savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC); 4071b082ccfSAlan Cox 4081b082ccfSAlan Cox return 0; 4091b082ccfSAlan Cox } 4101b082ccfSAlan Cox 4111b082ccfSAlan Cox /** 4121b082ccfSAlan Cox * oaktrail_power_down - power down the display island 4131b082ccfSAlan Cox * @dev: our DRM device 4141b082ccfSAlan Cox * 4151b082ccfSAlan Cox * Power down the display interface of our device 4161b082ccfSAlan Cox */ 4171b082ccfSAlan Cox static int oaktrail_power_down(struct drm_device *dev) 4181b082ccfSAlan Cox { 4191b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4201b082ccfSAlan Cox u32 pwr_mask ; 4211b082ccfSAlan Cox u32 pwr_sts; 4221b082ccfSAlan Cox 4231b082ccfSAlan Cox pwr_mask = PSB_PWRGT_DISPLAY_MASK; 4241b082ccfSAlan Cox outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); 4251b082ccfSAlan Cox 4261b082ccfSAlan Cox while (true) { 4271b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 4281b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == pwr_mask) 4291b082ccfSAlan Cox break; 4301b082ccfSAlan Cox else 4311b082ccfSAlan Cox udelay(10); 4321b082ccfSAlan Cox } 4331b082ccfSAlan Cox return 0; 4341b082ccfSAlan Cox } 4351b082ccfSAlan Cox 4361b082ccfSAlan Cox /* 4371b082ccfSAlan Cox * oaktrail_power_up 4381b082ccfSAlan Cox * 4391b082ccfSAlan Cox * Restore power to the specified island(s) (powergating) 4401b082ccfSAlan Cox */ 4411b082ccfSAlan Cox static int oaktrail_power_up(struct drm_device *dev) 4421b082ccfSAlan Cox { 4431b082ccfSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4441b082ccfSAlan Cox u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; 4451b082ccfSAlan Cox u32 pwr_sts, pwr_cnt; 4461b082ccfSAlan Cox 4471b082ccfSAlan Cox pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC); 4481b082ccfSAlan Cox pwr_cnt &= ~pwr_mask; 4491b082ccfSAlan Cox outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC)); 4501b082ccfSAlan Cox 4511b082ccfSAlan Cox while (true) { 4521b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS); 4531b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == 0) 4541b082ccfSAlan Cox break; 4551b082ccfSAlan Cox else 4561b082ccfSAlan Cox udelay(10); 4571b082ccfSAlan Cox } 4581b082ccfSAlan Cox return 0; 4591b082ccfSAlan Cox } 4601b082ccfSAlan Cox 4611b082ccfSAlan Cox 4621b22edfdSAlan Cox static int oaktrail_chip_setup(struct drm_device *dev) 463aa0c45fdSAlan Cox { 4641b22edfdSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4651b22edfdSAlan Cox struct oaktrail_vbt *vbt = &dev_priv->vbt_data; 4661b22edfdSAlan Cox int ret; 4671b22edfdSAlan Cox 4681b22edfdSAlan Cox ret = mid_chip_setup(dev); 469aa0c45fdSAlan Cox if (ret < 0) 470aa0c45fdSAlan Cox return ret; 471aa0c45fdSAlan Cox if (vbt->size == 0) { 472aa0c45fdSAlan Cox /* Now pull the BIOS data */ 473aa0c45fdSAlan Cox gma_intel_opregion_init(dev); 474aa0c45fdSAlan Cox psb_intel_init_bios(dev); 475aa0c45fdSAlan Cox } 476aa0c45fdSAlan Cox return 0; 477aa0c45fdSAlan Cox } 478aa0c45fdSAlan Cox 4791b082ccfSAlan Cox static void oaktrail_teardown(struct drm_device *dev) 4801b082ccfSAlan Cox { 4811b22edfdSAlan Cox struct drm_psb_private *dev_priv = dev->dev_private; 4821b22edfdSAlan Cox struct oaktrail_vbt *vbt = &dev_priv->vbt_data; 4831b22edfdSAlan Cox 4841b082ccfSAlan Cox oaktrail_hdmi_teardown(dev); 485aa0c45fdSAlan Cox if (vbt->size == 0) 486aa0c45fdSAlan Cox psb_intel_destroy_bios(dev); 4871b082ccfSAlan Cox } 4881b082ccfSAlan Cox 4891b082ccfSAlan Cox const struct psb_ops oaktrail_chip_ops = { 4901b082ccfSAlan Cox .name = "Oaktrail", 4911b082ccfSAlan Cox .accel_2d = 1, 4921b082ccfSAlan Cox .pipes = 2, 4931b082ccfSAlan Cox .crtcs = 2, 4941b082ccfSAlan Cox .sgx_offset = MRST_SGX_OFFSET, 4951b082ccfSAlan Cox 496aa0c45fdSAlan Cox .chip_setup = oaktrail_chip_setup, 4971b082ccfSAlan Cox .chip_teardown = oaktrail_teardown, 4981b082ccfSAlan Cox .crtc_helper = &oaktrail_helper_funcs, 4991b082ccfSAlan Cox .crtc_funcs = &psb_intel_crtc_funcs, 5001b082ccfSAlan Cox 5011b082ccfSAlan Cox .output_init = oaktrail_output_init, 5021b082ccfSAlan Cox 5031b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 5041b082ccfSAlan Cox .backlight_init = oaktrail_backlight_init, 5051b082ccfSAlan Cox #endif 5061b082ccfSAlan Cox 5071b082ccfSAlan Cox .init_pm = oaktrail_init_pm, 5081b082ccfSAlan Cox .save_regs = oaktrail_save_display_registers, 5091b082ccfSAlan Cox .restore_regs = oaktrail_restore_display_registers, 5101b082ccfSAlan Cox .power_down = oaktrail_power_down, 5111b082ccfSAlan Cox .power_up = oaktrail_power_up, 5121b082ccfSAlan Cox 5131b082ccfSAlan Cox .i2c_bus = 1, 5141b082ccfSAlan Cox }; 515