11b082ccfSAlan Cox /**************************************************************************
21b082ccfSAlan Cox  * Copyright (c) 2011, Intel Corporation.
31b082ccfSAlan Cox  * All Rights Reserved.
41b082ccfSAlan Cox  *
51b082ccfSAlan Cox  * This program is free software; you can redistribute it and/or modify it
61b082ccfSAlan Cox  * under the terms and conditions of the GNU General Public License,
71b082ccfSAlan Cox  * version 2, as published by the Free Software Foundation.
81b082ccfSAlan Cox  *
91b082ccfSAlan Cox  * This program is distributed in the hope it will be useful, but WITHOUT
101b082ccfSAlan Cox  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
111b082ccfSAlan Cox  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
121b082ccfSAlan Cox  * more details.
131b082ccfSAlan Cox  *
141b082ccfSAlan Cox  * You should have received a copy of the GNU General Public License along with
151b082ccfSAlan Cox  * this program; if not, write to the Free Software Foundation, Inc.,
161b082ccfSAlan Cox  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
171b082ccfSAlan Cox  *
181b082ccfSAlan Cox  **************************************************************************/
191b082ccfSAlan Cox 
201b082ccfSAlan Cox #include <linux/backlight.h>
211b082ccfSAlan Cox #include <linux/module.h>
221b082ccfSAlan Cox #include <linux/dmi.h>
231b082ccfSAlan Cox #include <drm/drmP.h>
241b082ccfSAlan Cox #include <drm/drm.h>
25760285e7SDavid Howells #include <drm/gma_drm.h>
261b082ccfSAlan Cox #include "psb_drv.h"
271b082ccfSAlan Cox #include "psb_reg.h"
281b082ccfSAlan Cox #include "psb_intel_reg.h"
291b082ccfSAlan Cox #include <asm/mrst.h>
301b082ccfSAlan Cox #include <asm/intel_scu_ipc.h>
311b082ccfSAlan Cox #include "mid_bios.h"
32aa0c45fdSAlan Cox #include "intel_bios.h"
331b082ccfSAlan Cox 
341b082ccfSAlan Cox static int oaktrail_output_init(struct drm_device *dev)
351b082ccfSAlan Cox {
361b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
371b082ccfSAlan Cox 	if (dev_priv->iLVDS_enable)
381b082ccfSAlan Cox 		oaktrail_lvds_init(dev, &dev_priv->mode_dev);
391b082ccfSAlan Cox 	else
401b082ccfSAlan Cox 		dev_err(dev->dev, "DSI is not supported\n");
411b082ccfSAlan Cox 	if (dev_priv->hdmi_priv)
421b082ccfSAlan Cox 		oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
431b082ccfSAlan Cox 	return 0;
441b082ccfSAlan Cox }
451b082ccfSAlan Cox 
461b082ccfSAlan Cox /*
471b082ccfSAlan Cox  *	Provide the low level interfaces for the Moorestown backlight
481b082ccfSAlan Cox  */
491b082ccfSAlan Cox 
501b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
511b082ccfSAlan Cox 
521b082ccfSAlan Cox #define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
531b082ccfSAlan Cox #define BLC_PWM_PRECISION_FACTOR 100	/* 10000000 */
541b082ccfSAlan Cox #define BLC_PWM_FREQ_CALC_CONSTANT 32
551b082ccfSAlan Cox #define MHz 1000000
561b082ccfSAlan Cox #define BLC_ADJUSTMENT_MAX 100
571b082ccfSAlan Cox 
581b082ccfSAlan Cox static struct backlight_device *oaktrail_backlight_device;
591b082ccfSAlan Cox static int oaktrail_brightness;
601b082ccfSAlan Cox 
611b082ccfSAlan Cox static int oaktrail_set_brightness(struct backlight_device *bd)
621b082ccfSAlan Cox {
631b082ccfSAlan Cox 	struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
641b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
651b082ccfSAlan Cox 	int level = bd->props.brightness;
661b082ccfSAlan Cox 	u32 blc_pwm_ctl;
671b082ccfSAlan Cox 	u32 max_pwm_blc;
681b082ccfSAlan Cox 
691b082ccfSAlan Cox 	/* Percentage 1-100% being valid */
701b082ccfSAlan Cox 	if (level < 1)
711b082ccfSAlan Cox 		level = 1;
721b082ccfSAlan Cox 
731b082ccfSAlan Cox 	if (gma_power_begin(dev, 0)) {
741b082ccfSAlan Cox 		/* Calculate and set the brightness value */
751b082ccfSAlan Cox 		max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
761b082ccfSAlan Cox 		blc_pwm_ctl = level * max_pwm_blc / 100;
771b082ccfSAlan Cox 
781b082ccfSAlan Cox 		/* Adjust the backlight level with the percent in
791b082ccfSAlan Cox 		 * dev_priv->blc_adj1;
801b082ccfSAlan Cox 		 */
811b082ccfSAlan Cox 		blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
821b082ccfSAlan Cox 		blc_pwm_ctl = blc_pwm_ctl / 100;
831b082ccfSAlan Cox 
841b082ccfSAlan Cox 		/* Adjust the backlight level with the percent in
851b082ccfSAlan Cox 		 * dev_priv->blc_adj2;
861b082ccfSAlan Cox 		 */
871b082ccfSAlan Cox 		blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
881b082ccfSAlan Cox 		blc_pwm_ctl = blc_pwm_ctl / 100;
891b082ccfSAlan Cox 
901b082ccfSAlan Cox 		/* force PWM bit on */
911b082ccfSAlan Cox 		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
921b082ccfSAlan Cox 		REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
931b082ccfSAlan Cox 		gma_power_end(dev);
941b082ccfSAlan Cox 	}
951b082ccfSAlan Cox 	oaktrail_brightness = level;
961b082ccfSAlan Cox 	return 0;
971b082ccfSAlan Cox }
981b082ccfSAlan Cox 
991b082ccfSAlan Cox static int oaktrail_get_brightness(struct backlight_device *bd)
1001b082ccfSAlan Cox {
1011b082ccfSAlan Cox 	/* return locally cached var instead of HW read (due to DPST etc.) */
1021b082ccfSAlan Cox 	/* FIXME: ideally return actual value in case firmware fiddled with
1031b082ccfSAlan Cox 	   it */
1041b082ccfSAlan Cox 	return oaktrail_brightness;
1051b082ccfSAlan Cox }
1061b082ccfSAlan Cox 
1071b082ccfSAlan Cox static int device_backlight_init(struct drm_device *dev)
1081b082ccfSAlan Cox {
1091b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
1101b082ccfSAlan Cox 	unsigned long core_clock;
1111b082ccfSAlan Cox 	u16 bl_max_freq;
1121b082ccfSAlan Cox 	uint32_t value;
1131b082ccfSAlan Cox 	uint32_t blc_pwm_precision_factor;
1141b082ccfSAlan Cox 
1151b082ccfSAlan Cox 	dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
1161b082ccfSAlan Cox 	dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
1171b082ccfSAlan Cox 	bl_max_freq = 256;
1181b082ccfSAlan Cox 	/* this needs to be set elsewhere */
1191b082ccfSAlan Cox 	blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
1201b082ccfSAlan Cox 
1211b082ccfSAlan Cox 	core_clock = dev_priv->core_freq;
1221b082ccfSAlan Cox 
1231b082ccfSAlan Cox 	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
1241b082ccfSAlan Cox 	value *= blc_pwm_precision_factor;
1251b082ccfSAlan Cox 	value /= bl_max_freq;
1261b082ccfSAlan Cox 	value /= blc_pwm_precision_factor;
1271b082ccfSAlan Cox 
1281b082ccfSAlan Cox 	if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
1291b082ccfSAlan Cox 			return -ERANGE;
1301b082ccfSAlan Cox 
1311b082ccfSAlan Cox 	if (gma_power_begin(dev, false)) {
1321b082ccfSAlan Cox 		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
1331b082ccfSAlan Cox 		REG_WRITE(BLC_PWM_CTL, value | (value << 16));
1341b082ccfSAlan Cox 		gma_power_end(dev);
1351b082ccfSAlan Cox 	}
1361b082ccfSAlan Cox 	return 0;
1371b082ccfSAlan Cox }
1381b082ccfSAlan Cox 
1391b082ccfSAlan Cox static const struct backlight_ops oaktrail_ops = {
1401b082ccfSAlan Cox 	.get_brightness = oaktrail_get_brightness,
1411b082ccfSAlan Cox 	.update_status  = oaktrail_set_brightness,
1421b082ccfSAlan Cox };
1431b082ccfSAlan Cox 
144771f64d0SKirill A. Shutemov static int oaktrail_backlight_init(struct drm_device *dev)
1451b082ccfSAlan Cox {
1461b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
1471b082ccfSAlan Cox 	int ret;
1481b082ccfSAlan Cox 	struct backlight_properties props;
1491b082ccfSAlan Cox 
1501b082ccfSAlan Cox 	memset(&props, 0, sizeof(struct backlight_properties));
1511b082ccfSAlan Cox 	props.max_brightness = 100;
1521b082ccfSAlan Cox 	props.type = BACKLIGHT_PLATFORM;
1531b082ccfSAlan Cox 
1541b082ccfSAlan Cox 	oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
1551b082ccfSAlan Cox 				NULL, (void *)dev, &oaktrail_ops, &props);
1561b082ccfSAlan Cox 
1571b082ccfSAlan Cox 	if (IS_ERR(oaktrail_backlight_device))
1581b082ccfSAlan Cox 		return PTR_ERR(oaktrail_backlight_device);
1591b082ccfSAlan Cox 
1601b082ccfSAlan Cox 	ret = device_backlight_init(dev);
1611b082ccfSAlan Cox 	if (ret < 0) {
1621b082ccfSAlan Cox 		backlight_device_unregister(oaktrail_backlight_device);
1631b082ccfSAlan Cox 		return ret;
1641b082ccfSAlan Cox 	}
1651b082ccfSAlan Cox 	oaktrail_backlight_device->props.brightness = 100;
1661b082ccfSAlan Cox 	oaktrail_backlight_device->props.max_brightness = 100;
1671b082ccfSAlan Cox 	backlight_update_status(oaktrail_backlight_device);
1681b082ccfSAlan Cox 	dev_priv->backlight_device = oaktrail_backlight_device;
1691b082ccfSAlan Cox 	return 0;
1701b082ccfSAlan Cox }
1711b082ccfSAlan Cox 
1721b082ccfSAlan Cox #endif
1731b082ccfSAlan Cox 
1741b082ccfSAlan Cox /*
1751b082ccfSAlan Cox  *	Provide the Moorestown specific chip logic and low level methods
1761b082ccfSAlan Cox  *	for power management
1771b082ccfSAlan Cox  */
1781b082ccfSAlan Cox 
1791b082ccfSAlan Cox /**
1801b082ccfSAlan Cox  *	oaktrail_save_display_registers	-	save registers lost on suspend
1811b082ccfSAlan Cox  *	@dev: our DRM device
1821b082ccfSAlan Cox  *
1831b082ccfSAlan Cox  *	Save the state we need in order to be able to restore the interface
1841b082ccfSAlan Cox  *	upon resume from suspend
1851b082ccfSAlan Cox  */
1861b082ccfSAlan Cox static int oaktrail_save_display_registers(struct drm_device *dev)
1871b082ccfSAlan Cox {
1881b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
189c6265ff5SAlan Cox 	struct psb_save_area *regs = &dev_priv->regs;
1906256304bSAlan Cox 	struct psb_pipe *p = &regs->pipe[0];
1911b082ccfSAlan Cox 	int i;
1921b082ccfSAlan Cox 	u32 pp_stat;
1931b082ccfSAlan Cox 
1941b082ccfSAlan Cox 	/* Display arbitration control + watermarks */
195c6265ff5SAlan Cox 	regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
196c6265ff5SAlan Cox 	regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
197c6265ff5SAlan Cox 	regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
198c6265ff5SAlan Cox 	regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
199c6265ff5SAlan Cox 	regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
200c6265ff5SAlan Cox 	regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
201c6265ff5SAlan Cox 	regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
202c6265ff5SAlan Cox 	regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
2031b082ccfSAlan Cox 
2041b082ccfSAlan Cox 	/* Pipe & plane A info */
2056256304bSAlan Cox 	p->conf = PSB_RVDC32(PIPEACONF);
2066256304bSAlan Cox 	p->src = PSB_RVDC32(PIPEASRC);
2076256304bSAlan Cox 	p->fp0 = PSB_RVDC32(MRST_FPA0);
2086256304bSAlan Cox 	p->fp1 = PSB_RVDC32(MRST_FPA1);
2096256304bSAlan Cox 	p->dpll = PSB_RVDC32(MRST_DPLL_A);
2106256304bSAlan Cox 	p->htotal = PSB_RVDC32(HTOTAL_A);
2116256304bSAlan Cox 	p->hblank = PSB_RVDC32(HBLANK_A);
2126256304bSAlan Cox 	p->hsync = PSB_RVDC32(HSYNC_A);
2136256304bSAlan Cox 	p->vtotal = PSB_RVDC32(VTOTAL_A);
2146256304bSAlan Cox 	p->vblank = PSB_RVDC32(VBLANK_A);
2156256304bSAlan Cox 	p->vsync = PSB_RVDC32(VSYNC_A);
216c6265ff5SAlan Cox 	regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
2176256304bSAlan Cox 	p->cntr = PSB_RVDC32(DSPACNTR);
2186256304bSAlan Cox 	p->stride = PSB_RVDC32(DSPASTRIDE);
2196256304bSAlan Cox 	p->addr = PSB_RVDC32(DSPABASE);
2206256304bSAlan Cox 	p->surf = PSB_RVDC32(DSPASURF);
2216256304bSAlan Cox 	p->linoff = PSB_RVDC32(DSPALINOFF);
2226256304bSAlan Cox 	p->tileoff = PSB_RVDC32(DSPATILEOFF);
2231b082ccfSAlan Cox 
2241b082ccfSAlan Cox 	/* Save cursor regs */
225c6265ff5SAlan Cox 	regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
226c6265ff5SAlan Cox 	regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
227c6265ff5SAlan Cox 	regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
2281b082ccfSAlan Cox 
2291b082ccfSAlan Cox 	/* Save palette (gamma) */
2301b082ccfSAlan Cox 	for (i = 0; i < 256; i++)
2316256304bSAlan Cox 		p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
2321b082ccfSAlan Cox 
2331b082ccfSAlan Cox 	if (dev_priv->hdmi_priv)
2341b082ccfSAlan Cox 		oaktrail_hdmi_save(dev);
2351b082ccfSAlan Cox 
2361b082ccfSAlan Cox 	/* Save performance state */
237c6265ff5SAlan Cox 	regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
2381b082ccfSAlan Cox 
2391b082ccfSAlan Cox 	/* LVDS state */
240c6265ff5SAlan Cox 	regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
241c6265ff5SAlan Cox 	regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
242c6265ff5SAlan Cox 	regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
243648a8e34SAlan Cox 	regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
244648a8e34SAlan Cox 	regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
245c6265ff5SAlan Cox 	regs->psb.saveLVDS = PSB_RVDC32(LVDS);
246c6265ff5SAlan Cox 	regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
247c6265ff5SAlan Cox 	regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
248c6265ff5SAlan Cox 	regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
249c6265ff5SAlan Cox 	regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
2501b082ccfSAlan Cox 
2511b082ccfSAlan Cox 	/* HW overlay */
252c6265ff5SAlan Cox 	regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
253c6265ff5SAlan Cox 	regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
254c6265ff5SAlan Cox 	regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
255c6265ff5SAlan Cox 	regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
256c6265ff5SAlan Cox 	regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
257c6265ff5SAlan Cox 	regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
258c6265ff5SAlan Cox 	regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
2591b082ccfSAlan Cox 
2601b082ccfSAlan Cox 	/* DPST registers */
261c6265ff5SAlan Cox 	regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
2621b082ccfSAlan Cox 					PSB_RVDC32(HISTOGRAM_INT_CONTROL);
263c6265ff5SAlan Cox 	regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
2641b082ccfSAlan Cox 					PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
265c6265ff5SAlan Cox 	regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
2661b082ccfSAlan Cox 
2671b082ccfSAlan Cox 	if (dev_priv->iLVDS_enable) {
2681b082ccfSAlan Cox 		/* Shut down the panel */
2691b082ccfSAlan Cox 		PSB_WVDC32(0, PP_CONTROL);
2701b082ccfSAlan Cox 
2711b082ccfSAlan Cox 		do {
2721b082ccfSAlan Cox 			pp_stat = PSB_RVDC32(PP_STATUS);
2731b082ccfSAlan Cox 		} while (pp_stat & 0x80000000);
2741b082ccfSAlan Cox 
2751b082ccfSAlan Cox 		/* Turn off the plane */
2761b082ccfSAlan Cox 		PSB_WVDC32(0x58000000, DSPACNTR);
2771b082ccfSAlan Cox 		/* Trigger the plane disable */
2781b082ccfSAlan Cox 		PSB_WVDC32(0, DSPASURF);
2791b082ccfSAlan Cox 
2801b082ccfSAlan Cox 		/* Wait ~4 ticks */
2811b082ccfSAlan Cox 		msleep(4);
2821b082ccfSAlan Cox 
2831b082ccfSAlan Cox 		/* Turn off pipe */
2841b082ccfSAlan Cox 		PSB_WVDC32(0x0, PIPEACONF);
2851b082ccfSAlan Cox 		/* Wait ~8 ticks */
2861b082ccfSAlan Cox 		msleep(8);
2871b082ccfSAlan Cox 
2881b082ccfSAlan Cox 		/* Turn off PLLs */
2891b082ccfSAlan Cox 		PSB_WVDC32(0, MRST_DPLL_A);
2901b082ccfSAlan Cox 	}
2911b082ccfSAlan Cox 	return 0;
2921b082ccfSAlan Cox }
2931b082ccfSAlan Cox 
2941b082ccfSAlan Cox /**
2951b082ccfSAlan Cox  *	oaktrail_restore_display_registers	-	restore lost register state
2961b082ccfSAlan Cox  *	@dev: our DRM device
2971b082ccfSAlan Cox  *
2981b082ccfSAlan Cox  *	Restore register state that was lost during suspend and resume.
2991b082ccfSAlan Cox  */
3001b082ccfSAlan Cox static int oaktrail_restore_display_registers(struct drm_device *dev)
3011b082ccfSAlan Cox {
3021b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
303c6265ff5SAlan Cox 	struct psb_save_area *regs = &dev_priv->regs;
3046256304bSAlan Cox 	struct psb_pipe *p = &regs->pipe[0];
3051b082ccfSAlan Cox 	u32 pp_stat;
3061b082ccfSAlan Cox 	int i;
3071b082ccfSAlan Cox 
3081b082ccfSAlan Cox 	/* Display arbitration + watermarks */
309c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
310c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
311c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
312c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
313c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
314c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
315c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
316c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
3171b082ccfSAlan Cox 
3181b082ccfSAlan Cox 	/* Make sure VGA plane is off. it initializes to on after reset!*/
3191b082ccfSAlan Cox 	PSB_WVDC32(0x80000000, VGACNTRL);
3201b082ccfSAlan Cox 
3211b082ccfSAlan Cox 	/* set the plls */
3226256304bSAlan Cox 	PSB_WVDC32(p->fp0, MRST_FPA0);
3236256304bSAlan Cox 	PSB_WVDC32(p->fp1, MRST_FPA1);
3241b082ccfSAlan Cox 
3251b082ccfSAlan Cox 	/* Actually enable it */
3266256304bSAlan Cox 	PSB_WVDC32(p->dpll, MRST_DPLL_A);
3271b082ccfSAlan Cox 	DRM_UDELAY(150);
3281b082ccfSAlan Cox 
3291b082ccfSAlan Cox 	/* Restore mode */
3306256304bSAlan Cox 	PSB_WVDC32(p->htotal, HTOTAL_A);
3316256304bSAlan Cox 	PSB_WVDC32(p->hblank, HBLANK_A);
3326256304bSAlan Cox 	PSB_WVDC32(p->hsync, HSYNC_A);
3336256304bSAlan Cox 	PSB_WVDC32(p->vtotal, VTOTAL_A);
3346256304bSAlan Cox 	PSB_WVDC32(p->vblank, VBLANK_A);
3356256304bSAlan Cox 	PSB_WVDC32(p->vsync, VSYNC_A);
3366256304bSAlan Cox 	PSB_WVDC32(p->src, PIPEASRC);
337c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
3381b082ccfSAlan Cox 
3391b082ccfSAlan Cox 	/* Restore performance mode*/
340c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
3411b082ccfSAlan Cox 
3421b082ccfSAlan Cox 	/* Enable the pipe*/
3431b082ccfSAlan Cox 	if (dev_priv->iLVDS_enable)
3446256304bSAlan Cox 		PSB_WVDC32(p->conf, PIPEACONF);
3451b082ccfSAlan Cox 
3461b082ccfSAlan Cox 	/* Set up the plane*/
3476256304bSAlan Cox 	PSB_WVDC32(p->linoff, DSPALINOFF);
3486256304bSAlan Cox 	PSB_WVDC32(p->stride, DSPASTRIDE);
3496256304bSAlan Cox 	PSB_WVDC32(p->tileoff, DSPATILEOFF);
3501b082ccfSAlan Cox 
3511b082ccfSAlan Cox 	/* Enable the plane */
3526256304bSAlan Cox 	PSB_WVDC32(p->cntr, DSPACNTR);
3536256304bSAlan Cox 	PSB_WVDC32(p->surf, DSPASURF);
3541b082ccfSAlan Cox 
3551b082ccfSAlan Cox 	/* Enable Cursor A */
356c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
357c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
358c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
3591b082ccfSAlan Cox 
3601b082ccfSAlan Cox 	/* Restore palette (gamma) */
3611b082ccfSAlan Cox 	for (i = 0; i < 256; i++)
3626256304bSAlan Cox 		PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
3631b082ccfSAlan Cox 
3641b082ccfSAlan Cox 	if (dev_priv->hdmi_priv)
3651b082ccfSAlan Cox 		oaktrail_hdmi_restore(dev);
3661b082ccfSAlan Cox 
3671b082ccfSAlan Cox 	if (dev_priv->iLVDS_enable) {
368648a8e34SAlan Cox 		PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
369c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
370c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
371c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
372c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
373648a8e34SAlan Cox 		PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
374c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
375c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
376c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
377c6265ff5SAlan Cox 		PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
3781b082ccfSAlan Cox 	}
3791b082ccfSAlan Cox 
3801b082ccfSAlan Cox 	/* Wait for cycle delay */
3811b082ccfSAlan Cox 	do {
3821b082ccfSAlan Cox 		pp_stat = PSB_RVDC32(PP_STATUS);
3831b082ccfSAlan Cox 	} while (pp_stat & 0x08000000);
3841b082ccfSAlan Cox 
3851b082ccfSAlan Cox 	/* Wait for panel power up */
3861b082ccfSAlan Cox 	do {
3871b082ccfSAlan Cox 		pp_stat = PSB_RVDC32(PP_STATUS);
3881b082ccfSAlan Cox 	} while (pp_stat & 0x10000000);
3891b082ccfSAlan Cox 
3901b082ccfSAlan Cox 	/* Restore HW overlay */
391c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
392c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
393c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
394c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
395c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
396c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
397c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
3981b082ccfSAlan Cox 
3991b082ccfSAlan Cox 	/* DPST registers */
400c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
4011b082ccfSAlan Cox 						HISTOGRAM_INT_CONTROL);
402c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
4031b082ccfSAlan Cox 						HISTOGRAM_LOGIC_CONTROL);
404c6265ff5SAlan Cox 	PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
4051b082ccfSAlan Cox 
4061b082ccfSAlan Cox 	return 0;
4071b082ccfSAlan Cox }
4081b082ccfSAlan Cox 
4091b082ccfSAlan Cox /**
4101b082ccfSAlan Cox  *	oaktrail_power_down	-	power down the display island
4111b082ccfSAlan Cox  *	@dev: our DRM device
4121b082ccfSAlan Cox  *
4131b082ccfSAlan Cox  *	Power down the display interface of our device
4141b082ccfSAlan Cox  */
4151b082ccfSAlan Cox static int oaktrail_power_down(struct drm_device *dev)
4161b082ccfSAlan Cox {
4171b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
4181b082ccfSAlan Cox 	u32 pwr_mask ;
4191b082ccfSAlan Cox 	u32 pwr_sts;
4201b082ccfSAlan Cox 
4211b082ccfSAlan Cox 	pwr_mask = PSB_PWRGT_DISPLAY_MASK;
4221b082ccfSAlan Cox 	outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
4231b082ccfSAlan Cox 
4241b082ccfSAlan Cox 	while (true) {
4251b082ccfSAlan Cox 		pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
4261b082ccfSAlan Cox 		if ((pwr_sts & pwr_mask) == pwr_mask)
4271b082ccfSAlan Cox 			break;
4281b082ccfSAlan Cox 		else
4291b082ccfSAlan Cox 			udelay(10);
4301b082ccfSAlan Cox 	}
4311b082ccfSAlan Cox 	return 0;
4321b082ccfSAlan Cox }
4331b082ccfSAlan Cox 
4341b082ccfSAlan Cox /*
4351b082ccfSAlan Cox  * oaktrail_power_up
4361b082ccfSAlan Cox  *
4371b082ccfSAlan Cox  * Restore power to the specified island(s) (powergating)
4381b082ccfSAlan Cox  */
4391b082ccfSAlan Cox static int oaktrail_power_up(struct drm_device *dev)
4401b082ccfSAlan Cox {
4411b082ccfSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
4421b082ccfSAlan Cox 	u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
4431b082ccfSAlan Cox 	u32 pwr_sts, pwr_cnt;
4441b082ccfSAlan Cox 
4451b082ccfSAlan Cox 	pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
4461b082ccfSAlan Cox 	pwr_cnt &= ~pwr_mask;
4471b082ccfSAlan Cox 	outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
4481b082ccfSAlan Cox 
4491b082ccfSAlan Cox 	while (true) {
4501b082ccfSAlan Cox 		pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
4511b082ccfSAlan Cox 		if ((pwr_sts & pwr_mask) == 0)
4521b082ccfSAlan Cox 			break;
4531b082ccfSAlan Cox 		else
4541b082ccfSAlan Cox 			udelay(10);
4551b082ccfSAlan Cox 	}
4561b082ccfSAlan Cox 	return 0;
4571b082ccfSAlan Cox }
4581b082ccfSAlan Cox 
4598512e074SAlan Cox /* Oaktrail */
4608512e074SAlan Cox static const struct psb_offset oaktrail_regmap[2] = {
4618512e074SAlan Cox 	{
4628512e074SAlan Cox 		.fp0 = MRST_FPA0,
4638512e074SAlan Cox 		.fp1 = MRST_FPA1,
4648512e074SAlan Cox 		.cntr = DSPACNTR,
4658512e074SAlan Cox 		.conf = PIPEACONF,
4668512e074SAlan Cox 		.src = PIPEASRC,
4678512e074SAlan Cox 		.dpll = MRST_DPLL_A,
4688512e074SAlan Cox 		.htotal = HTOTAL_A,
4698512e074SAlan Cox 		.hblank = HBLANK_A,
4708512e074SAlan Cox 		.hsync = HSYNC_A,
4718512e074SAlan Cox 		.vtotal = VTOTAL_A,
4728512e074SAlan Cox 		.vblank = VBLANK_A,
4738512e074SAlan Cox 		.vsync = VSYNC_A,
4748512e074SAlan Cox 		.stride = DSPASTRIDE,
4758512e074SAlan Cox 		.size = DSPASIZE,
4768512e074SAlan Cox 		.pos = DSPAPOS,
4778512e074SAlan Cox 		.surf = DSPASURF,
478213a8434SAlan Cox 		.addr = MRST_DSPABASE,
47926df641eSAlan Cox 		.base = MRST_DSPABASE,
4808512e074SAlan Cox 		.status = PIPEASTAT,
4818512e074SAlan Cox 		.linoff = DSPALINOFF,
4828512e074SAlan Cox 		.tileoff = DSPATILEOFF,
4838512e074SAlan Cox 		.palette = PALETTE_A,
4848512e074SAlan Cox 	},
4858512e074SAlan Cox 	{
4868512e074SAlan Cox 		.fp0 = FPB0,
4878512e074SAlan Cox 		.fp1 = FPB1,
4888512e074SAlan Cox 		.cntr = DSPBCNTR,
4898512e074SAlan Cox 		.conf = PIPEBCONF,
4908512e074SAlan Cox 		.src = PIPEBSRC,
4918512e074SAlan Cox 		.dpll = DPLL_B,
4928512e074SAlan Cox 		.htotal = HTOTAL_B,
4938512e074SAlan Cox 		.hblank = HBLANK_B,
4948512e074SAlan Cox 		.hsync = HSYNC_B,
4958512e074SAlan Cox 		.vtotal = VTOTAL_B,
4968512e074SAlan Cox 		.vblank = VBLANK_B,
4978512e074SAlan Cox 		.vsync = VSYNC_B,
4988512e074SAlan Cox 		.stride = DSPBSTRIDE,
4998512e074SAlan Cox 		.size = DSPBSIZE,
5008512e074SAlan Cox 		.pos = DSPBPOS,
5018512e074SAlan Cox 		.surf = DSPBSURF,
5028512e074SAlan Cox 		.addr = DSPBBASE,
50326df641eSAlan Cox 		.base = DSPBBASE,
5048512e074SAlan Cox 		.status = PIPEBSTAT,
5058512e074SAlan Cox 		.linoff = DSPBLINOFF,
5068512e074SAlan Cox 		.tileoff = DSPBTILEOFF,
5078512e074SAlan Cox 		.palette = PALETTE_B,
5088512e074SAlan Cox 	},
5098512e074SAlan Cox };
5101b082ccfSAlan Cox 
5111b22edfdSAlan Cox static int oaktrail_chip_setup(struct drm_device *dev)
512aa0c45fdSAlan Cox {
5131b22edfdSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
5141b22edfdSAlan Cox 	int ret;
5151b22edfdSAlan Cox 
5169c0b6fcdSAlan Cox 	if (pci_enable_msi(dev->pdev))
5179c0b6fcdSAlan Cox 		dev_warn(dev->dev, "Enabling MSI failed!\n");
5189c0b6fcdSAlan Cox 
5198512e074SAlan Cox 	dev_priv->regmap = oaktrail_regmap;
5208512e074SAlan Cox 
5211b22edfdSAlan Cox 	ret = mid_chip_setup(dev);
522aa0c45fdSAlan Cox 	if (ret < 0)
523aa0c45fdSAlan Cox 		return ret;
5244086b1e2SKirill A. Shutemov 	if (!dev_priv->has_gct) {
525aa0c45fdSAlan Cox 		/* Now pull the BIOS data */
526d839ede4SAlan Cox 		psb_intel_opregion_init(dev);
527aa0c45fdSAlan Cox 		psb_intel_init_bios(dev);
528aa0c45fdSAlan Cox 	}
5295f503148SAlan Cox 	oaktrail_hdmi_setup(dev);
530aa0c45fdSAlan Cox 	return 0;
531aa0c45fdSAlan Cox }
532aa0c45fdSAlan Cox 
5331b082ccfSAlan Cox static void oaktrail_teardown(struct drm_device *dev)
5341b082ccfSAlan Cox {
5351b22edfdSAlan Cox 	struct drm_psb_private *dev_priv = dev->dev_private;
5361b22edfdSAlan Cox 
5371b082ccfSAlan Cox 	oaktrail_hdmi_teardown(dev);
5384086b1e2SKirill A. Shutemov 	if (!dev_priv->has_gct)
539aa0c45fdSAlan Cox 		psb_intel_destroy_bios(dev);
5401b082ccfSAlan Cox }
5411b082ccfSAlan Cox 
5421b082ccfSAlan Cox const struct psb_ops oaktrail_chip_ops = {
5431b082ccfSAlan Cox 	.name = "Oaktrail",
5441b082ccfSAlan Cox 	.accel_2d = 1,
5451b082ccfSAlan Cox 	.pipes = 2,
5461b082ccfSAlan Cox 	.crtcs = 2,
54739ec748fSAlan Cox 	.hdmi_mask = (1 << 1),
548d235e64aSAlan Cox 	.lvds_mask = (1 << 0),
549bc794829SPatrik Jakobsson 	.cursor_needs_phys = 0,
5501b082ccfSAlan Cox 	.sgx_offset = MRST_SGX_OFFSET,
5511b082ccfSAlan Cox 
552aa0c45fdSAlan Cox 	.chip_setup = oaktrail_chip_setup,
5531b082ccfSAlan Cox 	.chip_teardown = oaktrail_teardown,
5541b082ccfSAlan Cox 	.crtc_helper = &oaktrail_helper_funcs,
5551b082ccfSAlan Cox 	.crtc_funcs = &psb_intel_crtc_funcs,
5561b082ccfSAlan Cox 
5571b082ccfSAlan Cox 	.output_init = oaktrail_output_init,
5581b082ccfSAlan Cox 
5591b082ccfSAlan Cox #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
5601b082ccfSAlan Cox 	.backlight_init = oaktrail_backlight_init,
5611b082ccfSAlan Cox #endif
5621b082ccfSAlan Cox 
5631b082ccfSAlan Cox 	.save_regs = oaktrail_save_display_registers,
5641b082ccfSAlan Cox 	.restore_regs = oaktrail_restore_display_registers,
5651b082ccfSAlan Cox 	.power_down = oaktrail_power_down,
5661b082ccfSAlan Cox 	.power_up = oaktrail_power_up,
5671b082ccfSAlan Cox 
5681b082ccfSAlan Cox 	.i2c_bus = 1,
5691b082ccfSAlan Cox };
570