1a61127c2SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
21b082ccfSAlan Cox /**************************************************************************
31b082ccfSAlan Cox * Copyright (c) 2011, Intel Corporation.
41b082ccfSAlan Cox * All Rights Reserved.
51b082ccfSAlan Cox *
61b082ccfSAlan Cox **************************************************************************/
71b082ccfSAlan Cox
80c7b178aSSam Ravnborg #include <linux/delay.h>
91b082ccfSAlan Cox #include <linux/dmi.h>
100c7b178aSSam Ravnborg #include <linux/module.h>
11d825c565SSam Ravnborg
120c7b178aSSam Ravnborg #include <drm/drm.h>
130c7b178aSSam Ravnborg
14aa0c45fdSAlan Cox #include "intel_bios.h"
150c7b178aSSam Ravnborg #include "mid_bios.h"
160c7b178aSSam Ravnborg #include "psb_drv.h"
170c7b178aSSam Ravnborg #include "psb_intel_reg.h"
180c7b178aSSam Ravnborg #include "psb_reg.h"
191b082ccfSAlan Cox
oaktrail_output_init(struct drm_device * dev)201b082ccfSAlan Cox static int oaktrail_output_init(struct drm_device *dev)
211b082ccfSAlan Cox {
22f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
231b082ccfSAlan Cox if (dev_priv->iLVDS_enable)
241b082ccfSAlan Cox oaktrail_lvds_init(dev, &dev_priv->mode_dev);
251b082ccfSAlan Cox else
261b082ccfSAlan Cox dev_err(dev->dev, "DSI is not supported\n");
271b082ccfSAlan Cox if (dev_priv->hdmi_priv)
281b082ccfSAlan Cox oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
29cd3fdbe8SPatrik Jakobsson
30cd3fdbe8SPatrik Jakobsson psb_intel_sdvo_init(dev, SDVOB);
31cd3fdbe8SPatrik Jakobsson
321b082ccfSAlan Cox return 0;
331b082ccfSAlan Cox }
341b082ccfSAlan Cox
351b082ccfSAlan Cox /*
361b082ccfSAlan Cox * Provide the low level interfaces for the Moorestown backlight
371b082ccfSAlan Cox */
381b082ccfSAlan Cox
391b082ccfSAlan Cox #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
401b082ccfSAlan Cox #define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
411b082ccfSAlan Cox #define BLC_PWM_FREQ_CALC_CONSTANT 32
421b082ccfSAlan Cox #define MHz 1000000
431b082ccfSAlan Cox #define BLC_ADJUSTMENT_MAX 100
441b082ccfSAlan Cox
oaktrail_set_brightness(struct drm_device * dev,int level)45*1f90b123SHans de Goede static void oaktrail_set_brightness(struct drm_device *dev, int level)
461b082ccfSAlan Cox {
47f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
481b082ccfSAlan Cox u32 blc_pwm_ctl;
491b082ccfSAlan Cox u32 max_pwm_blc;
501b082ccfSAlan Cox
511b082ccfSAlan Cox if (gma_power_begin(dev, 0)) {
521b082ccfSAlan Cox /* Calculate and set the brightness value */
531b082ccfSAlan Cox max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
541b082ccfSAlan Cox blc_pwm_ctl = level * max_pwm_blc / 100;
551b082ccfSAlan Cox
561b082ccfSAlan Cox /* Adjust the backlight level with the percent in
571b082ccfSAlan Cox * dev_priv->blc_adj1;
581b082ccfSAlan Cox */
591b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
601b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100;
611b082ccfSAlan Cox
621b082ccfSAlan Cox /* Adjust the backlight level with the percent in
631b082ccfSAlan Cox * dev_priv->blc_adj2;
641b082ccfSAlan Cox */
651b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
661b082ccfSAlan Cox blc_pwm_ctl = blc_pwm_ctl / 100;
671b082ccfSAlan Cox
681b082ccfSAlan Cox /* force PWM bit on */
691b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
701b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
711b082ccfSAlan Cox gma_power_end(dev);
721b082ccfSAlan Cox }
731b082ccfSAlan Cox }
741b082ccfSAlan Cox
oaktrail_backlight_init(struct drm_device * dev)75*1f90b123SHans de Goede static int oaktrail_backlight_init(struct drm_device *dev)
761b082ccfSAlan Cox {
77f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
781b082ccfSAlan Cox unsigned long core_clock;
791b082ccfSAlan Cox u16 bl_max_freq;
801b082ccfSAlan Cox uint32_t value;
811b082ccfSAlan Cox uint32_t blc_pwm_precision_factor;
821b082ccfSAlan Cox
831b082ccfSAlan Cox dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
841b082ccfSAlan Cox dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
851b082ccfSAlan Cox bl_max_freq = 256;
861b082ccfSAlan Cox /* this needs to be set elsewhere */
871b082ccfSAlan Cox blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
881b082ccfSAlan Cox
891b082ccfSAlan Cox core_clock = dev_priv->core_freq;
901b082ccfSAlan Cox
911b082ccfSAlan Cox value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
921b082ccfSAlan Cox value *= blc_pwm_precision_factor;
931b082ccfSAlan Cox value /= bl_max_freq;
941b082ccfSAlan Cox value /= blc_pwm_precision_factor;
951b082ccfSAlan Cox
961b082ccfSAlan Cox if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
971b082ccfSAlan Cox return -ERANGE;
981b082ccfSAlan Cox
991b082ccfSAlan Cox if (gma_power_begin(dev, false)) {
1001b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
1011b082ccfSAlan Cox REG_WRITE(BLC_PWM_CTL, value | (value << 16));
1021b082ccfSAlan Cox gma_power_end(dev);
1031b082ccfSAlan Cox }
104*1f90b123SHans de Goede
105*1f90b123SHans de Goede oaktrail_set_brightness(dev, PSB_MAX_BRIGHTNESS);
1061b082ccfSAlan Cox return 0;
1071b082ccfSAlan Cox }
1081b082ccfSAlan Cox
1091b082ccfSAlan Cox /*
1101b082ccfSAlan Cox * Provide the Moorestown specific chip logic and low level methods
1111b082ccfSAlan Cox * for power management
1121b082ccfSAlan Cox */
1131b082ccfSAlan Cox
1141b082ccfSAlan Cox /**
1151b082ccfSAlan Cox * oaktrail_save_display_registers - save registers lost on suspend
1161b082ccfSAlan Cox * @dev: our DRM device
1171b082ccfSAlan Cox *
1181b082ccfSAlan Cox * Save the state we need in order to be able to restore the interface
1191b082ccfSAlan Cox * upon resume from suspend
1201b082ccfSAlan Cox */
oaktrail_save_display_registers(struct drm_device * dev)1211b082ccfSAlan Cox static int oaktrail_save_display_registers(struct drm_device *dev)
1221b082ccfSAlan Cox {
123f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
124c6265ff5SAlan Cox struct psb_save_area *regs = &dev_priv->regs;
1256256304bSAlan Cox struct psb_pipe *p = ®s->pipe[0];
1261b082ccfSAlan Cox int i;
1271b082ccfSAlan Cox u32 pp_stat;
1281b082ccfSAlan Cox
1291b082ccfSAlan Cox /* Display arbitration control + watermarks */
130c6265ff5SAlan Cox regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
131c6265ff5SAlan Cox regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
132c6265ff5SAlan Cox regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
133c6265ff5SAlan Cox regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
134c6265ff5SAlan Cox regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
135c6265ff5SAlan Cox regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
136c6265ff5SAlan Cox regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
137c6265ff5SAlan Cox regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
1381b082ccfSAlan Cox
1391b082ccfSAlan Cox /* Pipe & plane A info */
1406256304bSAlan Cox p->conf = PSB_RVDC32(PIPEACONF);
1416256304bSAlan Cox p->src = PSB_RVDC32(PIPEASRC);
1426256304bSAlan Cox p->fp0 = PSB_RVDC32(MRST_FPA0);
1436256304bSAlan Cox p->fp1 = PSB_RVDC32(MRST_FPA1);
1446256304bSAlan Cox p->dpll = PSB_RVDC32(MRST_DPLL_A);
1456256304bSAlan Cox p->htotal = PSB_RVDC32(HTOTAL_A);
1466256304bSAlan Cox p->hblank = PSB_RVDC32(HBLANK_A);
1476256304bSAlan Cox p->hsync = PSB_RVDC32(HSYNC_A);
1486256304bSAlan Cox p->vtotal = PSB_RVDC32(VTOTAL_A);
1496256304bSAlan Cox p->vblank = PSB_RVDC32(VBLANK_A);
1506256304bSAlan Cox p->vsync = PSB_RVDC32(VSYNC_A);
151c6265ff5SAlan Cox regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
1526256304bSAlan Cox p->cntr = PSB_RVDC32(DSPACNTR);
1536256304bSAlan Cox p->stride = PSB_RVDC32(DSPASTRIDE);
1546256304bSAlan Cox p->addr = PSB_RVDC32(DSPABASE);
1556256304bSAlan Cox p->surf = PSB_RVDC32(DSPASURF);
1566256304bSAlan Cox p->linoff = PSB_RVDC32(DSPALINOFF);
1576256304bSAlan Cox p->tileoff = PSB_RVDC32(DSPATILEOFF);
1581b082ccfSAlan Cox
1591b082ccfSAlan Cox /* Save cursor regs */
160c6265ff5SAlan Cox regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
161c6265ff5SAlan Cox regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
162c6265ff5SAlan Cox regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
1631b082ccfSAlan Cox
1641b082ccfSAlan Cox /* Save palette (gamma) */
1651b082ccfSAlan Cox for (i = 0; i < 256; i++)
1666256304bSAlan Cox p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
1671b082ccfSAlan Cox
1681b082ccfSAlan Cox if (dev_priv->hdmi_priv)
1691b082ccfSAlan Cox oaktrail_hdmi_save(dev);
1701b082ccfSAlan Cox
1711b082ccfSAlan Cox /* Save performance state */
172c6265ff5SAlan Cox regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
1731b082ccfSAlan Cox
1741b082ccfSAlan Cox /* LVDS state */
175c6265ff5SAlan Cox regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
176c6265ff5SAlan Cox regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
177c6265ff5SAlan Cox regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
178648a8e34SAlan Cox regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
179648a8e34SAlan Cox regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
180c6265ff5SAlan Cox regs->psb.saveLVDS = PSB_RVDC32(LVDS);
181c6265ff5SAlan Cox regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
182c6265ff5SAlan Cox regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
183c6265ff5SAlan Cox regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
184c6265ff5SAlan Cox regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
1851b082ccfSAlan Cox
1861b082ccfSAlan Cox /* HW overlay */
187c6265ff5SAlan Cox regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
188c6265ff5SAlan Cox regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
189c6265ff5SAlan Cox regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
190c6265ff5SAlan Cox regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
191c6265ff5SAlan Cox regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
192c6265ff5SAlan Cox regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
193c6265ff5SAlan Cox regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1941b082ccfSAlan Cox
1951b082ccfSAlan Cox /* DPST registers */
196c6265ff5SAlan Cox regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
1971b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_INT_CONTROL);
198c6265ff5SAlan Cox regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
1991b082ccfSAlan Cox PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
200c6265ff5SAlan Cox regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
2011b082ccfSAlan Cox
2021b082ccfSAlan Cox if (dev_priv->iLVDS_enable) {
2031b082ccfSAlan Cox /* Shut down the panel */
2041b082ccfSAlan Cox PSB_WVDC32(0, PP_CONTROL);
2051b082ccfSAlan Cox
2061b082ccfSAlan Cox do {
2071b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS);
2081b082ccfSAlan Cox } while (pp_stat & 0x80000000);
2091b082ccfSAlan Cox
2101b082ccfSAlan Cox /* Turn off the plane */
2111b082ccfSAlan Cox PSB_WVDC32(0x58000000, DSPACNTR);
2121b082ccfSAlan Cox /* Trigger the plane disable */
2131b082ccfSAlan Cox PSB_WVDC32(0, DSPASURF);
2141b082ccfSAlan Cox
2151b082ccfSAlan Cox /* Wait ~4 ticks */
2161b082ccfSAlan Cox msleep(4);
2171b082ccfSAlan Cox
2181b082ccfSAlan Cox /* Turn off pipe */
2191b082ccfSAlan Cox PSB_WVDC32(0x0, PIPEACONF);
2201b082ccfSAlan Cox /* Wait ~8 ticks */
2211b082ccfSAlan Cox msleep(8);
2221b082ccfSAlan Cox
2231b082ccfSAlan Cox /* Turn off PLLs */
2241b082ccfSAlan Cox PSB_WVDC32(0, MRST_DPLL_A);
2251b082ccfSAlan Cox }
2261b082ccfSAlan Cox return 0;
2271b082ccfSAlan Cox }
2281b082ccfSAlan Cox
2291b082ccfSAlan Cox /**
2301b082ccfSAlan Cox * oaktrail_restore_display_registers - restore lost register state
2311b082ccfSAlan Cox * @dev: our DRM device
2321b082ccfSAlan Cox *
2331b082ccfSAlan Cox * Restore register state that was lost during suspend and resume.
2341b082ccfSAlan Cox */
oaktrail_restore_display_registers(struct drm_device * dev)2351b082ccfSAlan Cox static int oaktrail_restore_display_registers(struct drm_device *dev)
2361b082ccfSAlan Cox {
237f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
238c6265ff5SAlan Cox struct psb_save_area *regs = &dev_priv->regs;
2396256304bSAlan Cox struct psb_pipe *p = ®s->pipe[0];
2401b082ccfSAlan Cox u32 pp_stat;
2411b082ccfSAlan Cox int i;
2421b082ccfSAlan Cox
2431b082ccfSAlan Cox /* Display arbitration + watermarks */
244c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
245c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
246c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
247c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
248c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
249c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
250c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
251c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
2521b082ccfSAlan Cox
2531b082ccfSAlan Cox /* Make sure VGA plane is off. it initializes to on after reset!*/
2541b082ccfSAlan Cox PSB_WVDC32(0x80000000, VGACNTRL);
2551b082ccfSAlan Cox
2561b082ccfSAlan Cox /* set the plls */
2576256304bSAlan Cox PSB_WVDC32(p->fp0, MRST_FPA0);
2586256304bSAlan Cox PSB_WVDC32(p->fp1, MRST_FPA1);
2591b082ccfSAlan Cox
2601b082ccfSAlan Cox /* Actually enable it */
2616256304bSAlan Cox PSB_WVDC32(p->dpll, MRST_DPLL_A);
262bc9f1007SSam Ravnborg udelay(150);
2631b082ccfSAlan Cox
2641b082ccfSAlan Cox /* Restore mode */
2656256304bSAlan Cox PSB_WVDC32(p->htotal, HTOTAL_A);
2666256304bSAlan Cox PSB_WVDC32(p->hblank, HBLANK_A);
2676256304bSAlan Cox PSB_WVDC32(p->hsync, HSYNC_A);
2686256304bSAlan Cox PSB_WVDC32(p->vtotal, VTOTAL_A);
2696256304bSAlan Cox PSB_WVDC32(p->vblank, VBLANK_A);
2706256304bSAlan Cox PSB_WVDC32(p->vsync, VSYNC_A);
2716256304bSAlan Cox PSB_WVDC32(p->src, PIPEASRC);
272c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
2731b082ccfSAlan Cox
2741b082ccfSAlan Cox /* Restore performance mode*/
275c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
2761b082ccfSAlan Cox
2771b082ccfSAlan Cox /* Enable the pipe*/
2781b082ccfSAlan Cox if (dev_priv->iLVDS_enable)
2796256304bSAlan Cox PSB_WVDC32(p->conf, PIPEACONF);
2801b082ccfSAlan Cox
2811b082ccfSAlan Cox /* Set up the plane*/
2826256304bSAlan Cox PSB_WVDC32(p->linoff, DSPALINOFF);
2836256304bSAlan Cox PSB_WVDC32(p->stride, DSPASTRIDE);
2846256304bSAlan Cox PSB_WVDC32(p->tileoff, DSPATILEOFF);
2851b082ccfSAlan Cox
2861b082ccfSAlan Cox /* Enable the plane */
2876256304bSAlan Cox PSB_WVDC32(p->cntr, DSPACNTR);
2886256304bSAlan Cox PSB_WVDC32(p->surf, DSPASURF);
2891b082ccfSAlan Cox
2901b082ccfSAlan Cox /* Enable Cursor A */
291c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
292c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
293c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
2941b082ccfSAlan Cox
2951b082ccfSAlan Cox /* Restore palette (gamma) */
2961b082ccfSAlan Cox for (i = 0; i < 256; i++)
2976256304bSAlan Cox PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
2981b082ccfSAlan Cox
2991b082ccfSAlan Cox if (dev_priv->hdmi_priv)
3001b082ccfSAlan Cox oaktrail_hdmi_restore(dev);
3011b082ccfSAlan Cox
3021b082ccfSAlan Cox if (dev_priv->iLVDS_enable) {
303648a8e34SAlan Cox PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
304c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
305c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
306c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
307c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
308648a8e34SAlan Cox PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
309c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
310c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
311c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
312c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
3131b082ccfSAlan Cox }
3141b082ccfSAlan Cox
3151b082ccfSAlan Cox /* Wait for cycle delay */
3161b082ccfSAlan Cox do {
3171b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS);
3181b082ccfSAlan Cox } while (pp_stat & 0x08000000);
3191b082ccfSAlan Cox
3201b082ccfSAlan Cox /* Wait for panel power up */
3211b082ccfSAlan Cox do {
3221b082ccfSAlan Cox pp_stat = PSB_RVDC32(PP_STATUS);
3231b082ccfSAlan Cox } while (pp_stat & 0x10000000);
3241b082ccfSAlan Cox
3251b082ccfSAlan Cox /* Restore HW overlay */
326c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
327c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
328c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
329c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
330c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
331c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
332c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
3331b082ccfSAlan Cox
3341b082ccfSAlan Cox /* DPST registers */
335c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
3361b082ccfSAlan Cox HISTOGRAM_INT_CONTROL);
337c6265ff5SAlan Cox PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
3381b082ccfSAlan Cox HISTOGRAM_LOGIC_CONTROL);
339c6265ff5SAlan Cox PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
3401b082ccfSAlan Cox
3411b082ccfSAlan Cox return 0;
3421b082ccfSAlan Cox }
3431b082ccfSAlan Cox
3441b082ccfSAlan Cox /**
3451b082ccfSAlan Cox * oaktrail_power_down - power down the display island
3461b082ccfSAlan Cox * @dev: our DRM device
3471b082ccfSAlan Cox *
3481b082ccfSAlan Cox * Power down the display interface of our device
3491b082ccfSAlan Cox */
oaktrail_power_down(struct drm_device * dev)3501b082ccfSAlan Cox static int oaktrail_power_down(struct drm_device *dev)
3511b082ccfSAlan Cox {
352f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
3531b082ccfSAlan Cox u32 pwr_mask ;
3541b082ccfSAlan Cox u32 pwr_sts;
3551b082ccfSAlan Cox
3561b082ccfSAlan Cox pwr_mask = PSB_PWRGT_DISPLAY_MASK;
3571b082ccfSAlan Cox outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
3581b082ccfSAlan Cox
3591b082ccfSAlan Cox while (true) {
3601b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
3611b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == pwr_mask)
3621b082ccfSAlan Cox break;
3631b082ccfSAlan Cox else
3641b082ccfSAlan Cox udelay(10);
3651b082ccfSAlan Cox }
3661b082ccfSAlan Cox return 0;
3671b082ccfSAlan Cox }
3681b082ccfSAlan Cox
3691b082ccfSAlan Cox /*
3701b082ccfSAlan Cox * oaktrail_power_up
3711b082ccfSAlan Cox *
3721b082ccfSAlan Cox * Restore power to the specified island(s) (powergating)
3731b082ccfSAlan Cox */
oaktrail_power_up(struct drm_device * dev)3741b082ccfSAlan Cox static int oaktrail_power_up(struct drm_device *dev)
3751b082ccfSAlan Cox {
376f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
3771b082ccfSAlan Cox u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
3781b082ccfSAlan Cox u32 pwr_sts, pwr_cnt;
3791b082ccfSAlan Cox
3801b082ccfSAlan Cox pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
3811b082ccfSAlan Cox pwr_cnt &= ~pwr_mask;
3821b082ccfSAlan Cox outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
3831b082ccfSAlan Cox
3841b082ccfSAlan Cox while (true) {
3851b082ccfSAlan Cox pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
3861b082ccfSAlan Cox if ((pwr_sts & pwr_mask) == 0)
3871b082ccfSAlan Cox break;
3881b082ccfSAlan Cox else
3891b082ccfSAlan Cox udelay(10);
3901b082ccfSAlan Cox }
3911b082ccfSAlan Cox return 0;
3921b082ccfSAlan Cox }
3931b082ccfSAlan Cox
3948512e074SAlan Cox /* Oaktrail */
3958512e074SAlan Cox static const struct psb_offset oaktrail_regmap[2] = {
3968512e074SAlan Cox {
3978512e074SAlan Cox .fp0 = MRST_FPA0,
3988512e074SAlan Cox .fp1 = MRST_FPA1,
3998512e074SAlan Cox .cntr = DSPACNTR,
4008512e074SAlan Cox .conf = PIPEACONF,
4018512e074SAlan Cox .src = PIPEASRC,
4028512e074SAlan Cox .dpll = MRST_DPLL_A,
4038512e074SAlan Cox .htotal = HTOTAL_A,
4048512e074SAlan Cox .hblank = HBLANK_A,
4058512e074SAlan Cox .hsync = HSYNC_A,
4068512e074SAlan Cox .vtotal = VTOTAL_A,
4078512e074SAlan Cox .vblank = VBLANK_A,
4088512e074SAlan Cox .vsync = VSYNC_A,
4098512e074SAlan Cox .stride = DSPASTRIDE,
4108512e074SAlan Cox .size = DSPASIZE,
4118512e074SAlan Cox .pos = DSPAPOS,
4128512e074SAlan Cox .surf = DSPASURF,
413213a8434SAlan Cox .addr = MRST_DSPABASE,
41426df641eSAlan Cox .base = MRST_DSPABASE,
4158512e074SAlan Cox .status = PIPEASTAT,
4168512e074SAlan Cox .linoff = DSPALINOFF,
4178512e074SAlan Cox .tileoff = DSPATILEOFF,
4188512e074SAlan Cox .palette = PALETTE_A,
4198512e074SAlan Cox },
4208512e074SAlan Cox {
4218512e074SAlan Cox .fp0 = FPB0,
4228512e074SAlan Cox .fp1 = FPB1,
4238512e074SAlan Cox .cntr = DSPBCNTR,
4248512e074SAlan Cox .conf = PIPEBCONF,
4258512e074SAlan Cox .src = PIPEBSRC,
4268512e074SAlan Cox .dpll = DPLL_B,
4278512e074SAlan Cox .htotal = HTOTAL_B,
4288512e074SAlan Cox .hblank = HBLANK_B,
4298512e074SAlan Cox .hsync = HSYNC_B,
4308512e074SAlan Cox .vtotal = VTOTAL_B,
4318512e074SAlan Cox .vblank = VBLANK_B,
4328512e074SAlan Cox .vsync = VSYNC_B,
4338512e074SAlan Cox .stride = DSPBSTRIDE,
4348512e074SAlan Cox .size = DSPBSIZE,
4358512e074SAlan Cox .pos = DSPBPOS,
4368512e074SAlan Cox .surf = DSPBSURF,
4378512e074SAlan Cox .addr = DSPBBASE,
43826df641eSAlan Cox .base = DSPBBASE,
4398512e074SAlan Cox .status = PIPEBSTAT,
4408512e074SAlan Cox .linoff = DSPBLINOFF,
4418512e074SAlan Cox .tileoff = DSPBTILEOFF,
4428512e074SAlan Cox .palette = PALETTE_B,
4438512e074SAlan Cox },
4448512e074SAlan Cox };
4451b082ccfSAlan Cox
oaktrail_chip_setup(struct drm_device * dev)4461b22edfdSAlan Cox static int oaktrail_chip_setup(struct drm_device *dev)
447aa0c45fdSAlan Cox {
448f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
4491b22edfdSAlan Cox int ret;
4501b22edfdSAlan Cox
4519b6a1657SHans de Goede dev_priv->use_msi = true;
4528512e074SAlan Cox dev_priv->regmap = oaktrail_regmap;
4538512e074SAlan Cox
4541b22edfdSAlan Cox ret = mid_chip_setup(dev);
455aa0c45fdSAlan Cox if (ret < 0)
456aa0c45fdSAlan Cox return ret;
4574086b1e2SKirill A. Shutemov if (!dev_priv->has_gct) {
458aa0c45fdSAlan Cox /* Now pull the BIOS data */
459d839ede4SAlan Cox psb_intel_opregion_init(dev);
460aa0c45fdSAlan Cox psb_intel_init_bios(dev);
461aa0c45fdSAlan Cox }
4626528c897SPatrik Jakobsson gma_intel_setup_gmbus(dev);
4635f503148SAlan Cox oaktrail_hdmi_setup(dev);
464aa0c45fdSAlan Cox return 0;
465aa0c45fdSAlan Cox }
466aa0c45fdSAlan Cox
oaktrail_teardown(struct drm_device * dev)4671b082ccfSAlan Cox static void oaktrail_teardown(struct drm_device *dev)
4681b082ccfSAlan Cox {
469f71635e8SThomas Zimmermann struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
4701b22edfdSAlan Cox
4716528c897SPatrik Jakobsson gma_intel_teardown_gmbus(dev);
4721b082ccfSAlan Cox oaktrail_hdmi_teardown(dev);
4734086b1e2SKirill A. Shutemov if (!dev_priv->has_gct)
474aa0c45fdSAlan Cox psb_intel_destroy_bios(dev);
4751b082ccfSAlan Cox }
4761b082ccfSAlan Cox
4771b082ccfSAlan Cox const struct psb_ops oaktrail_chip_ops = {
4781b082ccfSAlan Cox .name = "Oaktrail",
4791b082ccfSAlan Cox .pipes = 2,
4801b082ccfSAlan Cox .crtcs = 2,
48139ec748fSAlan Cox .hdmi_mask = (1 << 1),
482d235e64aSAlan Cox .lvds_mask = (1 << 0),
483cf8efd3aSPatrik Jakobsson .sdvo_mask = (1 << 1),
484bc794829SPatrik Jakobsson .cursor_needs_phys = 0,
4851b082ccfSAlan Cox .sgx_offset = MRST_SGX_OFFSET,
4861b082ccfSAlan Cox
487aa0c45fdSAlan Cox .chip_setup = oaktrail_chip_setup,
4881b082ccfSAlan Cox .chip_teardown = oaktrail_teardown,
4891b082ccfSAlan Cox .crtc_helper = &oaktrail_helper_funcs,
4901b082ccfSAlan Cox
4911b082ccfSAlan Cox .output_init = oaktrail_output_init,
4921b082ccfSAlan Cox
4931b082ccfSAlan Cox .backlight_init = oaktrail_backlight_init,
494*1f90b123SHans de Goede .backlight_set = oaktrail_set_brightness,
495*1f90b123SHans de Goede .backlight_name = "oaktrail-bl",
4961b082ccfSAlan Cox
4971b082ccfSAlan Cox .save_regs = oaktrail_save_display_registers,
4981b082ccfSAlan Cox .restore_regs = oaktrail_restore_display_registers,
499d56f57acSDaniel Vetter .save_crtc = gma_crtc_save,
500d56f57acSDaniel Vetter .restore_crtc = gma_crtc_restore,
5011b082ccfSAlan Cox .power_down = oaktrail_power_down,
5021b082ccfSAlan Cox .power_up = oaktrail_power_up,
5031b082ccfSAlan Cox
5041b082ccfSAlan Cox .i2c_bus = 1,
5051b082ccfSAlan Cox };
506