1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright © 2009 Intel Corporation 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/i2c.h> 8 #include <linux/pm_runtime.h> 9 10 #include <drm/drm_fourcc.h> 11 12 #include "framebuffer.h" 13 #include "gma_display.h" 14 #include "power.h" 15 #include "psb_drv.h" 16 #include "psb_intel_drv.h" 17 #include "psb_intel_reg.h" 18 19 #define MRST_LIMIT_LVDS_100L 0 20 #define MRST_LIMIT_LVDS_83 1 21 #define MRST_LIMIT_LVDS_100 2 22 #define MRST_LIMIT_SDVO 3 23 24 #define MRST_DOT_MIN 19750 25 #define MRST_DOT_MAX 120000 26 #define MRST_M_MIN_100L 20 27 #define MRST_M_MIN_100 10 28 #define MRST_M_MIN_83 12 29 #define MRST_M_MAX_100L 34 30 #define MRST_M_MAX_100 17 31 #define MRST_M_MAX_83 20 32 #define MRST_P1_MIN 2 33 #define MRST_P1_MAX_0 7 34 #define MRST_P1_MAX_1 8 35 36 static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, 37 struct drm_crtc *crtc, int target, 38 int refclk, struct gma_clock_t *best_clock); 39 40 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, 41 struct drm_crtc *crtc, int target, 42 int refclk, struct gma_clock_t *best_clock); 43 44 static const struct gma_limit_t mrst_limits[] = { 45 { /* MRST_LIMIT_LVDS_100L */ 46 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, 47 .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L}, 48 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, 49 .find_pll = mrst_lvds_find_best_pll, 50 }, 51 { /* MRST_LIMIT_LVDS_83L */ 52 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, 53 .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83}, 54 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0}, 55 .find_pll = mrst_lvds_find_best_pll, 56 }, 57 { /* MRST_LIMIT_LVDS_100 */ 58 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, 59 .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100}, 60 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, 61 .find_pll = mrst_lvds_find_best_pll, 62 }, 63 { /* MRST_LIMIT_SDVO */ 64 .vco = {.min = 1400000, .max = 2800000}, 65 .n = {.min = 3, .max = 7}, 66 .m = {.min = 80, .max = 137}, 67 .p1 = {.min = 1, .max = 2}, 68 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10}, 69 .find_pll = mrst_sdvo_find_best_pll, 70 }, 71 }; 72 73 #define MRST_M_MIN 10 74 static const u32 oaktrail_m_converts[] = { 75 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C, 76 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25, 77 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c, 78 }; 79 80 static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc, 81 int refclk) 82 { 83 const struct gma_limit_t *limit = NULL; 84 struct drm_device *dev = crtc->dev; 85 struct drm_psb_private *dev_priv = dev->dev_private; 86 87 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 88 || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { 89 switch (dev_priv->core_freq) { 90 case 100: 91 limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; 92 break; 93 case 166: 94 limit = &mrst_limits[MRST_LIMIT_LVDS_83]; 95 break; 96 case 200: 97 limit = &mrst_limits[MRST_LIMIT_LVDS_100]; 98 break; 99 } 100 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 101 limit = &mrst_limits[MRST_LIMIT_SDVO]; 102 } else { 103 limit = NULL; 104 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); 105 } 106 107 return limit; 108 } 109 110 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 111 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) 112 { 113 clock->dot = (refclk * clock->m) / (14 * clock->p1); 114 } 115 116 static void mrst_print_pll(struct gma_clock_t *clock) 117 { 118 DRM_DEBUG_DRIVER("dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n", 119 clock->dot, clock->m, clock->m1, clock->m2, clock->n, 120 clock->p1, clock->p2); 121 } 122 123 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, 124 struct drm_crtc *crtc, int target, 125 int refclk, struct gma_clock_t *best_clock) 126 { 127 struct gma_clock_t clock; 128 u32 target_vco, actual_freq; 129 s32 freq_error, min_error = 100000; 130 131 memset(best_clock, 0, sizeof(*best_clock)); 132 133 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { 134 for (clock.n = limit->n.min; clock.n <= limit->n.max; 135 clock.n++) { 136 for (clock.p1 = limit->p1.min; 137 clock.p1 <= limit->p1.max; clock.p1++) { 138 /* p2 value always stored in p2_slow on SDVO */ 139 clock.p = clock.p1 * limit->p2.p2_slow; 140 target_vco = target * clock.p; 141 142 /* VCO will increase at this point so break */ 143 if (target_vco > limit->vco.max) 144 break; 145 146 if (target_vco < limit->vco.min) 147 continue; 148 149 actual_freq = (refclk * clock.m) / 150 (clock.n * clock.p); 151 freq_error = 10000 - 152 ((target * 10000) / actual_freq); 153 154 if (freq_error < -min_error) { 155 /* freq_error will start to decrease at 156 this point so break */ 157 break; 158 } 159 160 if (freq_error < 0) 161 freq_error = -freq_error; 162 163 if (freq_error < min_error) { 164 min_error = freq_error; 165 *best_clock = clock; 166 } 167 } 168 } 169 if (min_error == 0) 170 break; 171 } 172 173 return min_error == 0; 174 } 175 176 /** 177 * Returns a set of divisors for the desired target clock with the given refclk, 178 * or FALSE. Divisor values are the actual divisors for 179 */ 180 static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, 181 struct drm_crtc *crtc, int target, 182 int refclk, struct gma_clock_t *best_clock) 183 { 184 struct gma_clock_t clock; 185 int err = target; 186 187 memset(best_clock, 0, sizeof(*best_clock)); 188 189 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { 190 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; 191 clock.p1++) { 192 int this_err; 193 194 mrst_lvds_clock(refclk, &clock); 195 196 this_err = abs(clock.dot - target); 197 if (this_err < err) { 198 *best_clock = clock; 199 err = this_err; 200 } 201 } 202 } 203 return err != target; 204 } 205 206 /** 207 * Sets the power management mode of the pipe and plane. 208 * 209 * This code should probably grow support for turning the cursor off and back 210 * on appropriately at the same time as we're turning the pipe off/on. 211 */ 212 static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) 213 { 214 struct drm_device *dev = crtc->dev; 215 struct drm_psb_private *dev_priv = dev->dev_private; 216 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 217 int pipe = gma_crtc->pipe; 218 const struct psb_offset *map = &dev_priv->regmap[pipe]; 219 u32 temp; 220 int i; 221 int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0; 222 223 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { 224 oaktrail_crtc_hdmi_dpms(crtc, mode); 225 return; 226 } 227 228 if (!gma_power_begin(dev, true)) 229 return; 230 231 /* XXX: When our outputs are all unaware of DPMS modes other than off 232 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 233 */ 234 switch (mode) { 235 case DRM_MODE_DPMS_ON: 236 case DRM_MODE_DPMS_STANDBY: 237 case DRM_MODE_DPMS_SUSPEND: 238 for (i = 0; i <= need_aux; i++) { 239 /* Enable the DPLL */ 240 temp = REG_READ_WITH_AUX(map->dpll, i); 241 if ((temp & DPLL_VCO_ENABLE) == 0) { 242 REG_WRITE_WITH_AUX(map->dpll, temp, i); 243 REG_READ_WITH_AUX(map->dpll, i); 244 /* Wait for the clocks to stabilize. */ 245 udelay(150); 246 REG_WRITE_WITH_AUX(map->dpll, 247 temp | DPLL_VCO_ENABLE, i); 248 REG_READ_WITH_AUX(map->dpll, i); 249 /* Wait for the clocks to stabilize. */ 250 udelay(150); 251 REG_WRITE_WITH_AUX(map->dpll, 252 temp | DPLL_VCO_ENABLE, i); 253 REG_READ_WITH_AUX(map->dpll, i); 254 /* Wait for the clocks to stabilize. */ 255 udelay(150); 256 } 257 258 /* Enable the pipe */ 259 temp = REG_READ_WITH_AUX(map->conf, i); 260 if ((temp & PIPEACONF_ENABLE) == 0) { 261 REG_WRITE_WITH_AUX(map->conf, 262 temp | PIPEACONF_ENABLE, i); 263 } 264 265 /* Enable the plane */ 266 temp = REG_READ_WITH_AUX(map->cntr, i); 267 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 268 REG_WRITE_WITH_AUX(map->cntr, 269 temp | DISPLAY_PLANE_ENABLE, 270 i); 271 /* Flush the plane changes */ 272 REG_WRITE_WITH_AUX(map->base, 273 REG_READ_WITH_AUX(map->base, i), i); 274 } 275 276 } 277 gma_crtc_load_lut(crtc); 278 279 /* Give the overlay scaler a chance to enable 280 if it's on this pipe */ 281 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 282 break; 283 case DRM_MODE_DPMS_OFF: 284 /* Give the overlay scaler a chance to disable 285 * if it's on this pipe */ 286 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 287 288 for (i = 0; i <= need_aux; i++) { 289 /* Disable the VGA plane that we never use */ 290 REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i); 291 /* Disable display plane */ 292 temp = REG_READ_WITH_AUX(map->cntr, i); 293 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 294 REG_WRITE_WITH_AUX(map->cntr, 295 temp & ~DISPLAY_PLANE_ENABLE, i); 296 /* Flush the plane changes */ 297 REG_WRITE_WITH_AUX(map->base, 298 REG_READ(map->base), i); 299 REG_READ_WITH_AUX(map->base, i); 300 } 301 302 /* Next, disable display pipes */ 303 temp = REG_READ_WITH_AUX(map->conf, i); 304 if ((temp & PIPEACONF_ENABLE) != 0) { 305 REG_WRITE_WITH_AUX(map->conf, 306 temp & ~PIPEACONF_ENABLE, i); 307 REG_READ_WITH_AUX(map->conf, i); 308 } 309 /* Wait for for the pipe disable to take effect. */ 310 gma_wait_for_vblank(dev); 311 312 temp = REG_READ_WITH_AUX(map->dpll, i); 313 if ((temp & DPLL_VCO_ENABLE) != 0) { 314 REG_WRITE_WITH_AUX(map->dpll, 315 temp & ~DPLL_VCO_ENABLE, i); 316 REG_READ_WITH_AUX(map->dpll, i); 317 } 318 319 /* Wait for the clocks to turn off. */ 320 udelay(150); 321 } 322 break; 323 } 324 325 /* Set FIFO Watermarks (values taken from EMGD) */ 326 REG_WRITE(DSPARB, 0x3f80); 327 REG_WRITE(DSPFW1, 0x3f8f0404); 328 REG_WRITE(DSPFW2, 0x04040f04); 329 REG_WRITE(DSPFW3, 0x0); 330 REG_WRITE(DSPFW4, 0x04040404); 331 REG_WRITE(DSPFW5, 0x04040404); 332 REG_WRITE(DSPFW6, 0x78); 333 REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); 334 335 gma_power_end(dev); 336 } 337 338 /** 339 * Return the pipe currently connected to the panel fitter, 340 * or -1 if the panel fitter is not present or not in use 341 */ 342 static int oaktrail_panel_fitter_pipe(struct drm_device *dev) 343 { 344 u32 pfit_control; 345 346 pfit_control = REG_READ(PFIT_CONTROL); 347 348 /* See if the panel fitter is in use */ 349 if ((pfit_control & PFIT_ENABLE) == 0) 350 return -1; 351 return (pfit_control >> 29) & 3; 352 } 353 354 static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, 355 struct drm_display_mode *mode, 356 struct drm_display_mode *adjusted_mode, 357 int x, int y, 358 struct drm_framebuffer *old_fb) 359 { 360 struct drm_device *dev = crtc->dev; 361 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 362 struct drm_psb_private *dev_priv = dev->dev_private; 363 int pipe = gma_crtc->pipe; 364 const struct psb_offset *map = &dev_priv->regmap[pipe]; 365 int refclk = 0; 366 struct gma_clock_t clock; 367 const struct gma_limit_t *limit; 368 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 369 bool ok, is_sdvo = false; 370 bool is_lvds = false; 371 bool is_mipi = false; 372 struct drm_mode_config *mode_config = &dev->mode_config; 373 struct gma_encoder *gma_encoder = NULL; 374 uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; 375 struct drm_connector *connector; 376 int i; 377 int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0; 378 379 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 380 return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb); 381 382 if (!gma_power_begin(dev, true)) 383 return 0; 384 385 memcpy(&gma_crtc->saved_mode, 386 mode, 387 sizeof(struct drm_display_mode)); 388 memcpy(&gma_crtc->saved_adjusted_mode, 389 adjusted_mode, 390 sizeof(struct drm_display_mode)); 391 392 list_for_each_entry(connector, &mode_config->connector_list, head) { 393 if (!connector->encoder || connector->encoder->crtc != crtc) 394 continue; 395 396 gma_encoder = gma_attached_encoder(connector); 397 398 switch (gma_encoder->type) { 399 case INTEL_OUTPUT_LVDS: 400 is_lvds = true; 401 break; 402 case INTEL_OUTPUT_SDVO: 403 is_sdvo = true; 404 break; 405 case INTEL_OUTPUT_MIPI: 406 is_mipi = true; 407 break; 408 } 409 } 410 411 /* Disable the VGA plane that we never use */ 412 for (i = 0; i <= need_aux; i++) 413 REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i); 414 415 /* Disable the panel fitter if it was on our pipe */ 416 if (oaktrail_panel_fitter_pipe(dev) == pipe) 417 REG_WRITE(PFIT_CONTROL, 0); 418 419 for (i = 0; i <= need_aux; i++) { 420 REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) | 421 (mode->crtc_vdisplay - 1), i); 422 } 423 424 if (gma_encoder) 425 drm_object_property_get_value(&connector->base, 426 dev->mode_config.scaling_mode_property, &scalingType); 427 428 if (scalingType == DRM_MODE_SCALE_NO_SCALE) { 429 /* Moorestown doesn't have register support for centering so 430 * we need to mess with the h/vblank and h/vsync start and 431 * ends to get centering */ 432 int offsetX = 0, offsetY = 0; 433 434 offsetX = (adjusted_mode->crtc_hdisplay - 435 mode->crtc_hdisplay) / 2; 436 offsetY = (adjusted_mode->crtc_vdisplay - 437 mode->crtc_vdisplay) / 2; 438 439 for (i = 0; i <= need_aux; i++) { 440 REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) | 441 ((adjusted_mode->crtc_htotal - 1) << 16), i); 442 REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) | 443 ((adjusted_mode->crtc_vtotal - 1) << 16), i); 444 REG_WRITE_WITH_AUX(map->hblank, 445 (adjusted_mode->crtc_hblank_start - offsetX - 1) | 446 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i); 447 REG_WRITE_WITH_AUX(map->hsync, 448 (adjusted_mode->crtc_hsync_start - offsetX - 1) | 449 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i); 450 REG_WRITE_WITH_AUX(map->vblank, 451 (adjusted_mode->crtc_vblank_start - offsetY - 1) | 452 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i); 453 REG_WRITE_WITH_AUX(map->vsync, 454 (adjusted_mode->crtc_vsync_start - offsetY - 1) | 455 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i); 456 } 457 } else { 458 for (i = 0; i <= need_aux; i++) { 459 REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 460 ((adjusted_mode->crtc_htotal - 1) << 16), i); 461 REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 462 ((adjusted_mode->crtc_vtotal - 1) << 16), i); 463 REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 464 ((adjusted_mode->crtc_hblank_end - 1) << 16), i); 465 REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 466 ((adjusted_mode->crtc_hsync_end - 1) << 16), i); 467 REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 468 ((adjusted_mode->crtc_vblank_end - 1) << 16), i); 469 REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 470 ((adjusted_mode->crtc_vsync_end - 1) << 16), i); 471 } 472 } 473 474 /* Flush the plane changes */ 475 { 476 const struct drm_crtc_helper_funcs *crtc_funcs = 477 crtc->helper_private; 478 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 479 } 480 481 /* setup pipeconf */ 482 pipeconf = REG_READ(map->conf); 483 484 /* Set up the display plane register */ 485 dspcntr = REG_READ(map->cntr); 486 dspcntr |= DISPPLANE_GAMMA_ENABLE; 487 488 if (pipe == 0) 489 dspcntr |= DISPPLANE_SEL_PIPE_A; 490 else 491 dspcntr |= DISPPLANE_SEL_PIPE_B; 492 493 if (is_mipi) 494 goto oaktrail_crtc_mode_set_exit; 495 496 497 dpll = 0; /*BIT16 = 0 for 100MHz reference */ 498 499 refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; 500 limit = mrst_limit(crtc, refclk); 501 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, 502 refclk, &clock); 503 504 if (is_sdvo) { 505 /* Convert calculated values to register values */ 506 clock.p1 = (1L << (clock.p1 - 1)); 507 clock.m -= 2; 508 clock.n = (1L << (clock.n - 1)); 509 } 510 511 if (!ok) 512 DRM_ERROR("Failed to find proper PLL settings"); 513 514 mrst_print_pll(&clock); 515 516 if (is_sdvo) 517 fp = clock.n << 16 | clock.m; 518 else 519 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; 520 521 dpll |= DPLL_VGA_MODE_DIS; 522 523 524 dpll |= DPLL_VCO_ENABLE; 525 526 if (is_lvds) 527 dpll |= DPLLA_MODE_LVDS; 528 else 529 dpll |= DPLLB_MODE_DAC_SERIAL; 530 531 if (is_sdvo) { 532 int sdvo_pixel_multiply = 533 adjusted_mode->clock / mode->clock; 534 535 dpll |= DPLL_DVO_HIGH_SPEED; 536 dpll |= 537 (sdvo_pixel_multiply - 538 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 539 } 540 541 542 /* compute bitmask from p1 value */ 543 if (is_sdvo) 544 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; 545 else 546 dpll |= (1 << (clock.p1 - 2)) << 17; 547 548 dpll |= DPLL_VCO_ENABLE; 549 550 if (dpll & DPLL_VCO_ENABLE) { 551 for (i = 0; i <= need_aux; i++) { 552 REG_WRITE_WITH_AUX(map->fp0, fp, i); 553 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); 554 REG_READ_WITH_AUX(map->dpll, i); 555 /* Check the DPLLA lock bit PIPEACONF[29] */ 556 udelay(150); 557 } 558 } 559 560 for (i = 0; i <= need_aux; i++) { 561 REG_WRITE_WITH_AUX(map->fp0, fp, i); 562 REG_WRITE_WITH_AUX(map->dpll, dpll, i); 563 REG_READ_WITH_AUX(map->dpll, i); 564 /* Wait for the clocks to stabilize. */ 565 udelay(150); 566 567 /* write it again -- the BIOS does, after all */ 568 REG_WRITE_WITH_AUX(map->dpll, dpll, i); 569 REG_READ_WITH_AUX(map->dpll, i); 570 /* Wait for the clocks to stabilize. */ 571 udelay(150); 572 573 REG_WRITE_WITH_AUX(map->conf, pipeconf, i); 574 REG_READ_WITH_AUX(map->conf, i); 575 gma_wait_for_vblank(dev); 576 577 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); 578 gma_wait_for_vblank(dev); 579 } 580 581 oaktrail_crtc_mode_set_exit: 582 gma_power_end(dev); 583 return 0; 584 } 585 586 static int oaktrail_pipe_set_base(struct drm_crtc *crtc, 587 int x, int y, struct drm_framebuffer *old_fb) 588 { 589 struct drm_device *dev = crtc->dev; 590 struct drm_psb_private *dev_priv = dev->dev_private; 591 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 592 struct drm_framebuffer *fb = crtc->primary->fb; 593 int pipe = gma_crtc->pipe; 594 const struct psb_offset *map = &dev_priv->regmap[pipe]; 595 unsigned long start, offset; 596 597 u32 dspcntr; 598 int ret = 0; 599 600 /* no fb bound */ 601 if (!fb) { 602 dev_dbg(dev->dev, "No FB bound\n"); 603 return 0; 604 } 605 606 if (!gma_power_begin(dev, true)) 607 return 0; 608 609 start = to_gtt_range(fb->obj[0])->offset; 610 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; 611 612 REG_WRITE(map->stride, fb->pitches[0]); 613 614 dspcntr = REG_READ(map->cntr); 615 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 616 617 switch (fb->format->cpp[0] * 8) { 618 case 8: 619 dspcntr |= DISPPLANE_8BPP; 620 break; 621 case 16: 622 if (fb->format->depth == 15) 623 dspcntr |= DISPPLANE_15_16BPP; 624 else 625 dspcntr |= DISPPLANE_16BPP; 626 break; 627 case 24: 628 case 32: 629 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 630 break; 631 default: 632 dev_err(dev->dev, "Unknown color depth\n"); 633 ret = -EINVAL; 634 goto pipe_set_base_exit; 635 } 636 REG_WRITE(map->cntr, dspcntr); 637 638 REG_WRITE(map->base, offset); 639 REG_READ(map->base); 640 REG_WRITE(map->surf, start); 641 REG_READ(map->surf); 642 643 pipe_set_base_exit: 644 gma_power_end(dev); 645 return ret; 646 } 647 648 const struct drm_crtc_helper_funcs oaktrail_helper_funcs = { 649 .dpms = oaktrail_crtc_dpms, 650 .mode_set = oaktrail_crtc_mode_set, 651 .mode_set_base = oaktrail_pipe_set_base, 652 .prepare = gma_crtc_prepare, 653 .commit = gma_crtc_commit, 654 }; 655 656 /* Not used yet */ 657 const struct gma_clock_funcs mrst_clock_funcs = { 658 .clock = mrst_lvds_clock, 659 .limit = mrst_limit, 660 .pll_is_valid = gma_pll_is_valid, 661 }; 662