1 /* 2 * Copyright © 2009 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 */ 17 18 #include <linux/delay.h> 19 #include <linux/i2c.h> 20 #include <linux/pm_runtime.h> 21 22 #include <drm/drm_fourcc.h> 23 24 #include "framebuffer.h" 25 #include "gma_display.h" 26 #include "power.h" 27 #include "psb_drv.h" 28 #include "psb_intel_drv.h" 29 #include "psb_intel_reg.h" 30 31 #define MRST_LIMIT_LVDS_100L 0 32 #define MRST_LIMIT_LVDS_83 1 33 #define MRST_LIMIT_LVDS_100 2 34 #define MRST_LIMIT_SDVO 3 35 36 #define MRST_DOT_MIN 19750 37 #define MRST_DOT_MAX 120000 38 #define MRST_M_MIN_100L 20 39 #define MRST_M_MIN_100 10 40 #define MRST_M_MIN_83 12 41 #define MRST_M_MAX_100L 34 42 #define MRST_M_MAX_100 17 43 #define MRST_M_MAX_83 20 44 #define MRST_P1_MIN 2 45 #define MRST_P1_MAX_0 7 46 #define MRST_P1_MAX_1 8 47 48 static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, 49 struct drm_crtc *crtc, int target, 50 int refclk, struct gma_clock_t *best_clock); 51 52 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, 53 struct drm_crtc *crtc, int target, 54 int refclk, struct gma_clock_t *best_clock); 55 56 static const struct gma_limit_t mrst_limits[] = { 57 { /* MRST_LIMIT_LVDS_100L */ 58 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, 59 .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L}, 60 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, 61 .find_pll = mrst_lvds_find_best_pll, 62 }, 63 { /* MRST_LIMIT_LVDS_83L */ 64 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, 65 .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83}, 66 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0}, 67 .find_pll = mrst_lvds_find_best_pll, 68 }, 69 { /* MRST_LIMIT_LVDS_100 */ 70 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, 71 .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100}, 72 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, 73 .find_pll = mrst_lvds_find_best_pll, 74 }, 75 { /* MRST_LIMIT_SDVO */ 76 .vco = {.min = 1400000, .max = 2800000}, 77 .n = {.min = 3, .max = 7}, 78 .m = {.min = 80, .max = 137}, 79 .p1 = {.min = 1, .max = 2}, 80 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 10}, 81 .find_pll = mrst_sdvo_find_best_pll, 82 }, 83 }; 84 85 #define MRST_M_MIN 10 86 static const u32 oaktrail_m_converts[] = { 87 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C, 88 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25, 89 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c, 90 }; 91 92 static const struct gma_limit_t *mrst_limit(struct drm_crtc *crtc, 93 int refclk) 94 { 95 const struct gma_limit_t *limit = NULL; 96 struct drm_device *dev = crtc->dev; 97 struct drm_psb_private *dev_priv = dev->dev_private; 98 99 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 100 || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { 101 switch (dev_priv->core_freq) { 102 case 100: 103 limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; 104 break; 105 case 166: 106 limit = &mrst_limits[MRST_LIMIT_LVDS_83]; 107 break; 108 case 200: 109 limit = &mrst_limits[MRST_LIMIT_LVDS_100]; 110 break; 111 } 112 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 113 limit = &mrst_limits[MRST_LIMIT_SDVO]; 114 } else { 115 limit = NULL; 116 dev_err(dev->dev, "mrst_limit Wrong display type.\n"); 117 } 118 119 return limit; 120 } 121 122 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 123 static void mrst_lvds_clock(int refclk, struct gma_clock_t *clock) 124 { 125 clock->dot = (refclk * clock->m) / (14 * clock->p1); 126 } 127 128 static void mrst_print_pll(struct gma_clock_t *clock) 129 { 130 DRM_DEBUG_DRIVER("dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n", 131 clock->dot, clock->m, clock->m1, clock->m2, clock->n, 132 clock->p1, clock->p2); 133 } 134 135 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, 136 struct drm_crtc *crtc, int target, 137 int refclk, struct gma_clock_t *best_clock) 138 { 139 struct gma_clock_t clock; 140 u32 target_vco, actual_freq; 141 s32 freq_error, min_error = 100000; 142 143 memset(best_clock, 0, sizeof(*best_clock)); 144 145 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { 146 for (clock.n = limit->n.min; clock.n <= limit->n.max; 147 clock.n++) { 148 for (clock.p1 = limit->p1.min; 149 clock.p1 <= limit->p1.max; clock.p1++) { 150 /* p2 value always stored in p2_slow on SDVO */ 151 clock.p = clock.p1 * limit->p2.p2_slow; 152 target_vco = target * clock.p; 153 154 /* VCO will increase at this point so break */ 155 if (target_vco > limit->vco.max) 156 break; 157 158 if (target_vco < limit->vco.min) 159 continue; 160 161 actual_freq = (refclk * clock.m) / 162 (clock.n * clock.p); 163 freq_error = 10000 - 164 ((target * 10000) / actual_freq); 165 166 if (freq_error < -min_error) { 167 /* freq_error will start to decrease at 168 this point so break */ 169 break; 170 } 171 172 if (freq_error < 0) 173 freq_error = -freq_error; 174 175 if (freq_error < min_error) { 176 min_error = freq_error; 177 *best_clock = clock; 178 } 179 } 180 } 181 if (min_error == 0) 182 break; 183 } 184 185 return min_error == 0; 186 } 187 188 /** 189 * Returns a set of divisors for the desired target clock with the given refclk, 190 * or FALSE. Divisor values are the actual divisors for 191 */ 192 static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, 193 struct drm_crtc *crtc, int target, 194 int refclk, struct gma_clock_t *best_clock) 195 { 196 struct gma_clock_t clock; 197 int err = target; 198 199 memset(best_clock, 0, sizeof(*best_clock)); 200 201 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { 202 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; 203 clock.p1++) { 204 int this_err; 205 206 mrst_lvds_clock(refclk, &clock); 207 208 this_err = abs(clock.dot - target); 209 if (this_err < err) { 210 *best_clock = clock; 211 err = this_err; 212 } 213 } 214 } 215 return err != target; 216 } 217 218 /** 219 * Sets the power management mode of the pipe and plane. 220 * 221 * This code should probably grow support for turning the cursor off and back 222 * on appropriately at the same time as we're turning the pipe off/on. 223 */ 224 static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode) 225 { 226 struct drm_device *dev = crtc->dev; 227 struct drm_psb_private *dev_priv = dev->dev_private; 228 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 229 int pipe = gma_crtc->pipe; 230 const struct psb_offset *map = &dev_priv->regmap[pipe]; 231 u32 temp; 232 int i; 233 int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0; 234 235 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { 236 oaktrail_crtc_hdmi_dpms(crtc, mode); 237 return; 238 } 239 240 if (!gma_power_begin(dev, true)) 241 return; 242 243 /* XXX: When our outputs are all unaware of DPMS modes other than off 244 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 245 */ 246 switch (mode) { 247 case DRM_MODE_DPMS_ON: 248 case DRM_MODE_DPMS_STANDBY: 249 case DRM_MODE_DPMS_SUSPEND: 250 for (i = 0; i <= need_aux; i++) { 251 /* Enable the DPLL */ 252 temp = REG_READ_WITH_AUX(map->dpll, i); 253 if ((temp & DPLL_VCO_ENABLE) == 0) { 254 REG_WRITE_WITH_AUX(map->dpll, temp, i); 255 REG_READ_WITH_AUX(map->dpll, i); 256 /* Wait for the clocks to stabilize. */ 257 udelay(150); 258 REG_WRITE_WITH_AUX(map->dpll, 259 temp | DPLL_VCO_ENABLE, i); 260 REG_READ_WITH_AUX(map->dpll, i); 261 /* Wait for the clocks to stabilize. */ 262 udelay(150); 263 REG_WRITE_WITH_AUX(map->dpll, 264 temp | DPLL_VCO_ENABLE, i); 265 REG_READ_WITH_AUX(map->dpll, i); 266 /* Wait for the clocks to stabilize. */ 267 udelay(150); 268 } 269 270 /* Enable the pipe */ 271 temp = REG_READ_WITH_AUX(map->conf, i); 272 if ((temp & PIPEACONF_ENABLE) == 0) { 273 REG_WRITE_WITH_AUX(map->conf, 274 temp | PIPEACONF_ENABLE, i); 275 } 276 277 /* Enable the plane */ 278 temp = REG_READ_WITH_AUX(map->cntr, i); 279 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 280 REG_WRITE_WITH_AUX(map->cntr, 281 temp | DISPLAY_PLANE_ENABLE, 282 i); 283 /* Flush the plane changes */ 284 REG_WRITE_WITH_AUX(map->base, 285 REG_READ_WITH_AUX(map->base, i), i); 286 } 287 288 } 289 gma_crtc_load_lut(crtc); 290 291 /* Give the overlay scaler a chance to enable 292 if it's on this pipe */ 293 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 294 break; 295 case DRM_MODE_DPMS_OFF: 296 /* Give the overlay scaler a chance to disable 297 * if it's on this pipe */ 298 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 299 300 for (i = 0; i <= need_aux; i++) { 301 /* Disable the VGA plane that we never use */ 302 REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i); 303 /* Disable display plane */ 304 temp = REG_READ_WITH_AUX(map->cntr, i); 305 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 306 REG_WRITE_WITH_AUX(map->cntr, 307 temp & ~DISPLAY_PLANE_ENABLE, i); 308 /* Flush the plane changes */ 309 REG_WRITE_WITH_AUX(map->base, 310 REG_READ(map->base), i); 311 REG_READ_WITH_AUX(map->base, i); 312 } 313 314 /* Next, disable display pipes */ 315 temp = REG_READ_WITH_AUX(map->conf, i); 316 if ((temp & PIPEACONF_ENABLE) != 0) { 317 REG_WRITE_WITH_AUX(map->conf, 318 temp & ~PIPEACONF_ENABLE, i); 319 REG_READ_WITH_AUX(map->conf, i); 320 } 321 /* Wait for for the pipe disable to take effect. */ 322 gma_wait_for_vblank(dev); 323 324 temp = REG_READ_WITH_AUX(map->dpll, i); 325 if ((temp & DPLL_VCO_ENABLE) != 0) { 326 REG_WRITE_WITH_AUX(map->dpll, 327 temp & ~DPLL_VCO_ENABLE, i); 328 REG_READ_WITH_AUX(map->dpll, i); 329 } 330 331 /* Wait for the clocks to turn off. */ 332 udelay(150); 333 } 334 break; 335 } 336 337 /* Set FIFO Watermarks (values taken from EMGD) */ 338 REG_WRITE(DSPARB, 0x3f80); 339 REG_WRITE(DSPFW1, 0x3f8f0404); 340 REG_WRITE(DSPFW2, 0x04040f04); 341 REG_WRITE(DSPFW3, 0x0); 342 REG_WRITE(DSPFW4, 0x04040404); 343 REG_WRITE(DSPFW5, 0x04040404); 344 REG_WRITE(DSPFW6, 0x78); 345 REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); 346 347 gma_power_end(dev); 348 } 349 350 /** 351 * Return the pipe currently connected to the panel fitter, 352 * or -1 if the panel fitter is not present or not in use 353 */ 354 static int oaktrail_panel_fitter_pipe(struct drm_device *dev) 355 { 356 u32 pfit_control; 357 358 pfit_control = REG_READ(PFIT_CONTROL); 359 360 /* See if the panel fitter is in use */ 361 if ((pfit_control & PFIT_ENABLE) == 0) 362 return -1; 363 return (pfit_control >> 29) & 3; 364 } 365 366 static int oaktrail_crtc_mode_set(struct drm_crtc *crtc, 367 struct drm_display_mode *mode, 368 struct drm_display_mode *adjusted_mode, 369 int x, int y, 370 struct drm_framebuffer *old_fb) 371 { 372 struct drm_device *dev = crtc->dev; 373 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 374 struct drm_psb_private *dev_priv = dev->dev_private; 375 int pipe = gma_crtc->pipe; 376 const struct psb_offset *map = &dev_priv->regmap[pipe]; 377 int refclk = 0; 378 struct gma_clock_t clock; 379 const struct gma_limit_t *limit; 380 u32 dpll = 0, fp = 0, dspcntr, pipeconf; 381 bool ok, is_sdvo = false; 382 bool is_lvds = false; 383 bool is_mipi = false; 384 struct drm_mode_config *mode_config = &dev->mode_config; 385 struct gma_encoder *gma_encoder = NULL; 386 uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN; 387 struct drm_connector *connector; 388 int i; 389 int need_aux = gma_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ? 1 : 0; 390 391 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 392 return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb); 393 394 if (!gma_power_begin(dev, true)) 395 return 0; 396 397 memcpy(&gma_crtc->saved_mode, 398 mode, 399 sizeof(struct drm_display_mode)); 400 memcpy(&gma_crtc->saved_adjusted_mode, 401 adjusted_mode, 402 sizeof(struct drm_display_mode)); 403 404 list_for_each_entry(connector, &mode_config->connector_list, head) { 405 if (!connector->encoder || connector->encoder->crtc != crtc) 406 continue; 407 408 gma_encoder = gma_attached_encoder(connector); 409 410 switch (gma_encoder->type) { 411 case INTEL_OUTPUT_LVDS: 412 is_lvds = true; 413 break; 414 case INTEL_OUTPUT_SDVO: 415 is_sdvo = true; 416 break; 417 case INTEL_OUTPUT_MIPI: 418 is_mipi = true; 419 break; 420 } 421 } 422 423 /* Disable the VGA plane that we never use */ 424 for (i = 0; i <= need_aux; i++) 425 REG_WRITE_WITH_AUX(VGACNTRL, VGA_DISP_DISABLE, i); 426 427 /* Disable the panel fitter if it was on our pipe */ 428 if (oaktrail_panel_fitter_pipe(dev) == pipe) 429 REG_WRITE(PFIT_CONTROL, 0); 430 431 for (i = 0; i <= need_aux; i++) { 432 REG_WRITE_WITH_AUX(map->src, ((mode->crtc_hdisplay - 1) << 16) | 433 (mode->crtc_vdisplay - 1), i); 434 } 435 436 if (gma_encoder) 437 drm_object_property_get_value(&connector->base, 438 dev->mode_config.scaling_mode_property, &scalingType); 439 440 if (scalingType == DRM_MODE_SCALE_NO_SCALE) { 441 /* Moorestown doesn't have register support for centering so 442 * we need to mess with the h/vblank and h/vsync start and 443 * ends to get centering */ 444 int offsetX = 0, offsetY = 0; 445 446 offsetX = (adjusted_mode->crtc_hdisplay - 447 mode->crtc_hdisplay) / 2; 448 offsetY = (adjusted_mode->crtc_vdisplay - 449 mode->crtc_vdisplay) / 2; 450 451 for (i = 0; i <= need_aux; i++) { 452 REG_WRITE_WITH_AUX(map->htotal, (mode->crtc_hdisplay - 1) | 453 ((adjusted_mode->crtc_htotal - 1) << 16), i); 454 REG_WRITE_WITH_AUX(map->vtotal, (mode->crtc_vdisplay - 1) | 455 ((adjusted_mode->crtc_vtotal - 1) << 16), i); 456 REG_WRITE_WITH_AUX(map->hblank, 457 (adjusted_mode->crtc_hblank_start - offsetX - 1) | 458 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16), i); 459 REG_WRITE_WITH_AUX(map->hsync, 460 (adjusted_mode->crtc_hsync_start - offsetX - 1) | 461 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16), i); 462 REG_WRITE_WITH_AUX(map->vblank, 463 (adjusted_mode->crtc_vblank_start - offsetY - 1) | 464 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16), i); 465 REG_WRITE_WITH_AUX(map->vsync, 466 (adjusted_mode->crtc_vsync_start - offsetY - 1) | 467 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16), i); 468 } 469 } else { 470 for (i = 0; i <= need_aux; i++) { 471 REG_WRITE_WITH_AUX(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 472 ((adjusted_mode->crtc_htotal - 1) << 16), i); 473 REG_WRITE_WITH_AUX(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 474 ((adjusted_mode->crtc_vtotal - 1) << 16), i); 475 REG_WRITE_WITH_AUX(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 476 ((adjusted_mode->crtc_hblank_end - 1) << 16), i); 477 REG_WRITE_WITH_AUX(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 478 ((adjusted_mode->crtc_hsync_end - 1) << 16), i); 479 REG_WRITE_WITH_AUX(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 480 ((adjusted_mode->crtc_vblank_end - 1) << 16), i); 481 REG_WRITE_WITH_AUX(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 482 ((adjusted_mode->crtc_vsync_end - 1) << 16), i); 483 } 484 } 485 486 /* Flush the plane changes */ 487 { 488 const struct drm_crtc_helper_funcs *crtc_funcs = 489 crtc->helper_private; 490 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 491 } 492 493 /* setup pipeconf */ 494 pipeconf = REG_READ(map->conf); 495 496 /* Set up the display plane register */ 497 dspcntr = REG_READ(map->cntr); 498 dspcntr |= DISPPLANE_GAMMA_ENABLE; 499 500 if (pipe == 0) 501 dspcntr |= DISPPLANE_SEL_PIPE_A; 502 else 503 dspcntr |= DISPPLANE_SEL_PIPE_B; 504 505 if (is_mipi) 506 goto oaktrail_crtc_mode_set_exit; 507 508 509 dpll = 0; /*BIT16 = 0 for 100MHz reference */ 510 511 refclk = is_sdvo ? 96000 : dev_priv->core_freq * 1000; 512 limit = mrst_limit(crtc, refclk); 513 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, 514 refclk, &clock); 515 516 if (is_sdvo) { 517 /* Convert calculated values to register values */ 518 clock.p1 = (1L << (clock.p1 - 1)); 519 clock.m -= 2; 520 clock.n = (1L << (clock.n - 1)); 521 } 522 523 if (!ok) 524 DRM_ERROR("Failed to find proper PLL settings"); 525 526 mrst_print_pll(&clock); 527 528 if (is_sdvo) 529 fp = clock.n << 16 | clock.m; 530 else 531 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8; 532 533 dpll |= DPLL_VGA_MODE_DIS; 534 535 536 dpll |= DPLL_VCO_ENABLE; 537 538 if (is_lvds) 539 dpll |= DPLLA_MODE_LVDS; 540 else 541 dpll |= DPLLB_MODE_DAC_SERIAL; 542 543 if (is_sdvo) { 544 int sdvo_pixel_multiply = 545 adjusted_mode->clock / mode->clock; 546 547 dpll |= DPLL_DVO_HIGH_SPEED; 548 dpll |= 549 (sdvo_pixel_multiply - 550 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 551 } 552 553 554 /* compute bitmask from p1 value */ 555 if (is_sdvo) 556 dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16; 557 else 558 dpll |= (1 << (clock.p1 - 2)) << 17; 559 560 dpll |= DPLL_VCO_ENABLE; 561 562 if (dpll & DPLL_VCO_ENABLE) { 563 for (i = 0; i <= need_aux; i++) { 564 REG_WRITE_WITH_AUX(map->fp0, fp, i); 565 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); 566 REG_READ_WITH_AUX(map->dpll, i); 567 /* Check the DPLLA lock bit PIPEACONF[29] */ 568 udelay(150); 569 } 570 } 571 572 for (i = 0; i <= need_aux; i++) { 573 REG_WRITE_WITH_AUX(map->fp0, fp, i); 574 REG_WRITE_WITH_AUX(map->dpll, dpll, i); 575 REG_READ_WITH_AUX(map->dpll, i); 576 /* Wait for the clocks to stabilize. */ 577 udelay(150); 578 579 /* write it again -- the BIOS does, after all */ 580 REG_WRITE_WITH_AUX(map->dpll, dpll, i); 581 REG_READ_WITH_AUX(map->dpll, i); 582 /* Wait for the clocks to stabilize. */ 583 udelay(150); 584 585 REG_WRITE_WITH_AUX(map->conf, pipeconf, i); 586 REG_READ_WITH_AUX(map->conf, i); 587 gma_wait_for_vblank(dev); 588 589 REG_WRITE_WITH_AUX(map->cntr, dspcntr, i); 590 gma_wait_for_vblank(dev); 591 } 592 593 oaktrail_crtc_mode_set_exit: 594 gma_power_end(dev); 595 return 0; 596 } 597 598 static int oaktrail_pipe_set_base(struct drm_crtc *crtc, 599 int x, int y, struct drm_framebuffer *old_fb) 600 { 601 struct drm_device *dev = crtc->dev; 602 struct drm_psb_private *dev_priv = dev->dev_private; 603 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 604 struct drm_framebuffer *fb = crtc->primary->fb; 605 int pipe = gma_crtc->pipe; 606 const struct psb_offset *map = &dev_priv->regmap[pipe]; 607 unsigned long start, offset; 608 609 u32 dspcntr; 610 int ret = 0; 611 612 /* no fb bound */ 613 if (!fb) { 614 dev_dbg(dev->dev, "No FB bound\n"); 615 return 0; 616 } 617 618 if (!gma_power_begin(dev, true)) 619 return 0; 620 621 start = to_gtt_range(fb->obj[0])->offset; 622 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; 623 624 REG_WRITE(map->stride, fb->pitches[0]); 625 626 dspcntr = REG_READ(map->cntr); 627 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 628 629 switch (fb->format->cpp[0] * 8) { 630 case 8: 631 dspcntr |= DISPPLANE_8BPP; 632 break; 633 case 16: 634 if (fb->format->depth == 15) 635 dspcntr |= DISPPLANE_15_16BPP; 636 else 637 dspcntr |= DISPPLANE_16BPP; 638 break; 639 case 24: 640 case 32: 641 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 642 break; 643 default: 644 dev_err(dev->dev, "Unknown color depth\n"); 645 ret = -EINVAL; 646 goto pipe_set_base_exit; 647 } 648 REG_WRITE(map->cntr, dspcntr); 649 650 REG_WRITE(map->base, offset); 651 REG_READ(map->base); 652 REG_WRITE(map->surf, start); 653 REG_READ(map->surf); 654 655 pipe_set_base_exit: 656 gma_power_end(dev); 657 return ret; 658 } 659 660 const struct drm_crtc_helper_funcs oaktrail_helper_funcs = { 661 .dpms = oaktrail_crtc_dpms, 662 .mode_set = oaktrail_crtc_mode_set, 663 .mode_set_base = oaktrail_pipe_set_base, 664 .prepare = gma_crtc_prepare, 665 .commit = gma_crtc_commit, 666 }; 667 668 /* Not used yet */ 669 const struct gma_clock_funcs mrst_clock_funcs = { 670 .clock = mrst_lvds_clock, 671 .limit = mrst_limit, 672 .pll_is_valid = gma_pll_is_valid, 673 }; 674