1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /************************************************************************** 3 * Copyright (c) 2007-2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 /* MID device specific descriptors */ 9 10 struct oaktrail_timing_info { 11 u16 pixel_clock; 12 u8 hactive_lo; 13 u8 hblank_lo; 14 u8 hblank_hi:4; 15 u8 hactive_hi:4; 16 u8 vactive_lo; 17 u8 vblank_lo; 18 u8 vblank_hi:4; 19 u8 vactive_hi:4; 20 u8 hsync_offset_lo; 21 u8 hsync_pulse_width_lo; 22 u8 vsync_pulse_width_lo:4; 23 u8 vsync_offset_lo:4; 24 u8 vsync_pulse_width_hi:2; 25 u8 vsync_offset_hi:2; 26 u8 hsync_pulse_width_hi:2; 27 u8 hsync_offset_hi:2; 28 u8 width_mm_lo; 29 u8 height_mm_lo; 30 u8 height_mm_hi:4; 31 u8 width_mm_hi:4; 32 u8 hborder; 33 u8 vborder; 34 u8 unknown0:1; 35 u8 hsync_positive:1; 36 u8 vsync_positive:1; 37 u8 separate_sync:2; 38 u8 stereo:1; 39 u8 unknown6:1; 40 u8 interlaced:1; 41 } __packed; 42 43 struct gct_r10_timing_info { 44 u16 pixel_clock; 45 u32 hactive_lo:8; 46 u32 hactive_hi:4; 47 u32 hblank_lo:8; 48 u32 hblank_hi:4; 49 u32 hsync_offset_lo:8; 50 u16 hsync_offset_hi:2; 51 u16 hsync_pulse_width_lo:8; 52 u16 hsync_pulse_width_hi:2; 53 u16 hsync_positive:1; 54 u16 rsvd_1:3; 55 u8 vactive_lo:8; 56 u16 vactive_hi:4; 57 u16 vblank_lo:8; 58 u16 vblank_hi:4; 59 u16 vsync_offset_lo:4; 60 u16 vsync_offset_hi:2; 61 u16 vsync_pulse_width_lo:4; 62 u16 vsync_pulse_width_hi:2; 63 u16 vsync_positive:1; 64 u16 rsvd_2:3; 65 } __packed; 66 67 struct oaktrail_panel_descriptor_v1 { 68 u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ 69 /* 0x61190 if MIPI */ 70 u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ 71 u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 72 u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */ 73 /* Register 0x61210 */ 74 struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */ 75 u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */ 76 /* Bit 0, Frequency, 15 bits,0 - 32767Hz */ 77 /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */ 78 u16 Panel_MIPI_Display_Descriptor; 79 /*16 bits, Defined as follows: */ 80 /* if MIPI, 0x0000 if LVDS */ 81 /* Bit 0, Type, 2 bits, */ 82 /* 0: Type-1, */ 83 /* 1: Type-2, */ 84 /* 2: Type-3, */ 85 /* 3: Type-4 */ 86 /* Bit 2, Pixel Format, 4 bits */ 87 /* Bit0: 16bpp (not supported in LNC), */ 88 /* Bit1: 18bpp loosely packed, */ 89 /* Bit2: 18bpp packed, */ 90 /* Bit3: 24bpp */ 91 /* Bit 6, Reserved, 2 bits, 00b */ 92 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ 93 /* Bit 14, Reserved, 2 bits, 00b */ 94 } __packed; 95 96 struct oaktrail_panel_descriptor_v2 { 97 u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ 98 /* 0x61190 if MIPI */ 99 u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ 100 u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 101 u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */ 102 /* Register 0x61210 */ 103 struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */ 104 u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/ 105 /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/ 106 u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */ 107 /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/ 108 u16 Panel_MIPI_Display_Descriptor; 109 /*16 bits, Defined as follows: */ 110 /* if MIPI, 0x0000 if LVDS */ 111 /* Bit 0, Type, 2 bits, */ 112 /* 0: Type-1, */ 113 /* 1: Type-2, */ 114 /* 2: Type-3, */ 115 /* 3: Type-4 */ 116 /* Bit 2, Pixel Format, 4 bits */ 117 /* Bit0: 16bpp (not supported in LNC), */ 118 /* Bit1: 18bpp loosely packed, */ 119 /* Bit2: 18bpp packed, */ 120 /* Bit3: 24bpp */ 121 /* Bit 6, Reserved, 2 bits, 00b */ 122 /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ 123 /* Bit 14, Reserved, 2 bits, 00b */ 124 } __packed; 125 126 union oaktrail_panel_rx { 127 struct { 128 u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/ 129 /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */ 130 u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */ 131 /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/ 132 u16 SupportedVideoTransferMode:2; /*0: Non-burst only */ 133 /* 1: Burst and non-burst */ 134 /* 2/3: Reserved */ 135 u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/ 136 u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/ 137 u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/ 138 u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */ 139 u16 Rsvd:5;/*5 bits,00000b */ 140 } panelrx; 141 u16 panel_receiver; 142 } __packed; 143 144 struct gct_r0 { 145 union { /*8 bits,Defined as follows: */ 146 struct { 147 u8 PanelType:4; /*4 bits, Bit field for panels*/ 148 /* 0 - 3: 0 = LVDS, 1 = MIPI*/ 149 /*2 bits,Specifies which of the*/ 150 u8 BootPanelIndex:2; 151 /* 4 panels to use by default*/ 152 u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ 153 /* the 4 MIPI DSI receivers to use*/ 154 } PD; 155 u8 PanelDescriptor; 156 }; 157 struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/ 158 union oaktrail_panel_rx panelrx[4]; /* panel receivers*/ 159 } __packed; 160 161 struct gct_r1 { 162 union { /*8 bits,Defined as follows: */ 163 struct { 164 u8 PanelType:4; /*4 bits, Bit field for panels*/ 165 /* 0 - 3: 0 = LVDS, 1 = MIPI*/ 166 /*2 bits,Specifies which of the*/ 167 u8 BootPanelIndex:2; 168 /* 4 panels to use by default*/ 169 u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ 170 /* the 4 MIPI DSI receivers to use*/ 171 } PD; 172 u8 PanelDescriptor; 173 }; 174 struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/ 175 union oaktrail_panel_rx panelrx[4]; /* panel receivers*/ 176 } __packed; 177 178 struct gct_r10 { 179 struct gct_r10_timing_info DTD; 180 u16 Panel_MIPI_Display_Descriptor; 181 u16 Panel_MIPI_Receiver_Descriptor; 182 u16 Panel_Backlight_Inverter_Descriptor; 183 u8 Panel_Initial_Brightness; 184 u32 MIPI_Ctlr_Init_ptr; 185 u32 MIPI_Panel_Init_ptr; 186 } __packed; 187 188 struct oaktrail_gct_data { 189 u8 bpi; /* boot panel index, number of panel used during boot */ 190 u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */ 191 struct oaktrail_timing_info DTD; /* timing info for the selected panel */ 192 u32 Panel_Port_Control; 193 u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/ 194 u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/ 195 u32 PP_Cycle_Delay; 196 u16 Panel_Backlight_Inverter_Descriptor; 197 u16 Panel_MIPI_Display_Descriptor; 198 } __packed; 199 200 #define MODE_SETTING_IN_CRTC 0x1 201 #define MODE_SETTING_IN_ENCODER 0x2 202 #define MODE_SETTING_ON_GOING 0x3 203 #define MODE_SETTING_IN_DSR 0x4 204 #define MODE_SETTING_ENCODER_DONE 0x8 205 206 /* 207 * Moorestown HDMI interfaces 208 */ 209 210 struct oaktrail_hdmi_dev { 211 struct pci_dev *dev; 212 void __iomem *regs; 213 unsigned int mmio, mmio_len; 214 int dpms_mode; 215 struct hdmi_i2c_dev *i2c_dev; 216 217 /* register state */ 218 u32 saveDPLL_CTRL; 219 u32 saveDPLL_DIV_CTRL; 220 u32 saveDPLL_ADJUST; 221 u32 saveDPLL_UPDATE; 222 u32 saveDPLL_CLK_ENABLE; 223 u32 savePCH_HTOTAL_B; 224 u32 savePCH_HBLANK_B; 225 u32 savePCH_HSYNC_B; 226 u32 savePCH_VTOTAL_B; 227 u32 savePCH_VBLANK_B; 228 u32 savePCH_VSYNC_B; 229 u32 savePCH_PIPEBCONF; 230 u32 savePCH_PIPEBSRC; 231 }; 232 233 extern void oaktrail_hdmi_setup(struct drm_device *dev); 234 extern void oaktrail_hdmi_teardown(struct drm_device *dev); 235 extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev); 236 extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev); 237 extern void oaktrail_hdmi_save(struct drm_device *dev); 238 extern void oaktrail_hdmi_restore(struct drm_device *dev); 239 extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev); 240 extern int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 241 struct drm_display_mode *adjusted_mode, int x, int y, 242 struct drm_framebuffer *old_fb); 243 extern void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc, int mode); 244 245 246