1 /************************************************************************** 2 * Copyright (c) 2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 /* TODO 21 * - Split functions by vbt type 22 * - Make them all take drm_device 23 * - Check ioremap failures 24 */ 25 26 #include <drm/drm.h> 27 28 #include "mid_bios.h" 29 #include "psb_drv.h" 30 31 static void mid_get_fuse_settings(struct drm_device *dev) 32 { 33 struct drm_psb_private *dev_priv = dev->dev_private; 34 struct pci_dev *pci_root = 35 pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus), 36 0, 0); 37 uint32_t fuse_value = 0; 38 uint32_t fuse_value_tmp = 0; 39 40 #define FB_REG06 0xD0810600 41 #define FB_MIPI_DISABLE (1 << 11) 42 #define FB_REG09 0xD0810900 43 #define FB_SKU_MASK 0x7000 44 #define FB_SKU_SHIFT 12 45 #define FB_SKU_100 0 46 #define FB_SKU_100L 1 47 #define FB_SKU_83 2 48 if (pci_root == NULL) { 49 WARN_ON(1); 50 return; 51 } 52 53 54 pci_write_config_dword(pci_root, 0xD0, FB_REG06); 55 pci_read_config_dword(pci_root, 0xD4, &fuse_value); 56 57 /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */ 58 if (IS_MRST(dev)) 59 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE; 60 61 DRM_INFO("internal display is %s\n", 62 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display"); 63 64 /* Prevent runtime suspend at start*/ 65 if (dev_priv->iLVDS_enable) { 66 dev_priv->is_lvds_on = true; 67 dev_priv->is_mipi_on = false; 68 } else { 69 dev_priv->is_mipi_on = true; 70 dev_priv->is_lvds_on = false; 71 } 72 73 dev_priv->video_device_fuse = fuse_value; 74 75 pci_write_config_dword(pci_root, 0xD0, FB_REG09); 76 pci_read_config_dword(pci_root, 0xD4, &fuse_value); 77 78 dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value); 79 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT; 80 81 dev_priv->fuse_reg_value = fuse_value; 82 83 switch (fuse_value_tmp) { 84 case FB_SKU_100: 85 dev_priv->core_freq = 200; 86 break; 87 case FB_SKU_100L: 88 dev_priv->core_freq = 100; 89 break; 90 case FB_SKU_83: 91 dev_priv->core_freq = 166; 92 break; 93 default: 94 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n", 95 fuse_value_tmp); 96 dev_priv->core_freq = 0; 97 } 98 dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq); 99 pci_dev_put(pci_root); 100 } 101 102 /* 103 * Get the revison ID, B0:D2:F0;0x08 104 */ 105 static void mid_get_pci_revID(struct drm_psb_private *dev_priv) 106 { 107 uint32_t platform_rev_id = 0; 108 int domain = pci_domain_nr(dev_priv->dev->pdev->bus); 109 struct pci_dev *pci_gfx_root = 110 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0)); 111 112 if (pci_gfx_root == NULL) { 113 WARN_ON(1); 114 return; 115 } 116 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id); 117 dev_priv->platform_rev_id = (uint8_t) platform_rev_id; 118 pci_dev_put(pci_gfx_root); 119 dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n", 120 dev_priv->platform_rev_id); 121 } 122 123 struct mid_vbt_header { 124 u32 signature; 125 u8 revision; 126 } __packed; 127 128 /* The same for r0 and r1 */ 129 struct vbt_r0 { 130 struct mid_vbt_header vbt_header; 131 u8 size; 132 u8 checksum; 133 } __packed; 134 135 struct vbt_r10 { 136 struct mid_vbt_header vbt_header; 137 u8 checksum; 138 u16 size; 139 u8 panel_count; 140 u8 primary_panel_idx; 141 u8 secondary_panel_idx; 142 u8 __reserved[5]; 143 } __packed; 144 145 static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt) 146 { 147 void __iomem *vbt_virtual; 148 149 vbt_virtual = ioremap(addr, sizeof(*vbt)); 150 if (vbt_virtual == NULL) 151 return -1; 152 153 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt)); 154 iounmap(vbt_virtual); 155 156 return 0; 157 } 158 159 static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt) 160 { 161 void __iomem *vbt_virtual; 162 163 vbt_virtual = ioremap(addr, sizeof(*vbt)); 164 if (!vbt_virtual) 165 return -1; 166 167 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt)); 168 iounmap(vbt_virtual); 169 170 return 0; 171 } 172 173 static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr) 174 { 175 struct vbt_r0 vbt; 176 void __iomem *gct_virtual; 177 struct gct_r0 gct; 178 u8 bpi; 179 180 if (read_vbt_r0(addr, &vbt)) 181 return -1; 182 183 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt)); 184 if (!gct_virtual) 185 return -1; 186 memcpy_fromio(&gct, gct_virtual, sizeof(gct)); 187 iounmap(gct_virtual); 188 189 bpi = gct.PD.BootPanelIndex; 190 dev_priv->gct_data.bpi = bpi; 191 dev_priv->gct_data.pt = gct.PD.PanelType; 192 dev_priv->gct_data.DTD = gct.panel[bpi].DTD; 193 dev_priv->gct_data.Panel_Port_Control = 194 gct.panel[bpi].Panel_Port_Control; 195 dev_priv->gct_data.Panel_MIPI_Display_Descriptor = 196 gct.panel[bpi].Panel_MIPI_Display_Descriptor; 197 198 return 0; 199 } 200 201 static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr) 202 { 203 struct vbt_r0 vbt; 204 void __iomem *gct_virtual; 205 struct gct_r1 gct; 206 u8 bpi; 207 208 if (read_vbt_r0(addr, &vbt)) 209 return -1; 210 211 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt)); 212 if (!gct_virtual) 213 return -1; 214 memcpy_fromio(&gct, gct_virtual, sizeof(gct)); 215 iounmap(gct_virtual); 216 217 bpi = gct.PD.BootPanelIndex; 218 dev_priv->gct_data.bpi = bpi; 219 dev_priv->gct_data.pt = gct.PD.PanelType; 220 dev_priv->gct_data.DTD = gct.panel[bpi].DTD; 221 dev_priv->gct_data.Panel_Port_Control = 222 gct.panel[bpi].Panel_Port_Control; 223 dev_priv->gct_data.Panel_MIPI_Display_Descriptor = 224 gct.panel[bpi].Panel_MIPI_Display_Descriptor; 225 226 return 0; 227 } 228 229 static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr) 230 { 231 struct vbt_r10 vbt; 232 void __iomem *gct_virtual; 233 struct gct_r10 *gct; 234 struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD; 235 struct gct_r10_timing_info *ti; 236 int ret = -1; 237 238 if (read_vbt_r10(addr, &vbt)) 239 return -1; 240 241 gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL); 242 if (!gct) 243 return -ENOMEM; 244 245 gct_virtual = ioremap(addr + sizeof(vbt), 246 sizeof(*gct) * vbt.panel_count); 247 if (!gct_virtual) 248 goto out; 249 memcpy_fromio(gct, gct_virtual, sizeof(*gct)); 250 iounmap(gct_virtual); 251 252 dev_priv->gct_data.bpi = vbt.primary_panel_idx; 253 dev_priv->gct_data.Panel_MIPI_Display_Descriptor = 254 gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor; 255 256 ti = &gct[vbt.primary_panel_idx].DTD; 257 dp_ti->pixel_clock = ti->pixel_clock; 258 dp_ti->hactive_hi = ti->hactive_hi; 259 dp_ti->hactive_lo = ti->hactive_lo; 260 dp_ti->hblank_hi = ti->hblank_hi; 261 dp_ti->hblank_lo = ti->hblank_lo; 262 dp_ti->hsync_offset_hi = ti->hsync_offset_hi; 263 dp_ti->hsync_offset_lo = ti->hsync_offset_lo; 264 dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi; 265 dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo; 266 dp_ti->vactive_hi = ti->vactive_hi; 267 dp_ti->vactive_lo = ti->vactive_lo; 268 dp_ti->vblank_hi = ti->vblank_hi; 269 dp_ti->vblank_lo = ti->vblank_lo; 270 dp_ti->vsync_offset_hi = ti->vsync_offset_hi; 271 dp_ti->vsync_offset_lo = ti->vsync_offset_lo; 272 dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi; 273 dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo; 274 275 ret = 0; 276 out: 277 kfree(gct); 278 return ret; 279 } 280 281 static void mid_get_vbt_data(struct drm_psb_private *dev_priv) 282 { 283 struct drm_device *dev = dev_priv->dev; 284 u32 addr; 285 u8 __iomem *vbt_virtual; 286 struct mid_vbt_header vbt_header; 287 struct pci_dev *pci_gfx_root = 288 pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus), 289 0, PCI_DEVFN(2, 0)); 290 int ret = -1; 291 292 /* Get the address of the platform config vbt */ 293 pci_read_config_dword(pci_gfx_root, 0xFC, &addr); 294 pci_dev_put(pci_gfx_root); 295 296 dev_dbg(dev->dev, "drm platform config address is %x\n", addr); 297 298 if (!addr) 299 goto out; 300 301 /* get the virtual address of the vbt */ 302 vbt_virtual = ioremap(addr, sizeof(vbt_header)); 303 if (!vbt_virtual) 304 goto out; 305 306 memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header)); 307 iounmap(vbt_virtual); 308 309 if (memcmp(&vbt_header.signature, "$GCT", 4)) 310 goto out; 311 312 dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision); 313 314 switch (vbt_header.revision) { 315 case 0x00: 316 ret = mid_get_vbt_data_r0(dev_priv, addr); 317 break; 318 case 0x01: 319 ret = mid_get_vbt_data_r1(dev_priv, addr); 320 break; 321 case 0x10: 322 ret = mid_get_vbt_data_r10(dev_priv, addr); 323 break; 324 default: 325 dev_err(dev->dev, "Unknown revision of GCT!\n"); 326 } 327 328 out: 329 if (ret) 330 dev_err(dev->dev, "Unable to read GCT!"); 331 else 332 dev_priv->has_gct = true; 333 } 334 335 int mid_chip_setup(struct drm_device *dev) 336 { 337 struct drm_psb_private *dev_priv = dev->dev_private; 338 mid_get_fuse_settings(dev); 339 mid_get_vbt_data(dev_priv); 340 mid_get_pci_revID(dev_priv); 341 return 0; 342 } 343