1 /* 2 * Copyright (c) 2006 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 * 20 */ 21 22 #ifndef _I830_BIOS_H_ 23 #define _I830_BIOS_H_ 24 25 #include <drm/drmP.h> 26 27 struct vbt_header { 28 u8 signature[20]; /**< Always starts with 'VBT$' */ 29 u16 version; /**< decimal */ 30 u16 header_size; /**< in bytes */ 31 u16 vbt_size; /**< in bytes */ 32 u8 vbt_checksum; 33 u8 reserved0; 34 u32 bdb_offset; /**< from beginning of VBT */ 35 u32 aim_offset[4]; /**< from beginning of VBT */ 36 } __attribute__((packed)); 37 38 39 struct bdb_header { 40 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ 41 u16 version; /**< decimal */ 42 u16 header_size; /**< in bytes */ 43 u16 bdb_size; /**< in bytes */ 44 }; 45 46 /* strictly speaking, this is a "skip" block, but it has interesting info */ 47 struct vbios_data { 48 u8 type; /* 0 == desktop, 1 == mobile */ 49 u8 relstage; 50 u8 chipset; 51 u8 lvds_present:1; 52 u8 tv_present:1; 53 u8 rsvd2:6; /* finish byte */ 54 u8 rsvd3[4]; 55 u8 signon[155]; 56 u8 copyright[61]; 57 u16 code_segment; 58 u8 dos_boot_mode; 59 u8 bandwidth_percent; 60 u8 rsvd4; /* popup memory size */ 61 u8 resize_pci_bios; 62 u8 rsvd5; /* is crt already on ddc2 */ 63 } __attribute__((packed)); 64 65 /* 66 * There are several types of BIOS data blocks (BDBs), each block has 67 * an ID and size in the first 3 bytes (ID in first, size in next 2). 68 * Known types are listed below. 69 */ 70 #define BDB_GENERAL_FEATURES 1 71 #define BDB_GENERAL_DEFINITIONS 2 72 #define BDB_OLD_TOGGLE_LIST 3 73 #define BDB_MODE_SUPPORT_LIST 4 74 #define BDB_GENERIC_MODE_TABLE 5 75 #define BDB_EXT_MMIO_REGS 6 76 #define BDB_SWF_IO 7 77 #define BDB_SWF_MMIO 8 78 #define BDB_DOT_CLOCK_TABLE 9 79 #define BDB_MODE_REMOVAL_TABLE 10 80 #define BDB_CHILD_DEVICE_TABLE 11 81 #define BDB_DRIVER_FEATURES 12 82 #define BDB_DRIVER_PERSISTENCE 13 83 #define BDB_EXT_TABLE_PTRS 14 84 #define BDB_DOT_CLOCK_OVERRIDE 15 85 #define BDB_DISPLAY_SELECT 16 86 /* 17 rsvd */ 87 #define BDB_DRIVER_ROTATION 18 88 #define BDB_DISPLAY_REMOVE 19 89 #define BDB_OEM_CUSTOM 20 90 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 91 #define BDB_SDVO_LVDS_OPTIONS 22 92 #define BDB_SDVO_PANEL_DTDS 23 93 #define BDB_SDVO_LVDS_PNP_IDS 24 94 #define BDB_SDVO_LVDS_POWER_SEQ 25 95 #define BDB_TV_OPTIONS 26 96 #define BDB_LVDS_OPTIONS 40 97 #define BDB_LVDS_LFP_DATA_PTRS 41 98 #define BDB_LVDS_LFP_DATA 42 99 #define BDB_LVDS_BACKLIGHT 43 100 #define BDB_LVDS_POWER 44 101 #define BDB_SKIP 254 /* VBIOS private block, ignore */ 102 103 struct bdb_general_features { 104 /* bits 1 */ 105 u8 panel_fitting:2; 106 u8 flexaim:1; 107 u8 msg_enable:1; 108 u8 clear_screen:3; 109 u8 color_flip:1; 110 111 /* bits 2 */ 112 u8 download_ext_vbt:1; 113 u8 enable_ssc:1; 114 u8 ssc_freq:1; 115 u8 enable_lfp_on_override:1; 116 u8 disable_ssc_ddt:1; 117 u8 rsvd8:3; /* finish byte */ 118 119 /* bits 3 */ 120 u8 disable_smooth_vision:1; 121 u8 single_dvi:1; 122 u8 rsvd9:6; /* finish byte */ 123 124 /* bits 4 */ 125 u8 legacy_monitor_detect; 126 127 /* bits 5 */ 128 u8 int_crt_support:1; 129 u8 int_tv_support:1; 130 u8 int_efp_support:1; 131 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 132 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 133 u8 rsvd11:3; /* finish byte */ 134 } __attribute__((packed)); 135 136 /* pre-915 */ 137 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 138 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 139 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 140 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 141 142 /* Pre 915 */ 143 #define DEVICE_TYPE_NONE 0x00 144 #define DEVICE_TYPE_CRT 0x01 145 #define DEVICE_TYPE_TV 0x09 146 #define DEVICE_TYPE_EFP 0x12 147 #define DEVICE_TYPE_LFP 0x22 148 /* On 915+ */ 149 #define DEVICE_TYPE_CRT_DPMS 0x6001 150 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 151 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 152 #define DEVICE_TYPE_TV_MACROVISION 0x0289 153 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 154 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 155 #define DEVICE_TYPE_TV_SCART 0x0209 156 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 157 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 158 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 159 #define DEVICE_TYPE_EFP_DVI_I 0x6053 160 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 161 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 162 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 163 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 164 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 165 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 166 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 167 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 168 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 169 170 #define DEVICE_CFG_NONE 0x00 171 #define DEVICE_CFG_12BIT_DVOB 0x01 172 #define DEVICE_CFG_12BIT_DVOC 0x02 173 #define DEVICE_CFG_24BIT_DVOBC 0x09 174 #define DEVICE_CFG_24BIT_DVOCB 0x0a 175 #define DEVICE_CFG_DUAL_DVOB 0x11 176 #define DEVICE_CFG_DUAL_DVOC 0x12 177 #define DEVICE_CFG_DUAL_DVOBC 0x13 178 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 179 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 180 181 #define DEVICE_WIRE_NONE 0x00 182 #define DEVICE_WIRE_DVOB 0x01 183 #define DEVICE_WIRE_DVOC 0x02 184 #define DEVICE_WIRE_DVOBC 0x03 185 #define DEVICE_WIRE_DVOBB 0x05 186 #define DEVICE_WIRE_DVOCC 0x06 187 #define DEVICE_WIRE_DVOB_MASTER 0x0d 188 #define DEVICE_WIRE_DVOC_MASTER 0x0e 189 190 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 191 #define DEVICE_PORT_DVOB 0x01 192 #define DEVICE_PORT_DVOC 0x02 193 194 struct child_device_config { 195 u16 handle; 196 u16 device_type; 197 u8 device_id[10]; /* ascii string */ 198 u16 addin_offset; 199 u8 dvo_port; /* See Device_PORT_* above */ 200 u8 i2c_pin; 201 u8 slave_addr; 202 u8 ddc_pin; 203 u16 edid_ptr; 204 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 205 u8 dvo2_port; 206 u8 i2c2_pin; 207 u8 slave2_addr; 208 u8 ddc2_pin; 209 u8 capabilities; 210 u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 211 u8 dvo2_wiring; 212 u16 extended_type; 213 u8 dvo_function; 214 } __attribute__((packed)); 215 216 217 struct bdb_general_definitions { 218 /* DDC GPIO */ 219 u8 crt_ddc_gmbus_pin; 220 221 /* DPMS bits */ 222 u8 dpms_acpi:1; 223 u8 skip_boot_crt_detect:1; 224 u8 dpms_aim:1; 225 u8 rsvd1:5; /* finish byte */ 226 227 /* boot device bits */ 228 u8 boot_display[2]; 229 u8 child_dev_size; 230 231 /* 232 * Device info: 233 * If TV is present, it'll be at devices[0]. 234 * LVDS will be next, either devices[0] or [1], if present. 235 * On some platforms the number of device is 6. But could be as few as 236 * 4 if both TV and LVDS are missing. 237 * And the device num is related with the size of general definition 238 * block. It is obtained by using the following formula: 239 * number = (block_size - sizeof(bdb_general_definitions))/ 240 * sizeof(child_device_config); 241 */ 242 struct child_device_config devices[0]; 243 }; 244 245 struct bdb_lvds_options { 246 u8 panel_type; 247 u8 rsvd1; 248 /* LVDS capabilities, stored in a dword */ 249 u8 pfit_mode:2; 250 u8 pfit_text_mode_enhanced:1; 251 u8 pfit_gfx_mode_enhanced:1; 252 u8 pfit_ratio_auto:1; 253 u8 pixel_dither:1; 254 u8 lvds_edid:1; 255 u8 rsvd2:1; 256 u8 rsvd4; 257 } __attribute__((packed)); 258 259 struct bdb_lvds_backlight { 260 u8 type:2; 261 u8 pol:1; 262 u8 gpio:3; 263 u8 gmbus:2; 264 u16 freq; 265 u8 minbrightness; 266 u8 i2caddr; 267 u8 brightnesscmd; 268 /*FIXME: more...*/ 269 } __attribute__((packed)); 270 271 /* LFP pointer table contains entries to the struct below */ 272 struct bdb_lvds_lfp_data_ptr { 273 u16 fp_timing_offset; /* offsets are from start of bdb */ 274 u8 fp_table_size; 275 u16 dvo_timing_offset; 276 u8 dvo_table_size; 277 u16 panel_pnp_id_offset; 278 u8 pnp_table_size; 279 } __attribute__((packed)); 280 281 struct bdb_lvds_lfp_data_ptrs { 282 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 283 struct bdb_lvds_lfp_data_ptr ptr[16]; 284 } __attribute__((packed)); 285 286 /* LFP data has 3 blocks per entry */ 287 struct lvds_fp_timing { 288 u16 x_res; 289 u16 y_res; 290 u32 lvds_reg; 291 u32 lvds_reg_val; 292 u32 pp_on_reg; 293 u32 pp_on_reg_val; 294 u32 pp_off_reg; 295 u32 pp_off_reg_val; 296 u32 pp_cycle_reg; 297 u32 pp_cycle_reg_val; 298 u32 pfit_reg; 299 u32 pfit_reg_val; 300 u16 terminator; 301 } __attribute__((packed)); 302 303 struct lvds_dvo_timing { 304 u16 clock; /**< In 10khz */ 305 u8 hactive_lo; 306 u8 hblank_lo; 307 u8 hblank_hi:4; 308 u8 hactive_hi:4; 309 u8 vactive_lo; 310 u8 vblank_lo; 311 u8 vblank_hi:4; 312 u8 vactive_hi:4; 313 u8 hsync_off_lo; 314 u8 hsync_pulse_width; 315 u8 vsync_pulse_width:4; 316 u8 vsync_off:4; 317 u8 rsvd0:6; 318 u8 hsync_off_hi:2; 319 u8 h_image; 320 u8 v_image; 321 u8 max_hv; 322 u8 h_border; 323 u8 v_border; 324 u8 rsvd1:3; 325 u8 digital:2; 326 u8 vsync_positive:1; 327 u8 hsync_positive:1; 328 u8 rsvd2:1; 329 } __attribute__((packed)); 330 331 struct lvds_pnp_id { 332 u16 mfg_name; 333 u16 product_code; 334 u32 serial; 335 u8 mfg_week; 336 u8 mfg_year; 337 } __attribute__((packed)); 338 339 struct bdb_lvds_lfp_data_entry { 340 struct lvds_fp_timing fp_timing; 341 struct lvds_dvo_timing dvo_timing; 342 struct lvds_pnp_id pnp_id; 343 } __attribute__((packed)); 344 345 struct bdb_lvds_lfp_data { 346 struct bdb_lvds_lfp_data_entry data[16]; 347 } __attribute__((packed)); 348 349 struct aimdb_header { 350 char signature[16]; 351 char oem_device[20]; 352 u16 aimdb_version; 353 u16 aimdb_header_size; 354 u16 aimdb_size; 355 } __attribute__((packed)); 356 357 struct aimdb_block { 358 u8 aimdb_id; 359 u16 aimdb_size; 360 } __attribute__((packed)); 361 362 struct vch_panel_data { 363 u16 fp_timing_offset; 364 u8 fp_timing_size; 365 u16 dvo_timing_offset; 366 u8 dvo_timing_size; 367 u16 text_fitting_offset; 368 u8 text_fitting_size; 369 u16 graphics_fitting_offset; 370 u8 graphics_fitting_size; 371 } __attribute__((packed)); 372 373 struct vch_bdb_22 { 374 struct aimdb_block aimdb_block; 375 struct vch_panel_data panels[16]; 376 } __attribute__((packed)); 377 378 struct bdb_sdvo_lvds_options { 379 u8 panel_backlight; 380 u8 h40_set_panel_type; 381 u8 panel_type; 382 u8 ssc_clk_freq; 383 u16 als_low_trip; 384 u16 als_high_trip; 385 u8 sclalarcoeff_tab_row_num; 386 u8 sclalarcoeff_tab_row_size; 387 u8 coefficient[8]; 388 u8 panel_misc_bits_1; 389 u8 panel_misc_bits_2; 390 u8 panel_misc_bits_3; 391 u8 panel_misc_bits_4; 392 } __attribute__((packed)); 393 394 struct bdb_driver_features { 395 u8 boot_dev_algorithm:1; 396 u8 block_display_switch:1; 397 u8 allow_display_switch:1; 398 u8 hotplug_dvo:1; 399 u8 dual_view_zoom:1; 400 u8 int15h_hook:1; 401 u8 sprite_in_clone:1; 402 u8 primary_lfp_id:1; 403 404 u16 boot_mode_x; 405 u16 boot_mode_y; 406 u8 boot_mode_bpp; 407 u8 boot_mode_refresh; 408 409 u16 enable_lfp_primary:1; 410 u16 selective_mode_pruning:1; 411 u16 dual_frequency:1; 412 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 413 u16 nt_clone_support:1; 414 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 415 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 416 u16 cui_aspect_scaling:1; 417 u16 preserve_aspect_ratio:1; 418 u16 sdvo_device_power_down:1; 419 u16 crt_hotplug:1; 420 u16 lvds_config:2; 421 u16 tv_hotplug:1; 422 u16 hdmi_config:2; 423 424 u8 static_display:1; 425 u8 reserved2:7; 426 u16 legacy_crt_max_x; 427 u16 legacy_crt_max_y; 428 u8 legacy_crt_max_refresh; 429 430 u8 hdmi_termination; 431 u8 custom_vbt_version; 432 } __attribute__((packed)); 433 434 extern int psb_intel_init_bios(struct drm_device *dev); 435 extern void psb_intel_destroy_bios(struct drm_device *dev); 436 437 /* 438 * Driver<->VBIOS interaction occurs through scratch bits in 439 * GR18 & SWF*. 440 */ 441 442 /* GR18 bits are set on display switch and hotkey events */ 443 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 444 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 445 #define GR18_HK_NONE (0x0<<3) 446 #define GR18_HK_LFP_STRETCH (0x1<<3) 447 #define GR18_HK_TOGGLE_DISP (0x2<<3) 448 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 449 #define GR18_HK_POPUP_DISABLED (0x6<<3) 450 #define GR18_HK_POPUP_ENABLED (0x7<<3) 451 #define GR18_HK_PFIT (0x8<<3) 452 #define GR18_HK_APM_CHANGE (0xa<<3) 453 #define GR18_HK_MULTIPLE (0xc<<3) 454 #define GR18_USER_INT_EN (1<<2) 455 #define GR18_A0000_FLUSH_EN (1<<1) 456 #define GR18_SMM_EN (1<<0) 457 458 /* Set by driver, cleared by VBIOS */ 459 #define SWF00_YRES_SHIFT 16 460 #define SWF00_XRES_SHIFT 0 461 #define SWF00_RES_MASK 0xffff 462 463 /* Set by VBIOS at boot time and driver at runtime */ 464 #define SWF01_TV2_FORMAT_SHIFT 8 465 #define SWF01_TV1_FORMAT_SHIFT 0 466 #define SWF01_TV_FORMAT_MASK 0xffff 467 468 #define SWF10_VBIOS_BLC_I2C_EN (1<<29) 469 #define SWF10_GTT_OVERRIDE_EN (1<<28) 470 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 471 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 472 #define SWF10_OLD_TOGGLE 0x0 473 #define SWF10_TOGGLE_LIST_1 0x1 474 #define SWF10_TOGGLE_LIST_2 0x2 475 #define SWF10_TOGGLE_LIST_3 0x3 476 #define SWF10_TOGGLE_LIST_4 0x4 477 #define SWF10_PANNING_EN (1<<23) 478 #define SWF10_DRIVER_LOADED (1<<22) 479 #define SWF10_EXTENDED_DESKTOP (1<<21) 480 #define SWF10_EXCLUSIVE_MODE (1<<20) 481 #define SWF10_OVERLAY_EN (1<<19) 482 #define SWF10_PLANEB_HOLDOFF (1<<18) 483 #define SWF10_PLANEA_HOLDOFF (1<<17) 484 #define SWF10_VGA_HOLDOFF (1<<16) 485 #define SWF10_ACTIVE_DISP_MASK 0xffff 486 #define SWF10_PIPEB_LFP2 (1<<15) 487 #define SWF10_PIPEB_EFP2 (1<<14) 488 #define SWF10_PIPEB_TV2 (1<<13) 489 #define SWF10_PIPEB_CRT2 (1<<12) 490 #define SWF10_PIPEB_LFP (1<<11) 491 #define SWF10_PIPEB_EFP (1<<10) 492 #define SWF10_PIPEB_TV (1<<9) 493 #define SWF10_PIPEB_CRT (1<<8) 494 #define SWF10_PIPEA_LFP2 (1<<7) 495 #define SWF10_PIPEA_EFP2 (1<<6) 496 #define SWF10_PIPEA_TV2 (1<<5) 497 #define SWF10_PIPEA_CRT2 (1<<4) 498 #define SWF10_PIPEA_LFP (1<<3) 499 #define SWF10_PIPEA_EFP (1<<2) 500 #define SWF10_PIPEA_TV (1<<1) 501 #define SWF10_PIPEA_CRT (1<<0) 502 503 #define SWF11_MEMORY_SIZE_SHIFT 16 504 #define SWF11_SV_TEST_EN (1<<15) 505 #define SWF11_IS_AGP (1<<14) 506 #define SWF11_DISPLAY_HOLDOFF (1<<13) 507 #define SWF11_DPMS_REDUCED (1<<12) 508 #define SWF11_IS_VBE_MODE (1<<11) 509 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 510 #define SWF11_DPMS_MASK 0x07 511 #define SWF11_DPMS_OFF (1<<2) 512 #define SWF11_DPMS_SUSPEND (1<<1) 513 #define SWF11_DPMS_STANDBY (1<<0) 514 #define SWF11_DPMS_ON 0 515 516 #define SWF14_GFX_PFIT_EN (1<<31) 517 #define SWF14_TEXT_PFIT_EN (1<<30) 518 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ 519 #define SWF14_POPUP_EN (1<<28) 520 #define SWF14_DISPLAY_HOLDOFF (1<<27) 521 #define SWF14_DISP_DETECT_EN (1<<26) 522 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 523 #define SWF14_DRIVER_STATUS (1<<24) 524 #define SWF14_OS_TYPE_WIN9X (1<<23) 525 #define SWF14_OS_TYPE_WINNT (1<<22) 526 /* 21:19 rsvd */ 527 #define SWF14_PM_TYPE_MASK 0x00070000 528 #define SWF14_PM_ACPI_VIDEO (0x4 << 16) 529 #define SWF14_PM_ACPI (0x3 << 16) 530 #define SWF14_PM_APM_12 (0x2 << 16) 531 #define SWF14_PM_APM_11 (0x1 << 16) 532 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 533 /* if GR18 indicates a display switch */ 534 #define SWF14_DS_PIPEB_LFP2_EN (1<<15) 535 #define SWF14_DS_PIPEB_EFP2_EN (1<<14) 536 #define SWF14_DS_PIPEB_TV2_EN (1<<13) 537 #define SWF14_DS_PIPEB_CRT2_EN (1<<12) 538 #define SWF14_DS_PIPEB_LFP_EN (1<<11) 539 #define SWF14_DS_PIPEB_EFP_EN (1<<10) 540 #define SWF14_DS_PIPEB_TV_EN (1<<9) 541 #define SWF14_DS_PIPEB_CRT_EN (1<<8) 542 #define SWF14_DS_PIPEA_LFP2_EN (1<<7) 543 #define SWF14_DS_PIPEA_EFP2_EN (1<<6) 544 #define SWF14_DS_PIPEA_TV2_EN (1<<5) 545 #define SWF14_DS_PIPEA_CRT2_EN (1<<4) 546 #define SWF14_DS_PIPEA_LFP_EN (1<<3) 547 #define SWF14_DS_PIPEA_EFP_EN (1<<2) 548 #define SWF14_DS_PIPEA_TV_EN (1<<1) 549 #define SWF14_DS_PIPEA_CRT_EN (1<<0) 550 /* if GR18 indicates a panel fitting request */ 551 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 552 /* if GR18 indicates an APM change request */ 553 #define SWF14_APM_HIBERNATE 0x4 554 #define SWF14_APM_SUSPEND 0x3 555 #define SWF14_APM_STANDBY 0x1 556 #define SWF14_APM_RESTORE 0x0 557 558 /* Add the device class for LFP, TV, HDMI */ 559 #define DEVICE_TYPE_INT_LFP 0x1022 560 #define DEVICE_TYPE_INT_TV 0x1009 561 #define DEVICE_TYPE_HDMI 0x60D2 562 #define DEVICE_TYPE_DP 0x68C6 563 #define DEVICE_TYPE_eDP 0x78C6 564 565 /* define the DVO port for HDMI output type */ 566 #define DVO_B 1 567 #define DVO_C 2 568 #define DVO_D 3 569 570 /* define the PORT for DP output type */ 571 #define PORT_IDPB 7 572 #define PORT_IDPC 8 573 #define PORT_IDPD 9 574 575 #endif /* _I830_BIOS_H_ */ 576