1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2007, Intel Corporation. 4 * All Rights Reserved. 5 * 6 * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com> 7 * Alan Cox <alan@linux.intel.com> 8 */ 9 10 #include "gem.h" /* TODO: for struct psb_gem_object, see psb_gtt_restore() */ 11 #include "psb_drv.h" 12 13 14 /* 15 * GTT resource allocator - manage page mappings in GTT space 16 */ 17 18 int psb_gtt_allocate_resource(struct drm_psb_private *pdev, struct resource *res, 19 const char *name, resource_size_t size, resource_size_t align, 20 bool stolen, u32 *offset) 21 { 22 struct resource *root = pdev->gtt_mem; 23 resource_size_t start, end; 24 int ret; 25 26 if (stolen) { 27 /* The start of the GTT is backed by stolen pages. */ 28 start = root->start; 29 end = root->start + pdev->gtt.stolen_size - 1; 30 } else { 31 /* The rest is backed by system pages. */ 32 start = root->start + pdev->gtt.stolen_size; 33 end = root->end; 34 } 35 36 res->name = name; 37 ret = allocate_resource(root, res, size, start, end, align, NULL, NULL); 38 if (ret) 39 return ret; 40 *offset = res->start - root->start; 41 42 return 0; 43 } 44 45 /** 46 * psb_gtt_mask_pte - generate GTT pte entry 47 * @pfn: page number to encode 48 * @type: type of memory in the GTT 49 * 50 * Set the GTT entry for the appropriate memory type. 51 */ 52 static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type) 53 { 54 uint32_t mask = PSB_PTE_VALID; 55 56 /* Ensure we explode rather than put an invalid low mapping of 57 a high mapping page into the gtt */ 58 BUG_ON(pfn & ~(0xFFFFFFFF >> PAGE_SHIFT)); 59 60 if (type & PSB_MMU_CACHED_MEMORY) 61 mask |= PSB_PTE_CACHED; 62 if (type & PSB_MMU_RO_MEMORY) 63 mask |= PSB_PTE_RO; 64 if (type & PSB_MMU_WO_MEMORY) 65 mask |= PSB_PTE_WO; 66 67 return (pfn << PAGE_SHIFT) | mask; 68 } 69 70 static u32 __iomem *psb_gtt_entry(struct drm_psb_private *pdev, const struct resource *res) 71 { 72 unsigned long offset = res->start - pdev->gtt_mem->start; 73 74 return pdev->gtt_map + (offset >> PAGE_SHIFT); 75 } 76 77 /* 78 * Take our preallocated GTT range and insert the GEM object into 79 * the GTT. This is protected via the gtt mutex which the caller 80 * must hold. 81 */ 82 void psb_gtt_insert_pages(struct drm_psb_private *pdev, const struct resource *res, 83 struct page **pages) 84 { 85 resource_size_t npages, i; 86 u32 __iomem *gtt_slot; 87 u32 pte; 88 89 /* Write our page entries into the GTT itself */ 90 91 npages = resource_size(res) >> PAGE_SHIFT; 92 gtt_slot = psb_gtt_entry(pdev, res); 93 94 for (i = 0; i < npages; ++i, ++gtt_slot) { 95 pte = psb_gtt_mask_pte(page_to_pfn(pages[i]), PSB_MMU_CACHED_MEMORY); 96 iowrite32(pte, gtt_slot); 97 } 98 99 /* Make sure all the entries are set before we return */ 100 ioread32(gtt_slot - 1); 101 } 102 103 /* 104 * Remove a preallocated GTT range from the GTT. Overwrite all the 105 * page table entries with the dummy page. This is protected via the gtt 106 * mutex which the caller must hold. 107 */ 108 void psb_gtt_remove_pages(struct drm_psb_private *pdev, const struct resource *res) 109 { 110 resource_size_t npages, i; 111 u32 __iomem *gtt_slot; 112 u32 pte; 113 114 /* Install scratch page for the resource */ 115 116 pte = psb_gtt_mask_pte(page_to_pfn(pdev->scratch_page), PSB_MMU_CACHED_MEMORY); 117 118 npages = resource_size(res) >> PAGE_SHIFT; 119 gtt_slot = psb_gtt_entry(pdev, res); 120 121 for (i = 0; i < npages; ++i, ++gtt_slot) 122 iowrite32(pte, gtt_slot); 123 124 /* Make sure all the entries are set before we return */ 125 ioread32(gtt_slot - 1); 126 } 127 128 static void psb_gtt_alloc(struct drm_device *dev) 129 { 130 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 131 init_rwsem(&dev_priv->gtt.sem); 132 } 133 134 void psb_gtt_takedown(struct drm_device *dev) 135 { 136 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 137 struct pci_dev *pdev = to_pci_dev(dev->dev); 138 139 if (dev_priv->gtt_map) { 140 iounmap(dev_priv->gtt_map); 141 dev_priv->gtt_map = NULL; 142 } 143 if (dev_priv->gtt_initialized) { 144 pci_write_config_word(pdev, PSB_GMCH_CTRL, 145 dev_priv->gmch_ctrl); 146 PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL); 147 (void) PSB_RVDC32(PSB_PGETBL_CTL); 148 } 149 if (dev_priv->vram_addr) 150 iounmap(dev_priv->gtt_map); 151 } 152 153 int psb_gtt_init(struct drm_device *dev, int resume) 154 { 155 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 156 struct pci_dev *pdev = to_pci_dev(dev->dev); 157 unsigned gtt_pages; 158 unsigned long stolen_size, vram_stolen_size; 159 unsigned i, num_pages; 160 unsigned pfn_base; 161 struct psb_gtt *pg; 162 163 int ret = 0; 164 uint32_t pte; 165 166 if (!resume) { 167 mutex_init(&dev_priv->gtt_mutex); 168 mutex_init(&dev_priv->mmap_mutex); 169 psb_gtt_alloc(dev); 170 } 171 172 pg = &dev_priv->gtt; 173 174 /* Enable the GTT */ 175 pci_read_config_word(pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl); 176 pci_write_config_word(pdev, PSB_GMCH_CTRL, 177 dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED); 178 179 dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); 180 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); 181 (void) PSB_RVDC32(PSB_PGETBL_CTL); 182 183 /* The root resource we allocate address space from */ 184 dev_priv->gtt_initialized = 1; 185 186 pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK; 187 188 /* 189 * The video mmu has a hw bug when accessing 0x0D0000000. 190 * Make gatt start at 0x0e000,0000. This doesn't actually 191 * matter for us but may do if the video acceleration ever 192 * gets opened up. 193 */ 194 pg->mmu_gatt_start = 0xE0000000; 195 196 pg->gtt_start = pci_resource_start(pdev, PSB_GTT_RESOURCE); 197 gtt_pages = pci_resource_len(pdev, PSB_GTT_RESOURCE) 198 >> PAGE_SHIFT; 199 /* CDV doesn't report this. In which case the system has 64 gtt pages */ 200 if (pg->gtt_start == 0 || gtt_pages == 0) { 201 dev_dbg(dev->dev, "GTT PCI BAR not initialized.\n"); 202 gtt_pages = 64; 203 pg->gtt_start = dev_priv->pge_ctl; 204 } 205 206 pg->gatt_start = pci_resource_start(pdev, PSB_GATT_RESOURCE); 207 pg->gatt_pages = pci_resource_len(pdev, PSB_GATT_RESOURCE) 208 >> PAGE_SHIFT; 209 dev_priv->gtt_mem = &pdev->resource[PSB_GATT_RESOURCE]; 210 211 if (pg->gatt_pages == 0 || pg->gatt_start == 0) { 212 static struct resource fudge; /* Preferably peppermint */ 213 /* This can occur on CDV systems. Fudge it in this case. 214 We really don't care what imaginary space is being allocated 215 at this point */ 216 dev_dbg(dev->dev, "GATT PCI BAR not initialized.\n"); 217 pg->gatt_start = 0x40000000; 218 pg->gatt_pages = (128 * 1024 * 1024) >> PAGE_SHIFT; 219 /* This is a little confusing but in fact the GTT is providing 220 a view from the GPU into memory and not vice versa. As such 221 this is really allocating space that is not the same as the 222 CPU address space on CDV */ 223 fudge.start = 0x40000000; 224 fudge.end = 0x40000000 + 128 * 1024 * 1024 - 1; 225 fudge.name = "fudge"; 226 fudge.flags = IORESOURCE_MEM; 227 dev_priv->gtt_mem = &fudge; 228 } 229 230 pci_read_config_dword(pdev, PSB_BSM, &dev_priv->stolen_base); 231 vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base 232 - PAGE_SIZE; 233 234 stolen_size = vram_stolen_size; 235 236 dev_dbg(dev->dev, "Stolen memory base 0x%x, size %luK\n", 237 dev_priv->stolen_base, vram_stolen_size / 1024); 238 239 if (resume && (gtt_pages != pg->gtt_pages) && 240 (stolen_size != pg->stolen_size)) { 241 dev_err(dev->dev, "GTT resume error.\n"); 242 ret = -EINVAL; 243 goto out_err; 244 } 245 246 pg->gtt_pages = gtt_pages; 247 pg->stolen_size = stolen_size; 248 dev_priv->vram_stolen_size = vram_stolen_size; 249 250 /* 251 * Map the GTT and the stolen memory area 252 */ 253 if (!resume) 254 dev_priv->gtt_map = ioremap(pg->gtt_phys_start, 255 gtt_pages << PAGE_SHIFT); 256 if (!dev_priv->gtt_map) { 257 dev_err(dev->dev, "Failure to map gtt.\n"); 258 ret = -ENOMEM; 259 goto out_err; 260 } 261 262 if (!resume) 263 dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base, 264 stolen_size); 265 266 if (!dev_priv->vram_addr) { 267 dev_err(dev->dev, "Failure to map stolen base.\n"); 268 ret = -ENOMEM; 269 goto out_err; 270 } 271 272 /* 273 * Insert vram stolen pages into the GTT 274 */ 275 276 pfn_base = dev_priv->stolen_base >> PAGE_SHIFT; 277 num_pages = vram_stolen_size >> PAGE_SHIFT; 278 dev_dbg(dev->dev, "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n", 279 num_pages, pfn_base << PAGE_SHIFT, 0); 280 for (i = 0; i < num_pages; ++i) { 281 pte = psb_gtt_mask_pte(pfn_base + i, PSB_MMU_CACHED_MEMORY); 282 iowrite32(pte, dev_priv->gtt_map + i); 283 } 284 285 /* 286 * Init rest of GTT to the scratch page to avoid accidents or scribbles 287 */ 288 289 pfn_base = page_to_pfn(dev_priv->scratch_page); 290 pte = psb_gtt_mask_pte(pfn_base, PSB_MMU_CACHED_MEMORY); 291 for (; i < gtt_pages; ++i) 292 iowrite32(pte, dev_priv->gtt_map + i); 293 294 (void) ioread32(dev_priv->gtt_map + i - 1); 295 return 0; 296 297 out_err: 298 psb_gtt_takedown(dev); 299 return ret; 300 } 301 302 int psb_gtt_restore(struct drm_device *dev) 303 { 304 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 305 struct resource *r = dev_priv->gtt_mem->child; 306 struct psb_gem_object *pobj; 307 unsigned int restored = 0, total = 0, size = 0; 308 309 /* On resume, the gtt_mutex is already initialized */ 310 mutex_lock(&dev_priv->gtt_mutex); 311 psb_gtt_init(dev, 1); 312 313 while (r != NULL) { 314 /* 315 * TODO: GTT restoration needs a refactoring, so that we don't have to touch 316 * struct psb_gem_object here. The type represents a GEM object and is 317 * not related to the GTT itself. 318 */ 319 pobj = container_of(r, struct psb_gem_object, resource); 320 if (pobj->pages) { 321 psb_gtt_insert_pages(dev_priv, &pobj->resource, pobj->pages); 322 size += pobj->resource.end - pobj->resource.start; 323 restored++; 324 } 325 r = r->sibling; 326 total++; 327 } 328 mutex_unlock(&dev_priv->gtt_mutex); 329 DRM_DEBUG_DRIVER("Restored %u of %u gtt ranges (%u KB)", restored, 330 total, (size / 1024)); 331 332 return 0; 333 } 334