1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 * Patrik Jakobsson <patrik.r.jakobsson@gmail.com> 20 */ 21 22 #include <drm/drmP.h> 23 #include "gma_display.h" 24 #include "psb_intel_drv.h" 25 #include "psb_intel_reg.h" 26 #include "psb_drv.h" 27 #include "framebuffer.h" 28 29 /** 30 * Returns whether any output on the specified pipe is of the specified type 31 */ 32 bool gma_pipe_has_type(struct drm_crtc *crtc, int type) 33 { 34 struct drm_device *dev = crtc->dev; 35 struct drm_mode_config *mode_config = &dev->mode_config; 36 struct drm_connector *l_entry; 37 38 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 39 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { 40 struct gma_encoder *gma_encoder = 41 gma_attached_encoder(l_entry); 42 if (gma_encoder->type == type) 43 return true; 44 } 45 } 46 47 return false; 48 } 49 50 void gma_wait_for_vblank(struct drm_device *dev) 51 { 52 /* Wait for 20ms, i.e. one cycle at 50hz. */ 53 mdelay(20); 54 } 55 56 int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y, 57 struct drm_framebuffer *old_fb) 58 { 59 struct drm_device *dev = crtc->dev; 60 struct drm_psb_private *dev_priv = dev->dev_private; 61 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 62 struct drm_framebuffer *fb = crtc->primary->fb; 63 struct psb_framebuffer *psbfb = to_psb_fb(fb); 64 int pipe = gma_crtc->pipe; 65 const struct psb_offset *map = &dev_priv->regmap[pipe]; 66 unsigned long start, offset; 67 u32 dspcntr; 68 int ret = 0; 69 70 if (!gma_power_begin(dev, true)) 71 return 0; 72 73 /* no fb bound */ 74 if (!fb) { 75 dev_err(dev->dev, "No FB bound\n"); 76 goto gma_pipe_cleaner; 77 } 78 79 /* We are displaying this buffer, make sure it is actually loaded 80 into the GTT */ 81 ret = psb_gtt_pin(psbfb->gtt); 82 if (ret < 0) 83 goto gma_pipe_set_base_exit; 84 start = psbfb->gtt->offset; 85 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; 86 87 REG_WRITE(map->stride, fb->pitches[0]); 88 89 dspcntr = REG_READ(map->cntr); 90 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 91 92 switch (fb->format->cpp[0] * 8) { 93 case 8: 94 dspcntr |= DISPPLANE_8BPP; 95 break; 96 case 16: 97 if (fb->format->depth == 15) 98 dspcntr |= DISPPLANE_15_16BPP; 99 else 100 dspcntr |= DISPPLANE_16BPP; 101 break; 102 case 24: 103 case 32: 104 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 105 break; 106 default: 107 dev_err(dev->dev, "Unknown color depth\n"); 108 ret = -EINVAL; 109 goto gma_pipe_set_base_exit; 110 } 111 REG_WRITE(map->cntr, dspcntr); 112 113 dev_dbg(dev->dev, 114 "Writing base %08lX %08lX %d %d\n", start, offset, x, y); 115 116 /* FIXME: Investigate whether this really is the base for psb and why 117 the linear offset is named base for the other chips. map->surf 118 should be the base and map->linoff the offset for all chips */ 119 if (IS_PSB(dev)) { 120 REG_WRITE(map->base, offset + start); 121 REG_READ(map->base); 122 } else { 123 REG_WRITE(map->base, offset); 124 REG_READ(map->base); 125 REG_WRITE(map->surf, start); 126 REG_READ(map->surf); 127 } 128 129 gma_pipe_cleaner: 130 /* If there was a previous display we can now unpin it */ 131 if (old_fb) 132 psb_gtt_unpin(to_psb_fb(old_fb)->gtt); 133 134 gma_pipe_set_base_exit: 135 gma_power_end(dev); 136 return ret; 137 } 138 139 /* Loads the palette/gamma unit for the CRTC with the prepared values */ 140 void gma_crtc_load_lut(struct drm_crtc *crtc) 141 { 142 struct drm_device *dev = crtc->dev; 143 struct drm_psb_private *dev_priv = dev->dev_private; 144 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 145 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; 146 int palreg = map->palette; 147 int i; 148 149 /* The clocks have to be on to load the palette. */ 150 if (!crtc->enabled) 151 return; 152 153 if (gma_power_begin(dev, false)) { 154 for (i = 0; i < 256; i++) { 155 REG_WRITE(palreg + 4 * i, 156 ((gma_crtc->lut_r[i] + 157 gma_crtc->lut_adj[i]) << 16) | 158 ((gma_crtc->lut_g[i] + 159 gma_crtc->lut_adj[i]) << 8) | 160 (gma_crtc->lut_b[i] + 161 gma_crtc->lut_adj[i])); 162 } 163 gma_power_end(dev); 164 } else { 165 for (i = 0; i < 256; i++) { 166 /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */ 167 dev_priv->regs.pipe[0].palette[i] = 168 ((gma_crtc->lut_r[i] + 169 gma_crtc->lut_adj[i]) << 16) | 170 ((gma_crtc->lut_g[i] + 171 gma_crtc->lut_adj[i]) << 8) | 172 (gma_crtc->lut_b[i] + 173 gma_crtc->lut_adj[i]); 174 } 175 176 } 177 } 178 179 int gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, 180 u32 size) 181 { 182 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 183 int i; 184 185 for (i = 0; i < size; i++) { 186 gma_crtc->lut_r[i] = red[i] >> 8; 187 gma_crtc->lut_g[i] = green[i] >> 8; 188 gma_crtc->lut_b[i] = blue[i] >> 8; 189 } 190 191 gma_crtc_load_lut(crtc); 192 193 return 0; 194 } 195 196 /** 197 * Sets the power management mode of the pipe and plane. 198 * 199 * This code should probably grow support for turning the cursor off and back 200 * on appropriately at the same time as we're turning the pipe off/on. 201 */ 202 void gma_crtc_dpms(struct drm_crtc *crtc, int mode) 203 { 204 struct drm_device *dev = crtc->dev; 205 struct drm_psb_private *dev_priv = dev->dev_private; 206 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 207 int pipe = gma_crtc->pipe; 208 const struct psb_offset *map = &dev_priv->regmap[pipe]; 209 u32 temp; 210 211 /* XXX: When our outputs are all unaware of DPMS modes other than off 212 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 213 */ 214 215 if (IS_CDV(dev)) 216 dev_priv->ops->disable_sr(dev); 217 218 switch (mode) { 219 case DRM_MODE_DPMS_ON: 220 case DRM_MODE_DPMS_STANDBY: 221 case DRM_MODE_DPMS_SUSPEND: 222 if (gma_crtc->active) 223 break; 224 225 gma_crtc->active = true; 226 227 /* Enable the DPLL */ 228 temp = REG_READ(map->dpll); 229 if ((temp & DPLL_VCO_ENABLE) == 0) { 230 REG_WRITE(map->dpll, temp); 231 REG_READ(map->dpll); 232 /* Wait for the clocks to stabilize. */ 233 udelay(150); 234 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 235 REG_READ(map->dpll); 236 /* Wait for the clocks to stabilize. */ 237 udelay(150); 238 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 239 REG_READ(map->dpll); 240 /* Wait for the clocks to stabilize. */ 241 udelay(150); 242 } 243 244 /* Enable the plane */ 245 temp = REG_READ(map->cntr); 246 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 247 REG_WRITE(map->cntr, 248 temp | DISPLAY_PLANE_ENABLE); 249 /* Flush the plane changes */ 250 REG_WRITE(map->base, REG_READ(map->base)); 251 } 252 253 udelay(150); 254 255 /* Enable the pipe */ 256 temp = REG_READ(map->conf); 257 if ((temp & PIPEACONF_ENABLE) == 0) 258 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); 259 260 temp = REG_READ(map->status); 261 temp &= ~(0xFFFF); 262 temp |= PIPE_FIFO_UNDERRUN; 263 REG_WRITE(map->status, temp); 264 REG_READ(map->status); 265 266 gma_crtc_load_lut(crtc); 267 268 /* Give the overlay scaler a chance to enable 269 * if it's on this pipe */ 270 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 271 break; 272 case DRM_MODE_DPMS_OFF: 273 if (!gma_crtc->active) 274 break; 275 276 gma_crtc->active = false; 277 278 /* Give the overlay scaler a chance to disable 279 * if it's on this pipe */ 280 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 281 282 /* Disable the VGA plane that we never use */ 283 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 284 285 /* Turn off vblank interrupts */ 286 drm_crtc_vblank_off(crtc); 287 288 /* Wait for vblank for the disable to take effect */ 289 gma_wait_for_vblank(dev); 290 291 /* Disable plane */ 292 temp = REG_READ(map->cntr); 293 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 294 REG_WRITE(map->cntr, 295 temp & ~DISPLAY_PLANE_ENABLE); 296 /* Flush the plane changes */ 297 REG_WRITE(map->base, REG_READ(map->base)); 298 REG_READ(map->base); 299 } 300 301 /* Disable pipe */ 302 temp = REG_READ(map->conf); 303 if ((temp & PIPEACONF_ENABLE) != 0) { 304 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); 305 REG_READ(map->conf); 306 } 307 308 /* Wait for vblank for the disable to take effect. */ 309 gma_wait_for_vblank(dev); 310 311 udelay(150); 312 313 /* Disable DPLL */ 314 temp = REG_READ(map->dpll); 315 if ((temp & DPLL_VCO_ENABLE) != 0) { 316 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); 317 REG_READ(map->dpll); 318 } 319 320 /* Wait for the clocks to turn off. */ 321 udelay(150); 322 break; 323 } 324 325 if (IS_CDV(dev)) 326 dev_priv->ops->update_wm(dev, crtc); 327 328 /* Set FIFO watermarks */ 329 REG_WRITE(DSPARB, 0x3F3E); 330 } 331 332 int gma_crtc_cursor_set(struct drm_crtc *crtc, 333 struct drm_file *file_priv, 334 uint32_t handle, 335 uint32_t width, uint32_t height) 336 { 337 struct drm_device *dev = crtc->dev; 338 struct drm_psb_private *dev_priv = dev->dev_private; 339 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 340 int pipe = gma_crtc->pipe; 341 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; 342 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; 343 uint32_t temp; 344 size_t addr = 0; 345 struct gtt_range *gt; 346 struct gtt_range *cursor_gt = gma_crtc->cursor_gt; 347 struct drm_gem_object *obj; 348 void *tmp_dst, *tmp_src; 349 int ret = 0, i, cursor_pages; 350 351 /* If we didn't get a handle then turn the cursor off */ 352 if (!handle) { 353 temp = CURSOR_MODE_DISABLE; 354 if (gma_power_begin(dev, false)) { 355 REG_WRITE(control, temp); 356 REG_WRITE(base, 0); 357 gma_power_end(dev); 358 } 359 360 /* Unpin the old GEM object */ 361 if (gma_crtc->cursor_obj) { 362 gt = container_of(gma_crtc->cursor_obj, 363 struct gtt_range, gem); 364 psb_gtt_unpin(gt); 365 drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj); 366 gma_crtc->cursor_obj = NULL; 367 } 368 return 0; 369 } 370 371 /* Currently we only support 64x64 cursors */ 372 if (width != 64 || height != 64) { 373 dev_dbg(dev->dev, "We currently only support 64x64 cursors\n"); 374 return -EINVAL; 375 } 376 377 obj = drm_gem_object_lookup(file_priv, handle); 378 if (!obj) { 379 ret = -ENOENT; 380 goto unlock; 381 } 382 383 if (obj->size < width * height * 4) { 384 dev_dbg(dev->dev, "Buffer is too small\n"); 385 ret = -ENOMEM; 386 goto unref_cursor; 387 } 388 389 gt = container_of(obj, struct gtt_range, gem); 390 391 /* Pin the memory into the GTT */ 392 ret = psb_gtt_pin(gt); 393 if (ret) { 394 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); 395 goto unref_cursor; 396 } 397 398 if (dev_priv->ops->cursor_needs_phys) { 399 if (cursor_gt == NULL) { 400 dev_err(dev->dev, "No hardware cursor mem available"); 401 ret = -ENOMEM; 402 goto unref_cursor; 403 } 404 405 /* Prevent overflow */ 406 if (gt->npage > 4) 407 cursor_pages = 4; 408 else 409 cursor_pages = gt->npage; 410 411 /* Copy the cursor to cursor mem */ 412 tmp_dst = dev_priv->vram_addr + cursor_gt->offset; 413 for (i = 0; i < cursor_pages; i++) { 414 tmp_src = kmap(gt->pages[i]); 415 memcpy(tmp_dst, tmp_src, PAGE_SIZE); 416 kunmap(gt->pages[i]); 417 tmp_dst += PAGE_SIZE; 418 } 419 420 addr = gma_crtc->cursor_addr; 421 } else { 422 addr = gt->offset; 423 gma_crtc->cursor_addr = addr; 424 } 425 426 temp = 0; 427 /* set the pipe for the cursor */ 428 temp |= (pipe << 28); 429 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 430 431 if (gma_power_begin(dev, false)) { 432 REG_WRITE(control, temp); 433 REG_WRITE(base, addr); 434 gma_power_end(dev); 435 } 436 437 /* unpin the old bo */ 438 if (gma_crtc->cursor_obj) { 439 gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem); 440 psb_gtt_unpin(gt); 441 drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj); 442 } 443 444 gma_crtc->cursor_obj = obj; 445 unlock: 446 return ret; 447 448 unref_cursor: 449 drm_gem_object_unreference_unlocked(obj); 450 return ret; 451 } 452 453 int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 454 { 455 struct drm_device *dev = crtc->dev; 456 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 457 int pipe = gma_crtc->pipe; 458 uint32_t temp = 0; 459 uint32_t addr; 460 461 if (x < 0) { 462 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 463 x = -x; 464 } 465 if (y < 0) { 466 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 467 y = -y; 468 } 469 470 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 471 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 472 473 addr = gma_crtc->cursor_addr; 474 475 if (gma_power_begin(dev, false)) { 476 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 477 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); 478 gma_power_end(dev); 479 } 480 return 0; 481 } 482 483 void gma_crtc_prepare(struct drm_crtc *crtc) 484 { 485 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 486 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 487 } 488 489 void gma_crtc_commit(struct drm_crtc *crtc) 490 { 491 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 492 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 493 } 494 495 void gma_crtc_disable(struct drm_crtc *crtc) 496 { 497 struct gtt_range *gt; 498 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 499 500 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 501 502 if (crtc->primary->fb) { 503 gt = to_psb_fb(crtc->primary->fb)->gtt; 504 psb_gtt_unpin(gt); 505 } 506 } 507 508 void gma_crtc_destroy(struct drm_crtc *crtc) 509 { 510 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 511 512 kfree(gma_crtc->crtc_state); 513 drm_crtc_cleanup(crtc); 514 kfree(gma_crtc); 515 } 516 517 int gma_crtc_set_config(struct drm_mode_set *set) 518 { 519 struct drm_device *dev = set->crtc->dev; 520 struct drm_psb_private *dev_priv = dev->dev_private; 521 int ret; 522 523 if (!dev_priv->rpm_enabled) 524 return drm_crtc_helper_set_config(set); 525 526 pm_runtime_forbid(&dev->pdev->dev); 527 ret = drm_crtc_helper_set_config(set); 528 pm_runtime_allow(&dev->pdev->dev); 529 530 return ret; 531 } 532 533 /** 534 * Save HW states of given crtc 535 */ 536 void gma_crtc_save(struct drm_crtc *crtc) 537 { 538 struct drm_device *dev = crtc->dev; 539 struct drm_psb_private *dev_priv = dev->dev_private; 540 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 541 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; 542 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; 543 uint32_t palette_reg; 544 int i; 545 546 if (!crtc_state) { 547 dev_err(dev->dev, "No CRTC state found\n"); 548 return; 549 } 550 551 crtc_state->saveDSPCNTR = REG_READ(map->cntr); 552 crtc_state->savePIPECONF = REG_READ(map->conf); 553 crtc_state->savePIPESRC = REG_READ(map->src); 554 crtc_state->saveFP0 = REG_READ(map->fp0); 555 crtc_state->saveFP1 = REG_READ(map->fp1); 556 crtc_state->saveDPLL = REG_READ(map->dpll); 557 crtc_state->saveHTOTAL = REG_READ(map->htotal); 558 crtc_state->saveHBLANK = REG_READ(map->hblank); 559 crtc_state->saveHSYNC = REG_READ(map->hsync); 560 crtc_state->saveVTOTAL = REG_READ(map->vtotal); 561 crtc_state->saveVBLANK = REG_READ(map->vblank); 562 crtc_state->saveVSYNC = REG_READ(map->vsync); 563 crtc_state->saveDSPSTRIDE = REG_READ(map->stride); 564 565 /* NOTE: DSPSIZE DSPPOS only for psb */ 566 crtc_state->saveDSPSIZE = REG_READ(map->size); 567 crtc_state->saveDSPPOS = REG_READ(map->pos); 568 569 crtc_state->saveDSPBASE = REG_READ(map->base); 570 571 palette_reg = map->palette; 572 for (i = 0; i < 256; ++i) 573 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); 574 } 575 576 /** 577 * Restore HW states of given crtc 578 */ 579 void gma_crtc_restore(struct drm_crtc *crtc) 580 { 581 struct drm_device *dev = crtc->dev; 582 struct drm_psb_private *dev_priv = dev->dev_private; 583 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 584 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; 585 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; 586 uint32_t palette_reg; 587 int i; 588 589 if (!crtc_state) { 590 dev_err(dev->dev, "No crtc state\n"); 591 return; 592 } 593 594 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { 595 REG_WRITE(map->dpll, 596 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); 597 REG_READ(map->dpll); 598 udelay(150); 599 } 600 601 REG_WRITE(map->fp0, crtc_state->saveFP0); 602 REG_READ(map->fp0); 603 604 REG_WRITE(map->fp1, crtc_state->saveFP1); 605 REG_READ(map->fp1); 606 607 REG_WRITE(map->dpll, crtc_state->saveDPLL); 608 REG_READ(map->dpll); 609 udelay(150); 610 611 REG_WRITE(map->htotal, crtc_state->saveHTOTAL); 612 REG_WRITE(map->hblank, crtc_state->saveHBLANK); 613 REG_WRITE(map->hsync, crtc_state->saveHSYNC); 614 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); 615 REG_WRITE(map->vblank, crtc_state->saveVBLANK); 616 REG_WRITE(map->vsync, crtc_state->saveVSYNC); 617 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); 618 619 REG_WRITE(map->size, crtc_state->saveDSPSIZE); 620 REG_WRITE(map->pos, crtc_state->saveDSPPOS); 621 622 REG_WRITE(map->src, crtc_state->savePIPESRC); 623 REG_WRITE(map->base, crtc_state->saveDSPBASE); 624 REG_WRITE(map->conf, crtc_state->savePIPECONF); 625 626 gma_wait_for_vblank(dev); 627 628 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); 629 REG_WRITE(map->base, crtc_state->saveDSPBASE); 630 631 gma_wait_for_vblank(dev); 632 633 palette_reg = map->palette; 634 for (i = 0; i < 256; ++i) 635 REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]); 636 } 637 638 void gma_encoder_prepare(struct drm_encoder *encoder) 639 { 640 const struct drm_encoder_helper_funcs *encoder_funcs = 641 encoder->helper_private; 642 /* lvds has its own version of prepare see psb_intel_lvds_prepare */ 643 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 644 } 645 646 void gma_encoder_commit(struct drm_encoder *encoder) 647 { 648 const struct drm_encoder_helper_funcs *encoder_funcs = 649 encoder->helper_private; 650 /* lvds has its own version of commit see psb_intel_lvds_commit */ 651 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 652 } 653 654 void gma_encoder_destroy(struct drm_encoder *encoder) 655 { 656 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 657 658 drm_encoder_cleanup(encoder); 659 kfree(intel_encoder); 660 } 661 662 /* Currently there is only a 1:1 mapping of encoders and connectors */ 663 struct drm_encoder *gma_best_encoder(struct drm_connector *connector) 664 { 665 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 666 667 return &gma_encoder->base; 668 } 669 670 void gma_connector_attach_encoder(struct gma_connector *connector, 671 struct gma_encoder *encoder) 672 { 673 connector->encoder = encoder; 674 drm_mode_connector_attach_encoder(&connector->base, 675 &encoder->base); 676 } 677 678 #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; } 679 680 bool gma_pll_is_valid(struct drm_crtc *crtc, 681 const struct gma_limit_t *limit, 682 struct gma_clock_t *clock) 683 { 684 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 685 GMA_PLL_INVALID("p1 out of range"); 686 if (clock->p < limit->p.min || limit->p.max < clock->p) 687 GMA_PLL_INVALID("p out of range"); 688 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 689 GMA_PLL_INVALID("m2 out of range"); 690 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 691 GMA_PLL_INVALID("m1 out of range"); 692 /* On CDV m1 is always 0 */ 693 if (clock->m1 <= clock->m2 && clock->m1 != 0) 694 GMA_PLL_INVALID("m1 <= m2 && m1 != 0"); 695 if (clock->m < limit->m.min || limit->m.max < clock->m) 696 GMA_PLL_INVALID("m out of range"); 697 if (clock->n < limit->n.min || limit->n.max < clock->n) 698 GMA_PLL_INVALID("n out of range"); 699 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 700 GMA_PLL_INVALID("vco out of range"); 701 /* XXX: We may need to be checking "Dot clock" 702 * depending on the multiplier, connector, etc., 703 * rather than just a single range. 704 */ 705 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 706 GMA_PLL_INVALID("dot out of range"); 707 708 return true; 709 } 710 711 bool gma_find_best_pll(const struct gma_limit_t *limit, 712 struct drm_crtc *crtc, int target, int refclk, 713 struct gma_clock_t *best_clock) 714 { 715 struct drm_device *dev = crtc->dev; 716 const struct gma_clock_funcs *clock_funcs = 717 to_gma_crtc(crtc)->clock_funcs; 718 struct gma_clock_t clock; 719 int err = target; 720 721 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 722 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { 723 /* 724 * For LVDS, if the panel is on, just rely on its current 725 * settings for dual-channel. We haven't figured out how to 726 * reliably set up different single/dual channel state, if we 727 * even can. 728 */ 729 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 730 LVDS_CLKB_POWER_UP) 731 clock.p2 = limit->p2.p2_fast; 732 else 733 clock.p2 = limit->p2.p2_slow; 734 } else { 735 if (target < limit->p2.dot_limit) 736 clock.p2 = limit->p2.p2_slow; 737 else 738 clock.p2 = limit->p2.p2_fast; 739 } 740 741 memset(best_clock, 0, sizeof(*best_clock)); 742 743 /* m1 is always 0 on CDV so the outmost loop will run just once */ 744 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 745 for (clock.m2 = limit->m2.min; 746 (clock.m2 < clock.m1 || clock.m1 == 0) && 747 clock.m2 <= limit->m2.max; clock.m2++) { 748 for (clock.n = limit->n.min; 749 clock.n <= limit->n.max; clock.n++) { 750 for (clock.p1 = limit->p1.min; 751 clock.p1 <= limit->p1.max; 752 clock.p1++) { 753 int this_err; 754 755 clock_funcs->clock(refclk, &clock); 756 757 if (!clock_funcs->pll_is_valid(crtc, 758 limit, &clock)) 759 continue; 760 761 this_err = abs(clock.dot - target); 762 if (this_err < err) { 763 *best_clock = clock; 764 err = this_err; 765 } 766 } 767 } 768 } 769 } 770 771 return err != target; 772 } 773