1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 * Patrik Jakobsson <patrik.r.jakobsson@gmail.com> 20 */ 21 22 #include <drm/drmP.h> 23 #include "gma_display.h" 24 #include "psb_intel_drv.h" 25 #include "psb_intel_reg.h" 26 #include "psb_drv.h" 27 #include "framebuffer.h" 28 29 /** 30 * Returns whether any output on the specified pipe is of the specified type 31 */ 32 bool gma_pipe_has_type(struct drm_crtc *crtc, int type) 33 { 34 struct drm_device *dev = crtc->dev; 35 struct drm_mode_config *mode_config = &dev->mode_config; 36 struct drm_connector *l_entry; 37 38 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 39 if (l_entry->encoder && l_entry->encoder->crtc == crtc) { 40 struct gma_encoder *gma_encoder = 41 gma_attached_encoder(l_entry); 42 if (gma_encoder->type == type) 43 return true; 44 } 45 } 46 47 return false; 48 } 49 50 void gma_wait_for_vblank(struct drm_device *dev) 51 { 52 /* Wait for 20ms, i.e. one cycle at 50hz. */ 53 mdelay(20); 54 } 55 56 int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y, 57 struct drm_framebuffer *old_fb) 58 { 59 struct drm_device *dev = crtc->dev; 60 struct drm_psb_private *dev_priv = dev->dev_private; 61 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 62 struct drm_framebuffer *fb = crtc->primary->fb; 63 struct gtt_range *gtt; 64 int pipe = gma_crtc->pipe; 65 const struct psb_offset *map = &dev_priv->regmap[pipe]; 66 unsigned long start, offset; 67 u32 dspcntr; 68 int ret = 0; 69 70 if (!gma_power_begin(dev, true)) 71 return 0; 72 73 /* no fb bound */ 74 if (!fb) { 75 dev_err(dev->dev, "No FB bound\n"); 76 goto gma_pipe_cleaner; 77 } 78 79 gtt = to_gtt_range(fb->obj[0]); 80 81 /* We are displaying this buffer, make sure it is actually loaded 82 into the GTT */ 83 ret = psb_gtt_pin(gtt); 84 if (ret < 0) 85 goto gma_pipe_set_base_exit; 86 start = gtt->offset; 87 offset = y * fb->pitches[0] + x * fb->format->cpp[0]; 88 89 REG_WRITE(map->stride, fb->pitches[0]); 90 91 dspcntr = REG_READ(map->cntr); 92 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 93 94 switch (fb->format->cpp[0] * 8) { 95 case 8: 96 dspcntr |= DISPPLANE_8BPP; 97 break; 98 case 16: 99 if (fb->format->depth == 15) 100 dspcntr |= DISPPLANE_15_16BPP; 101 else 102 dspcntr |= DISPPLANE_16BPP; 103 break; 104 case 24: 105 case 32: 106 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; 107 break; 108 default: 109 dev_err(dev->dev, "Unknown color depth\n"); 110 ret = -EINVAL; 111 goto gma_pipe_set_base_exit; 112 } 113 REG_WRITE(map->cntr, dspcntr); 114 115 dev_dbg(dev->dev, 116 "Writing base %08lX %08lX %d %d\n", start, offset, x, y); 117 118 /* FIXME: Investigate whether this really is the base for psb and why 119 the linear offset is named base for the other chips. map->surf 120 should be the base and map->linoff the offset for all chips */ 121 if (IS_PSB(dev)) { 122 REG_WRITE(map->base, offset + start); 123 REG_READ(map->base); 124 } else { 125 REG_WRITE(map->base, offset); 126 REG_READ(map->base); 127 REG_WRITE(map->surf, start); 128 REG_READ(map->surf); 129 } 130 131 gma_pipe_cleaner: 132 /* If there was a previous display we can now unpin it */ 133 if (old_fb) 134 psb_gtt_unpin(to_gtt_range(old_fb->obj[0])); 135 136 gma_pipe_set_base_exit: 137 gma_power_end(dev); 138 return ret; 139 } 140 141 /* Loads the palette/gamma unit for the CRTC with the prepared values */ 142 void gma_crtc_load_lut(struct drm_crtc *crtc) 143 { 144 struct drm_device *dev = crtc->dev; 145 struct drm_psb_private *dev_priv = dev->dev_private; 146 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 147 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; 148 int palreg = map->palette; 149 u16 *r, *g, *b; 150 int i; 151 152 /* The clocks have to be on to load the palette. */ 153 if (!crtc->enabled) 154 return; 155 156 r = crtc->gamma_store; 157 g = r + crtc->gamma_size; 158 b = g + crtc->gamma_size; 159 160 if (gma_power_begin(dev, false)) { 161 for (i = 0; i < 256; i++) { 162 REG_WRITE(palreg + 4 * i, 163 (((*r++ >> 8) + gma_crtc->lut_adj[i]) << 16) | 164 (((*g++ >> 8) + gma_crtc->lut_adj[i]) << 8) | 165 ((*b++ >> 8) + gma_crtc->lut_adj[i])); 166 } 167 gma_power_end(dev); 168 } else { 169 for (i = 0; i < 256; i++) { 170 /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */ 171 dev_priv->regs.pipe[0].palette[i] = 172 (((*r++ >> 8) + gma_crtc->lut_adj[i]) << 16) | 173 (((*g++ >> 8) + gma_crtc->lut_adj[i]) << 8) | 174 ((*b++ >> 8) + gma_crtc->lut_adj[i]); 175 } 176 177 } 178 } 179 180 int gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, 181 u32 size, 182 struct drm_modeset_acquire_ctx *ctx) 183 { 184 gma_crtc_load_lut(crtc); 185 186 return 0; 187 } 188 189 /** 190 * Sets the power management mode of the pipe and plane. 191 * 192 * This code should probably grow support for turning the cursor off and back 193 * on appropriately at the same time as we're turning the pipe off/on. 194 */ 195 void gma_crtc_dpms(struct drm_crtc *crtc, int mode) 196 { 197 struct drm_device *dev = crtc->dev; 198 struct drm_psb_private *dev_priv = dev->dev_private; 199 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 200 int pipe = gma_crtc->pipe; 201 const struct psb_offset *map = &dev_priv->regmap[pipe]; 202 u32 temp; 203 204 /* XXX: When our outputs are all unaware of DPMS modes other than off 205 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 206 */ 207 208 if (IS_CDV(dev)) 209 dev_priv->ops->disable_sr(dev); 210 211 switch (mode) { 212 case DRM_MODE_DPMS_ON: 213 case DRM_MODE_DPMS_STANDBY: 214 case DRM_MODE_DPMS_SUSPEND: 215 if (gma_crtc->active) 216 break; 217 218 gma_crtc->active = true; 219 220 /* Enable the DPLL */ 221 temp = REG_READ(map->dpll); 222 if ((temp & DPLL_VCO_ENABLE) == 0) { 223 REG_WRITE(map->dpll, temp); 224 REG_READ(map->dpll); 225 /* Wait for the clocks to stabilize. */ 226 udelay(150); 227 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 228 REG_READ(map->dpll); 229 /* Wait for the clocks to stabilize. */ 230 udelay(150); 231 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 232 REG_READ(map->dpll); 233 /* Wait for the clocks to stabilize. */ 234 udelay(150); 235 } 236 237 /* Enable the plane */ 238 temp = REG_READ(map->cntr); 239 if ((temp & DISPLAY_PLANE_ENABLE) == 0) { 240 REG_WRITE(map->cntr, 241 temp | DISPLAY_PLANE_ENABLE); 242 /* Flush the plane changes */ 243 REG_WRITE(map->base, REG_READ(map->base)); 244 } 245 246 udelay(150); 247 248 /* Enable the pipe */ 249 temp = REG_READ(map->conf); 250 if ((temp & PIPEACONF_ENABLE) == 0) 251 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE); 252 253 temp = REG_READ(map->status); 254 temp &= ~(0xFFFF); 255 temp |= PIPE_FIFO_UNDERRUN; 256 REG_WRITE(map->status, temp); 257 REG_READ(map->status); 258 259 gma_crtc_load_lut(crtc); 260 261 /* Give the overlay scaler a chance to enable 262 * if it's on this pipe */ 263 /* psb_intel_crtc_dpms_video(crtc, true); TODO */ 264 break; 265 case DRM_MODE_DPMS_OFF: 266 if (!gma_crtc->active) 267 break; 268 269 gma_crtc->active = false; 270 271 /* Give the overlay scaler a chance to disable 272 * if it's on this pipe */ 273 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */ 274 275 /* Disable the VGA plane that we never use */ 276 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 277 278 /* Turn off vblank interrupts */ 279 drm_crtc_vblank_off(crtc); 280 281 /* Wait for vblank for the disable to take effect */ 282 gma_wait_for_vblank(dev); 283 284 /* Disable plane */ 285 temp = REG_READ(map->cntr); 286 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 287 REG_WRITE(map->cntr, 288 temp & ~DISPLAY_PLANE_ENABLE); 289 /* Flush the plane changes */ 290 REG_WRITE(map->base, REG_READ(map->base)); 291 REG_READ(map->base); 292 } 293 294 /* Disable pipe */ 295 temp = REG_READ(map->conf); 296 if ((temp & PIPEACONF_ENABLE) != 0) { 297 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE); 298 REG_READ(map->conf); 299 } 300 301 /* Wait for vblank for the disable to take effect. */ 302 gma_wait_for_vblank(dev); 303 304 udelay(150); 305 306 /* Disable DPLL */ 307 temp = REG_READ(map->dpll); 308 if ((temp & DPLL_VCO_ENABLE) != 0) { 309 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); 310 REG_READ(map->dpll); 311 } 312 313 /* Wait for the clocks to turn off. */ 314 udelay(150); 315 break; 316 } 317 318 if (IS_CDV(dev)) 319 dev_priv->ops->update_wm(dev, crtc); 320 321 /* Set FIFO watermarks */ 322 REG_WRITE(DSPARB, 0x3F3E); 323 } 324 325 int gma_crtc_cursor_set(struct drm_crtc *crtc, 326 struct drm_file *file_priv, 327 uint32_t handle, 328 uint32_t width, uint32_t height) 329 { 330 struct drm_device *dev = crtc->dev; 331 struct drm_psb_private *dev_priv = dev->dev_private; 332 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 333 int pipe = gma_crtc->pipe; 334 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; 335 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; 336 uint32_t temp; 337 size_t addr = 0; 338 struct gtt_range *gt; 339 struct gtt_range *cursor_gt = gma_crtc->cursor_gt; 340 struct drm_gem_object *obj; 341 void *tmp_dst, *tmp_src; 342 int ret = 0, i, cursor_pages; 343 344 /* If we didn't get a handle then turn the cursor off */ 345 if (!handle) { 346 temp = CURSOR_MODE_DISABLE; 347 if (gma_power_begin(dev, false)) { 348 REG_WRITE(control, temp); 349 REG_WRITE(base, 0); 350 gma_power_end(dev); 351 } 352 353 /* Unpin the old GEM object */ 354 if (gma_crtc->cursor_obj) { 355 gt = container_of(gma_crtc->cursor_obj, 356 struct gtt_range, gem); 357 psb_gtt_unpin(gt); 358 drm_gem_object_put_unlocked(gma_crtc->cursor_obj); 359 gma_crtc->cursor_obj = NULL; 360 } 361 return 0; 362 } 363 364 /* Currently we only support 64x64 cursors */ 365 if (width != 64 || height != 64) { 366 dev_dbg(dev->dev, "We currently only support 64x64 cursors\n"); 367 return -EINVAL; 368 } 369 370 obj = drm_gem_object_lookup(file_priv, handle); 371 if (!obj) { 372 ret = -ENOENT; 373 goto unlock; 374 } 375 376 if (obj->size < width * height * 4) { 377 dev_dbg(dev->dev, "Buffer is too small\n"); 378 ret = -ENOMEM; 379 goto unref_cursor; 380 } 381 382 gt = container_of(obj, struct gtt_range, gem); 383 384 /* Pin the memory into the GTT */ 385 ret = psb_gtt_pin(gt); 386 if (ret) { 387 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle); 388 goto unref_cursor; 389 } 390 391 if (dev_priv->ops->cursor_needs_phys) { 392 if (cursor_gt == NULL) { 393 dev_err(dev->dev, "No hardware cursor mem available"); 394 ret = -ENOMEM; 395 goto unref_cursor; 396 } 397 398 /* Prevent overflow */ 399 if (gt->npage > 4) 400 cursor_pages = 4; 401 else 402 cursor_pages = gt->npage; 403 404 /* Copy the cursor to cursor mem */ 405 tmp_dst = dev_priv->vram_addr + cursor_gt->offset; 406 for (i = 0; i < cursor_pages; i++) { 407 tmp_src = kmap(gt->pages[i]); 408 memcpy(tmp_dst, tmp_src, PAGE_SIZE); 409 kunmap(gt->pages[i]); 410 tmp_dst += PAGE_SIZE; 411 } 412 413 addr = gma_crtc->cursor_addr; 414 } else { 415 addr = gt->offset; 416 gma_crtc->cursor_addr = addr; 417 } 418 419 temp = 0; 420 /* set the pipe for the cursor */ 421 temp |= (pipe << 28); 422 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 423 424 if (gma_power_begin(dev, false)) { 425 REG_WRITE(control, temp); 426 REG_WRITE(base, addr); 427 gma_power_end(dev); 428 } 429 430 /* unpin the old bo */ 431 if (gma_crtc->cursor_obj) { 432 gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem); 433 psb_gtt_unpin(gt); 434 drm_gem_object_put_unlocked(gma_crtc->cursor_obj); 435 } 436 437 gma_crtc->cursor_obj = obj; 438 unlock: 439 return ret; 440 441 unref_cursor: 442 drm_gem_object_put_unlocked(obj); 443 return ret; 444 } 445 446 int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 447 { 448 struct drm_device *dev = crtc->dev; 449 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 450 int pipe = gma_crtc->pipe; 451 uint32_t temp = 0; 452 uint32_t addr; 453 454 if (x < 0) { 455 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 456 x = -x; 457 } 458 if (y < 0) { 459 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 460 y = -y; 461 } 462 463 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 464 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 465 466 addr = gma_crtc->cursor_addr; 467 468 if (gma_power_begin(dev, false)) { 469 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 470 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr); 471 gma_power_end(dev); 472 } 473 return 0; 474 } 475 476 void gma_crtc_prepare(struct drm_crtc *crtc) 477 { 478 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 479 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 480 } 481 482 void gma_crtc_commit(struct drm_crtc *crtc) 483 { 484 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 485 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 486 } 487 488 void gma_crtc_disable(struct drm_crtc *crtc) 489 { 490 struct gtt_range *gt; 491 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 492 493 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 494 495 if (crtc->primary->fb) { 496 gt = to_gtt_range(crtc->primary->fb->obj[0]); 497 psb_gtt_unpin(gt); 498 } 499 } 500 501 void gma_crtc_destroy(struct drm_crtc *crtc) 502 { 503 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 504 505 kfree(gma_crtc->crtc_state); 506 drm_crtc_cleanup(crtc); 507 kfree(gma_crtc); 508 } 509 510 int gma_crtc_set_config(struct drm_mode_set *set, 511 struct drm_modeset_acquire_ctx *ctx) 512 { 513 struct drm_device *dev = set->crtc->dev; 514 struct drm_psb_private *dev_priv = dev->dev_private; 515 int ret; 516 517 if (!dev_priv->rpm_enabled) 518 return drm_crtc_helper_set_config(set, ctx); 519 520 pm_runtime_forbid(&dev->pdev->dev); 521 ret = drm_crtc_helper_set_config(set, ctx); 522 pm_runtime_allow(&dev->pdev->dev); 523 524 return ret; 525 } 526 527 /** 528 * Save HW states of given crtc 529 */ 530 void gma_crtc_save(struct drm_crtc *crtc) 531 { 532 struct drm_device *dev = crtc->dev; 533 struct drm_psb_private *dev_priv = dev->dev_private; 534 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 535 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; 536 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; 537 uint32_t palette_reg; 538 int i; 539 540 if (!crtc_state) { 541 dev_err(dev->dev, "No CRTC state found\n"); 542 return; 543 } 544 545 crtc_state->saveDSPCNTR = REG_READ(map->cntr); 546 crtc_state->savePIPECONF = REG_READ(map->conf); 547 crtc_state->savePIPESRC = REG_READ(map->src); 548 crtc_state->saveFP0 = REG_READ(map->fp0); 549 crtc_state->saveFP1 = REG_READ(map->fp1); 550 crtc_state->saveDPLL = REG_READ(map->dpll); 551 crtc_state->saveHTOTAL = REG_READ(map->htotal); 552 crtc_state->saveHBLANK = REG_READ(map->hblank); 553 crtc_state->saveHSYNC = REG_READ(map->hsync); 554 crtc_state->saveVTOTAL = REG_READ(map->vtotal); 555 crtc_state->saveVBLANK = REG_READ(map->vblank); 556 crtc_state->saveVSYNC = REG_READ(map->vsync); 557 crtc_state->saveDSPSTRIDE = REG_READ(map->stride); 558 559 /* NOTE: DSPSIZE DSPPOS only for psb */ 560 crtc_state->saveDSPSIZE = REG_READ(map->size); 561 crtc_state->saveDSPPOS = REG_READ(map->pos); 562 563 crtc_state->saveDSPBASE = REG_READ(map->base); 564 565 palette_reg = map->palette; 566 for (i = 0; i < 256; ++i) 567 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); 568 } 569 570 /** 571 * Restore HW states of given crtc 572 */ 573 void gma_crtc_restore(struct drm_crtc *crtc) 574 { 575 struct drm_device *dev = crtc->dev; 576 struct drm_psb_private *dev_priv = dev->dev_private; 577 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 578 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; 579 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe]; 580 uint32_t palette_reg; 581 int i; 582 583 if (!crtc_state) { 584 dev_err(dev->dev, "No crtc state\n"); 585 return; 586 } 587 588 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { 589 REG_WRITE(map->dpll, 590 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); 591 REG_READ(map->dpll); 592 udelay(150); 593 } 594 595 REG_WRITE(map->fp0, crtc_state->saveFP0); 596 REG_READ(map->fp0); 597 598 REG_WRITE(map->fp1, crtc_state->saveFP1); 599 REG_READ(map->fp1); 600 601 REG_WRITE(map->dpll, crtc_state->saveDPLL); 602 REG_READ(map->dpll); 603 udelay(150); 604 605 REG_WRITE(map->htotal, crtc_state->saveHTOTAL); 606 REG_WRITE(map->hblank, crtc_state->saveHBLANK); 607 REG_WRITE(map->hsync, crtc_state->saveHSYNC); 608 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL); 609 REG_WRITE(map->vblank, crtc_state->saveVBLANK); 610 REG_WRITE(map->vsync, crtc_state->saveVSYNC); 611 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE); 612 613 REG_WRITE(map->size, crtc_state->saveDSPSIZE); 614 REG_WRITE(map->pos, crtc_state->saveDSPPOS); 615 616 REG_WRITE(map->src, crtc_state->savePIPESRC); 617 REG_WRITE(map->base, crtc_state->saveDSPBASE); 618 REG_WRITE(map->conf, crtc_state->savePIPECONF); 619 620 gma_wait_for_vblank(dev); 621 622 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR); 623 REG_WRITE(map->base, crtc_state->saveDSPBASE); 624 625 gma_wait_for_vblank(dev); 626 627 palette_reg = map->palette; 628 for (i = 0; i < 256; ++i) 629 REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]); 630 } 631 632 void gma_encoder_prepare(struct drm_encoder *encoder) 633 { 634 const struct drm_encoder_helper_funcs *encoder_funcs = 635 encoder->helper_private; 636 /* lvds has its own version of prepare see psb_intel_lvds_prepare */ 637 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 638 } 639 640 void gma_encoder_commit(struct drm_encoder *encoder) 641 { 642 const struct drm_encoder_helper_funcs *encoder_funcs = 643 encoder->helper_private; 644 /* lvds has its own version of commit see psb_intel_lvds_commit */ 645 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 646 } 647 648 void gma_encoder_destroy(struct drm_encoder *encoder) 649 { 650 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 651 652 drm_encoder_cleanup(encoder); 653 kfree(intel_encoder); 654 } 655 656 /* Currently there is only a 1:1 mapping of encoders and connectors */ 657 struct drm_encoder *gma_best_encoder(struct drm_connector *connector) 658 { 659 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 660 661 return &gma_encoder->base; 662 } 663 664 void gma_connector_attach_encoder(struct gma_connector *connector, 665 struct gma_encoder *encoder) 666 { 667 connector->encoder = encoder; 668 drm_connector_attach_encoder(&connector->base, 669 &encoder->base); 670 } 671 672 #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; } 673 674 bool gma_pll_is_valid(struct drm_crtc *crtc, 675 const struct gma_limit_t *limit, 676 struct gma_clock_t *clock) 677 { 678 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 679 GMA_PLL_INVALID("p1 out of range"); 680 if (clock->p < limit->p.min || limit->p.max < clock->p) 681 GMA_PLL_INVALID("p out of range"); 682 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 683 GMA_PLL_INVALID("m2 out of range"); 684 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 685 GMA_PLL_INVALID("m1 out of range"); 686 /* On CDV m1 is always 0 */ 687 if (clock->m1 <= clock->m2 && clock->m1 != 0) 688 GMA_PLL_INVALID("m1 <= m2 && m1 != 0"); 689 if (clock->m < limit->m.min || limit->m.max < clock->m) 690 GMA_PLL_INVALID("m out of range"); 691 if (clock->n < limit->n.min || limit->n.max < clock->n) 692 GMA_PLL_INVALID("n out of range"); 693 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 694 GMA_PLL_INVALID("vco out of range"); 695 /* XXX: We may need to be checking "Dot clock" 696 * depending on the multiplier, connector, etc., 697 * rather than just a single range. 698 */ 699 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 700 GMA_PLL_INVALID("dot out of range"); 701 702 return true; 703 } 704 705 bool gma_find_best_pll(const struct gma_limit_t *limit, 706 struct drm_crtc *crtc, int target, int refclk, 707 struct gma_clock_t *best_clock) 708 { 709 struct drm_device *dev = crtc->dev; 710 const struct gma_clock_funcs *clock_funcs = 711 to_gma_crtc(crtc)->clock_funcs; 712 struct gma_clock_t clock; 713 int err = target; 714 715 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 716 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { 717 /* 718 * For LVDS, if the panel is on, just rely on its current 719 * settings for dual-channel. We haven't figured out how to 720 * reliably set up different single/dual channel state, if we 721 * even can. 722 */ 723 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == 724 LVDS_CLKB_POWER_UP) 725 clock.p2 = limit->p2.p2_fast; 726 else 727 clock.p2 = limit->p2.p2_slow; 728 } else { 729 if (target < limit->p2.dot_limit) 730 clock.p2 = limit->p2.p2_slow; 731 else 732 clock.p2 = limit->p2.p2_fast; 733 } 734 735 memset(best_clock, 0, sizeof(*best_clock)); 736 737 /* m1 is always 0 on CDV so the outmost loop will run just once */ 738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 739 for (clock.m2 = limit->m2.min; 740 (clock.m2 < clock.m1 || clock.m1 == 0) && 741 clock.m2 <= limit->m2.max; clock.m2++) { 742 for (clock.n = limit->n.min; 743 clock.n <= limit->n.max; clock.n++) { 744 for (clock.p1 = limit->p1.min; 745 clock.p1 <= limit->p1.max; 746 clock.p1++) { 747 int this_err; 748 749 clock_funcs->clock(refclk, &clock); 750 751 if (!clock_funcs->pll_is_valid(crtc, 752 limit, &clock)) 753 continue; 754 755 this_err = abs(clock.dot - target); 756 if (this_err < err) { 757 *best_clock = clock; 758 err = this_err; 759 } 760 } 761 } 762 } 763 } 764 765 return err != target; 766 } 767