1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/module.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include "psb_drv.h" 35 #include "psb_intel_drv.h" 36 #include "psb_intel_reg.h" 37 #include "gma_display.h" 38 #include <drm/drm_dp_helper.h> 39 40 #define _wait_for(COND, MS, W) ({ \ 41 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 42 int ret__ = 0; \ 43 while (! (COND)) { \ 44 if (time_after(jiffies, timeout__)) { \ 45 ret__ = -ETIMEDOUT; \ 46 break; \ 47 } \ 48 if (W && !in_dbg_master()) msleep(W); \ 49 } \ 50 ret__; \ 51 }) 52 53 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 54 55 #define DP_LINK_STATUS_SIZE 6 56 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 57 58 #define DP_LINK_CONFIGURATION_SIZE 9 59 60 #define CDV_FAST_LINK_TRAIN 1 61 62 struct cdv_intel_dp { 63 uint32_t output_reg; 64 uint32_t DP; 65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 66 bool has_audio; 67 int force_audio; 68 uint32_t color_range; 69 uint8_t link_bw; 70 uint8_t lane_count; 71 uint8_t dpcd[4]; 72 struct gma_encoder *encoder; 73 struct i2c_adapter adapter; 74 struct i2c_algo_dp_aux_data algo; 75 uint8_t train_set[4]; 76 uint8_t link_status[DP_LINK_STATUS_SIZE]; 77 int panel_power_up_delay; 78 int panel_power_down_delay; 79 int panel_power_cycle_delay; 80 int backlight_on_delay; 81 int backlight_off_delay; 82 struct drm_display_mode *panel_fixed_mode; /* for eDP */ 83 bool panel_on; 84 }; 85 86 struct ddi_regoff { 87 uint32_t PreEmph1; 88 uint32_t PreEmph2; 89 uint32_t VSwing1; 90 uint32_t VSwing2; 91 uint32_t VSwing3; 92 uint32_t VSwing4; 93 uint32_t VSwing5; 94 }; 95 96 static struct ddi_regoff ddi_DP_train_table[] = { 97 {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154, 98 .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150, 99 .VSwing5 = 0x8158,}, 100 {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254, 101 .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250, 102 .VSwing5 = 0x8258,}, 103 }; 104 105 static uint32_t dp_vswing_premph_table[] = { 106 0x55338954, 0x4000, 107 0x554d8954, 0x2000, 108 0x55668954, 0, 109 0x559ac0d4, 0x6000, 110 }; 111 /** 112 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 113 * @intel_dp: DP struct 114 * 115 * If a CPU or PCH DP output is attached to an eDP panel, this function 116 * will return true, and false otherwise. 117 */ 118 static bool is_edp(struct gma_encoder *encoder) 119 { 120 return encoder->type == INTEL_OUTPUT_EDP; 121 } 122 123 124 static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder); 125 static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder); 126 static void cdv_intel_dp_link_down(struct gma_encoder *encoder); 127 128 static int 129 cdv_intel_dp_max_lane_count(struct gma_encoder *encoder) 130 { 131 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 132 int max_lane_count = 4; 133 134 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 135 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 136 switch (max_lane_count) { 137 case 1: case 2: case 4: 138 break; 139 default: 140 max_lane_count = 4; 141 } 142 } 143 return max_lane_count; 144 } 145 146 static int 147 cdv_intel_dp_max_link_bw(struct gma_encoder *encoder) 148 { 149 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 151 152 switch (max_link_bw) { 153 case DP_LINK_BW_1_62: 154 case DP_LINK_BW_2_7: 155 break; 156 default: 157 max_link_bw = DP_LINK_BW_1_62; 158 break; 159 } 160 return max_link_bw; 161 } 162 163 static int 164 cdv_intel_dp_link_clock(uint8_t link_bw) 165 { 166 if (link_bw == DP_LINK_BW_2_7) 167 return 270000; 168 else 169 return 162000; 170 } 171 172 static int 173 cdv_intel_dp_link_required(int pixel_clock, int bpp) 174 { 175 return (pixel_clock * bpp + 7) / 8; 176 } 177 178 static int 179 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) 180 { 181 return (max_link_clock * max_lanes * 19) / 20; 182 } 183 184 static void cdv_intel_edp_panel_vdd_on(struct gma_encoder *intel_encoder) 185 { 186 struct drm_device *dev = intel_encoder->base.dev; 187 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 188 u32 pp; 189 190 if (intel_dp->panel_on) { 191 DRM_DEBUG_KMS("Skip VDD on because of panel on\n"); 192 return; 193 } 194 DRM_DEBUG_KMS("\n"); 195 196 pp = REG_READ(PP_CONTROL); 197 198 pp |= EDP_FORCE_VDD; 199 REG_WRITE(PP_CONTROL, pp); 200 REG_READ(PP_CONTROL); 201 msleep(intel_dp->panel_power_up_delay); 202 } 203 204 static void cdv_intel_edp_panel_vdd_off(struct gma_encoder *intel_encoder) 205 { 206 struct drm_device *dev = intel_encoder->base.dev; 207 u32 pp; 208 209 DRM_DEBUG_KMS("\n"); 210 pp = REG_READ(PP_CONTROL); 211 212 pp &= ~EDP_FORCE_VDD; 213 REG_WRITE(PP_CONTROL, pp); 214 REG_READ(PP_CONTROL); 215 216 } 217 218 /* Returns true if the panel was already on when called */ 219 static bool cdv_intel_edp_panel_on(struct gma_encoder *intel_encoder) 220 { 221 struct drm_device *dev = intel_encoder->base.dev; 222 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 223 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE; 224 225 if (intel_dp->panel_on) 226 return true; 227 228 DRM_DEBUG_KMS("\n"); 229 pp = REG_READ(PP_CONTROL); 230 pp &= ~PANEL_UNLOCK_MASK; 231 232 pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON); 233 REG_WRITE(PP_CONTROL, pp); 234 REG_READ(PP_CONTROL); 235 236 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { 237 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); 238 intel_dp->panel_on = false; 239 } else 240 intel_dp->panel_on = true; 241 msleep(intel_dp->panel_power_up_delay); 242 243 return false; 244 } 245 246 static void cdv_intel_edp_panel_off (struct gma_encoder *intel_encoder) 247 { 248 struct drm_device *dev = intel_encoder->base.dev; 249 u32 pp, idle_off_mask = PP_ON ; 250 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 251 252 DRM_DEBUG_KMS("\n"); 253 254 pp = REG_READ(PP_CONTROL); 255 256 if ((pp & POWER_TARGET_ON) == 0) 257 return; 258 259 intel_dp->panel_on = false; 260 pp &= ~PANEL_UNLOCK_MASK; 261 /* ILK workaround: disable reset around power sequence */ 262 263 pp &= ~POWER_TARGET_ON; 264 pp &= ~EDP_FORCE_VDD; 265 pp &= ~EDP_BLC_ENABLE; 266 REG_WRITE(PP_CONTROL, pp); 267 REG_READ(PP_CONTROL); 268 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS)); 269 270 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { 271 DRM_DEBUG_KMS("Error in turning off Panel\n"); 272 } 273 274 msleep(intel_dp->panel_power_cycle_delay); 275 DRM_DEBUG_KMS("Over\n"); 276 } 277 278 static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder) 279 { 280 struct drm_device *dev = intel_encoder->base.dev; 281 u32 pp; 282 283 DRM_DEBUG_KMS("\n"); 284 /* 285 * If we enable the backlight right away following a panel power 286 * on, we may see slight flicker as the panel syncs with the eDP 287 * link. So delay a bit to make sure the image is solid before 288 * allowing it to appear. 289 */ 290 msleep(300); 291 pp = REG_READ(PP_CONTROL); 292 293 pp |= EDP_BLC_ENABLE; 294 REG_WRITE(PP_CONTROL, pp); 295 gma_backlight_enable(dev); 296 } 297 298 static void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder) 299 { 300 struct drm_device *dev = intel_encoder->base.dev; 301 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 302 u32 pp; 303 304 DRM_DEBUG_KMS("\n"); 305 gma_backlight_disable(dev); 306 msleep(10); 307 pp = REG_READ(PP_CONTROL); 308 309 pp &= ~EDP_BLC_ENABLE; 310 REG_WRITE(PP_CONTROL, pp); 311 msleep(intel_dp->backlight_off_delay); 312 } 313 314 static int 315 cdv_intel_dp_mode_valid(struct drm_connector *connector, 316 struct drm_display_mode *mode) 317 { 318 struct gma_encoder *encoder = gma_attached_encoder(connector); 319 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 320 int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder)); 321 int max_lanes = cdv_intel_dp_max_lane_count(encoder); 322 struct drm_psb_private *dev_priv = connector->dev->dev_private; 323 324 if (is_edp(encoder) && intel_dp->panel_fixed_mode) { 325 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) 326 return MODE_PANEL; 327 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) 328 return MODE_PANEL; 329 } 330 331 /* only refuse the mode on non eDP since we have seen some weird eDP panels 332 which are outside spec tolerances but somehow work by magic */ 333 if (!is_edp(encoder) && 334 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp) 335 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))) 336 return MODE_CLOCK_HIGH; 337 338 if (is_edp(encoder)) { 339 if (cdv_intel_dp_link_required(mode->clock, 24) 340 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)) 341 return MODE_CLOCK_HIGH; 342 343 } 344 if (mode->clock < 10000) 345 return MODE_CLOCK_LOW; 346 347 return MODE_OK; 348 } 349 350 static uint32_t 351 pack_aux(uint8_t *src, int src_bytes) 352 { 353 int i; 354 uint32_t v = 0; 355 356 if (src_bytes > 4) 357 src_bytes = 4; 358 for (i = 0; i < src_bytes; i++) 359 v |= ((uint32_t) src[i]) << ((3-i) * 8); 360 return v; 361 } 362 363 static void 364 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 365 { 366 int i; 367 if (dst_bytes > 4) 368 dst_bytes = 4; 369 for (i = 0; i < dst_bytes; i++) 370 dst[i] = src >> ((3-i) * 8); 371 } 372 373 static int 374 cdv_intel_dp_aux_ch(struct gma_encoder *encoder, 375 uint8_t *send, int send_bytes, 376 uint8_t *recv, int recv_size) 377 { 378 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 379 uint32_t output_reg = intel_dp->output_reg; 380 struct drm_device *dev = encoder->base.dev; 381 uint32_t ch_ctl = output_reg + 0x10; 382 uint32_t ch_data = ch_ctl + 4; 383 int i; 384 int recv_bytes; 385 uint32_t status; 386 uint32_t aux_clock_divider; 387 int try, precharge; 388 389 /* The clock divider is based off the hrawclk, 390 * and would like to run at 2MHz. So, take the 391 * hrawclk value and divide by 2 and use that 392 * On CDV platform it uses 200MHz as hrawclk. 393 * 394 */ 395 aux_clock_divider = 200 / 2; 396 397 precharge = 4; 398 if (is_edp(encoder)) 399 precharge = 10; 400 401 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 402 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 403 REG_READ(ch_ctl)); 404 return -EBUSY; 405 } 406 407 /* Must try at least 3 times according to DP spec */ 408 for (try = 0; try < 5; try++) { 409 /* Load the send data into the aux channel data registers */ 410 for (i = 0; i < send_bytes; i += 4) 411 REG_WRITE(ch_data + i, 412 pack_aux(send + i, send_bytes - i)); 413 414 /* Send the command and wait for it to complete */ 415 REG_WRITE(ch_ctl, 416 DP_AUX_CH_CTL_SEND_BUSY | 417 DP_AUX_CH_CTL_TIME_OUT_400us | 418 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 419 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 420 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 421 DP_AUX_CH_CTL_DONE | 422 DP_AUX_CH_CTL_TIME_OUT_ERROR | 423 DP_AUX_CH_CTL_RECEIVE_ERROR); 424 for (;;) { 425 status = REG_READ(ch_ctl); 426 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 427 break; 428 udelay(100); 429 } 430 431 /* Clear done status and any errors */ 432 REG_WRITE(ch_ctl, 433 status | 434 DP_AUX_CH_CTL_DONE | 435 DP_AUX_CH_CTL_TIME_OUT_ERROR | 436 DP_AUX_CH_CTL_RECEIVE_ERROR); 437 if (status & DP_AUX_CH_CTL_DONE) 438 break; 439 } 440 441 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 443 return -EBUSY; 444 } 445 446 /* Check for timeout or receive error. 447 * Timeouts occur when the sink is not connected 448 */ 449 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 451 return -EIO; 452 } 453 454 /* Timeouts occur when the device isn't connected, so they're 455 * "normal" -- don't fill the kernel log with these */ 456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 458 return -ETIMEDOUT; 459 } 460 461 /* Unload any bytes sent back from the other side */ 462 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 464 if (recv_bytes > recv_size) 465 recv_bytes = recv_size; 466 467 for (i = 0; i < recv_bytes; i += 4) 468 unpack_aux(REG_READ(ch_data + i), 469 recv + i, recv_bytes - i); 470 471 return recv_bytes; 472 } 473 474 /* Write data to the aux channel in native mode */ 475 static int 476 cdv_intel_dp_aux_native_write(struct gma_encoder *encoder, 477 uint16_t address, uint8_t *send, int send_bytes) 478 { 479 int ret; 480 uint8_t msg[20]; 481 int msg_bytes; 482 uint8_t ack; 483 484 if (send_bytes > 16) 485 return -1; 486 msg[0] = DP_AUX_NATIVE_WRITE << 4; 487 msg[1] = address >> 8; 488 msg[2] = address & 0xff; 489 msg[3] = send_bytes - 1; 490 memcpy(&msg[4], send, send_bytes); 491 msg_bytes = send_bytes + 4; 492 for (;;) { 493 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1); 494 if (ret < 0) 495 return ret; 496 ack >>= 4; 497 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) 498 break; 499 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 500 udelay(100); 501 else 502 return -EIO; 503 } 504 return send_bytes; 505 } 506 507 /* Write a single byte to the aux channel in native mode */ 508 static int 509 cdv_intel_dp_aux_native_write_1(struct gma_encoder *encoder, 510 uint16_t address, uint8_t byte) 511 { 512 return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1); 513 } 514 515 /* read bytes from a native aux channel */ 516 static int 517 cdv_intel_dp_aux_native_read(struct gma_encoder *encoder, 518 uint16_t address, uint8_t *recv, int recv_bytes) 519 { 520 uint8_t msg[4]; 521 int msg_bytes; 522 uint8_t reply[20]; 523 int reply_bytes; 524 uint8_t ack; 525 int ret; 526 527 msg[0] = DP_AUX_NATIVE_READ << 4; 528 msg[1] = address >> 8; 529 msg[2] = address & 0xff; 530 msg[3] = recv_bytes - 1; 531 532 msg_bytes = 4; 533 reply_bytes = recv_bytes + 1; 534 535 for (;;) { 536 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, 537 reply, reply_bytes); 538 if (ret == 0) 539 return -EPROTO; 540 if (ret < 0) 541 return ret; 542 ack = reply[0] >> 4; 543 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { 544 memcpy(recv, reply + 1, ret - 1); 545 return ret - 1; 546 } 547 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) 548 udelay(100); 549 else 550 return -EIO; 551 } 552 } 553 554 static int 555 cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 556 uint8_t write_byte, uint8_t *read_byte) 557 { 558 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 559 struct cdv_intel_dp *intel_dp = container_of(adapter, 560 struct cdv_intel_dp, 561 adapter); 562 struct gma_encoder *encoder = intel_dp->encoder; 563 uint16_t address = algo_data->address; 564 uint8_t msg[5]; 565 uint8_t reply[2]; 566 unsigned retry; 567 int msg_bytes; 568 int reply_bytes; 569 int ret; 570 571 /* Set up the command byte */ 572 if (mode & MODE_I2C_READ) 573 msg[0] = DP_AUX_I2C_READ << 4; 574 else 575 msg[0] = DP_AUX_I2C_WRITE << 4; 576 577 if (!(mode & MODE_I2C_STOP)) 578 msg[0] |= DP_AUX_I2C_MOT << 4; 579 580 msg[1] = address >> 8; 581 msg[2] = address; 582 583 switch (mode) { 584 case MODE_I2C_WRITE: 585 msg[3] = 0; 586 msg[4] = write_byte; 587 msg_bytes = 5; 588 reply_bytes = 1; 589 break; 590 case MODE_I2C_READ: 591 msg[3] = 0; 592 msg_bytes = 4; 593 reply_bytes = 2; 594 break; 595 default: 596 msg_bytes = 3; 597 reply_bytes = 1; 598 break; 599 } 600 601 for (retry = 0; retry < 5; retry++) { 602 ret = cdv_intel_dp_aux_ch(encoder, 603 msg, msg_bytes, 604 reply, reply_bytes); 605 if (ret < 0) { 606 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 607 return ret; 608 } 609 610 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { 611 case DP_AUX_NATIVE_REPLY_ACK: 612 /* I2C-over-AUX Reply field is only valid 613 * when paired with AUX ACK. 614 */ 615 break; 616 case DP_AUX_NATIVE_REPLY_NACK: 617 DRM_DEBUG_KMS("aux_ch native nack\n"); 618 return -EREMOTEIO; 619 case DP_AUX_NATIVE_REPLY_DEFER: 620 udelay(100); 621 continue; 622 default: 623 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 624 reply[0]); 625 return -EREMOTEIO; 626 } 627 628 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { 629 case DP_AUX_I2C_REPLY_ACK: 630 if (mode == MODE_I2C_READ) { 631 *read_byte = reply[1]; 632 } 633 return reply_bytes - 1; 634 case DP_AUX_I2C_REPLY_NACK: 635 DRM_DEBUG_KMS("aux_i2c nack\n"); 636 return -EREMOTEIO; 637 case DP_AUX_I2C_REPLY_DEFER: 638 DRM_DEBUG_KMS("aux_i2c defer\n"); 639 udelay(100); 640 break; 641 default: 642 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 643 return -EREMOTEIO; 644 } 645 } 646 647 DRM_ERROR("too many retries, giving up\n"); 648 return -EREMOTEIO; 649 } 650 651 static int 652 cdv_intel_dp_i2c_init(struct gma_connector *connector, 653 struct gma_encoder *encoder, const char *name) 654 { 655 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 656 int ret; 657 658 DRM_DEBUG_KMS("i2c_init %s\n", name); 659 660 intel_dp->algo.running = false; 661 intel_dp->algo.address = 0; 662 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch; 663 664 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 665 intel_dp->adapter.owner = THIS_MODULE; 666 intel_dp->adapter.class = I2C_CLASS_DDC; 667 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 668 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 669 intel_dp->adapter.algo_data = &intel_dp->algo; 670 intel_dp->adapter.dev.parent = connector->base.kdev; 671 672 if (is_edp(encoder)) 673 cdv_intel_edp_panel_vdd_on(encoder); 674 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 675 if (is_edp(encoder)) 676 cdv_intel_edp_panel_vdd_off(encoder); 677 678 return ret; 679 } 680 681 static void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 682 struct drm_display_mode *adjusted_mode) 683 { 684 adjusted_mode->hdisplay = fixed_mode->hdisplay; 685 adjusted_mode->hsync_start = fixed_mode->hsync_start; 686 adjusted_mode->hsync_end = fixed_mode->hsync_end; 687 adjusted_mode->htotal = fixed_mode->htotal; 688 689 adjusted_mode->vdisplay = fixed_mode->vdisplay; 690 adjusted_mode->vsync_start = fixed_mode->vsync_start; 691 adjusted_mode->vsync_end = fixed_mode->vsync_end; 692 adjusted_mode->vtotal = fixed_mode->vtotal; 693 694 adjusted_mode->clock = fixed_mode->clock; 695 696 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 697 } 698 699 static bool 700 cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, 701 struct drm_display_mode *adjusted_mode) 702 { 703 struct drm_psb_private *dev_priv = encoder->dev->dev_private; 704 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 705 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 706 int lane_count, clock; 707 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder); 708 int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; 709 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 710 int refclock = mode->clock; 711 int bpp = 24; 712 713 if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) { 714 cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); 715 refclock = intel_dp->panel_fixed_mode->clock; 716 bpp = dev_priv->edp.bpp; 717 } 718 719 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 720 for (clock = max_clock; clock >= 0; clock--) { 721 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); 722 723 if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) { 724 intel_dp->link_bw = bws[clock]; 725 intel_dp->lane_count = lane_count; 726 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); 727 DRM_DEBUG_KMS("Display port link bw %02x lane " 728 "count %d clock %d\n", 729 intel_dp->link_bw, intel_dp->lane_count, 730 adjusted_mode->clock); 731 return true; 732 } 733 } 734 } 735 if (is_edp(intel_encoder)) { 736 /* okay we failed just pick the highest */ 737 intel_dp->lane_count = max_lane_count; 738 intel_dp->link_bw = bws[max_clock]; 739 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); 740 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 741 "count %d clock %d\n", 742 intel_dp->link_bw, intel_dp->lane_count, 743 adjusted_mode->clock); 744 745 return true; 746 } 747 return false; 748 } 749 750 struct cdv_intel_dp_m_n { 751 uint32_t tu; 752 uint32_t gmch_m; 753 uint32_t gmch_n; 754 uint32_t link_m; 755 uint32_t link_n; 756 }; 757 758 static void 759 cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den) 760 { 761 /* 762 while (*num > 0xffffff || *den > 0xffffff) { 763 *num >>= 1; 764 *den >>= 1; 765 }*/ 766 uint64_t value, m; 767 m = *num; 768 value = m * (0x800000); 769 m = do_div(value, *den); 770 *num = value; 771 *den = 0x800000; 772 } 773 774 static void 775 cdv_intel_dp_compute_m_n(int bpp, 776 int nlanes, 777 int pixel_clock, 778 int link_clock, 779 struct cdv_intel_dp_m_n *m_n) 780 { 781 m_n->tu = 64; 782 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; 783 m_n->gmch_n = link_clock * nlanes; 784 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 785 m_n->link_m = pixel_clock; 786 m_n->link_n = link_clock; 787 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 788 } 789 790 void 791 cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 792 struct drm_display_mode *adjusted_mode) 793 { 794 struct drm_device *dev = crtc->dev; 795 struct drm_psb_private *dev_priv = dev->dev_private; 796 struct drm_mode_config *mode_config = &dev->mode_config; 797 struct drm_encoder *encoder; 798 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 799 int lane_count = 4, bpp = 24; 800 struct cdv_intel_dp_m_n m_n; 801 int pipe = gma_crtc->pipe; 802 803 /* 804 * Find the lane count in the intel_encoder private 805 */ 806 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 807 struct gma_encoder *intel_encoder; 808 struct cdv_intel_dp *intel_dp; 809 810 if (encoder->crtc != crtc) 811 continue; 812 813 intel_encoder = to_gma_encoder(encoder); 814 intel_dp = intel_encoder->dev_priv; 815 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 816 lane_count = intel_dp->lane_count; 817 break; 818 } else if (is_edp(intel_encoder)) { 819 lane_count = intel_dp->lane_count; 820 bpp = dev_priv->edp.bpp; 821 break; 822 } 823 } 824 825 /* 826 * Compute the GMCH and Link ratios. The '3' here is 827 * the number of bytes_per_pixel post-LUT, which we always 828 * set up for 8-bits of R/G/B, or 3 bytes total. 829 */ 830 cdv_intel_dp_compute_m_n(bpp, lane_count, 831 mode->clock, adjusted_mode->clock, &m_n); 832 833 { 834 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 835 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 836 m_n.gmch_m); 837 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 838 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 839 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 840 } 841 } 842 843 static void 844 cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 845 struct drm_display_mode *adjusted_mode) 846 { 847 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 848 struct drm_crtc *crtc = encoder->crtc; 849 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 850 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 851 struct drm_device *dev = encoder->dev; 852 853 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 854 intel_dp->DP |= intel_dp->color_range; 855 856 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 857 intel_dp->DP |= DP_SYNC_HS_HIGH; 858 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 859 intel_dp->DP |= DP_SYNC_VS_HIGH; 860 861 intel_dp->DP |= DP_LINK_TRAIN_OFF; 862 863 switch (intel_dp->lane_count) { 864 case 1: 865 intel_dp->DP |= DP_PORT_WIDTH_1; 866 break; 867 case 2: 868 intel_dp->DP |= DP_PORT_WIDTH_2; 869 break; 870 case 4: 871 intel_dp->DP |= DP_PORT_WIDTH_4; 872 break; 873 } 874 if (intel_dp->has_audio) 875 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 876 877 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 878 intel_dp->link_configuration[0] = intel_dp->link_bw; 879 intel_dp->link_configuration[1] = intel_dp->lane_count; 880 881 /* 882 * Check for DPCD version > 1.1 and enhanced framing support 883 */ 884 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 885 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 886 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 887 intel_dp->DP |= DP_ENHANCED_FRAMING; 888 } 889 890 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 891 if (gma_crtc->pipe == 1) 892 intel_dp->DP |= DP_PIPEB_SELECT; 893 894 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN)); 895 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP); 896 if (is_edp(intel_encoder)) { 897 uint32_t pfit_control; 898 cdv_intel_edp_panel_on(intel_encoder); 899 900 if (mode->hdisplay != adjusted_mode->hdisplay || 901 mode->vdisplay != adjusted_mode->vdisplay) 902 pfit_control = PFIT_ENABLE; 903 else 904 pfit_control = 0; 905 906 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; 907 908 REG_WRITE(PFIT_CONTROL, pfit_control); 909 } 910 } 911 912 913 /* If the sink supports it, try to set the power state appropriately */ 914 static void cdv_intel_dp_sink_dpms(struct gma_encoder *encoder, int mode) 915 { 916 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 917 int ret, i; 918 919 /* Should have a valid DPCD by this point */ 920 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 921 return; 922 923 if (mode != DRM_MODE_DPMS_ON) { 924 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER, 925 DP_SET_POWER_D3); 926 if (ret != 1) 927 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 928 } else { 929 /* 930 * When turning on, we need to retry for 1ms to give the sink 931 * time to wake up. 932 */ 933 for (i = 0; i < 3; i++) { 934 ret = cdv_intel_dp_aux_native_write_1(encoder, 935 DP_SET_POWER, 936 DP_SET_POWER_D0); 937 if (ret == 1) 938 break; 939 udelay(1000); 940 } 941 } 942 } 943 944 static void cdv_intel_dp_prepare(struct drm_encoder *encoder) 945 { 946 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 947 int edp = is_edp(intel_encoder); 948 949 if (edp) { 950 cdv_intel_edp_backlight_off(intel_encoder); 951 cdv_intel_edp_panel_off(intel_encoder); 952 cdv_intel_edp_panel_vdd_on(intel_encoder); 953 } 954 /* Wake up the sink first */ 955 cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON); 956 cdv_intel_dp_link_down(intel_encoder); 957 if (edp) 958 cdv_intel_edp_panel_vdd_off(intel_encoder); 959 } 960 961 static void cdv_intel_dp_commit(struct drm_encoder *encoder) 962 { 963 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 964 int edp = is_edp(intel_encoder); 965 966 if (edp) 967 cdv_intel_edp_panel_on(intel_encoder); 968 cdv_intel_dp_start_link_train(intel_encoder); 969 cdv_intel_dp_complete_link_train(intel_encoder); 970 if (edp) 971 cdv_intel_edp_backlight_on(intel_encoder); 972 } 973 974 static void 975 cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode) 976 { 977 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 978 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 979 struct drm_device *dev = encoder->dev; 980 uint32_t dp_reg = REG_READ(intel_dp->output_reg); 981 int edp = is_edp(intel_encoder); 982 983 if (mode != DRM_MODE_DPMS_ON) { 984 if (edp) { 985 cdv_intel_edp_backlight_off(intel_encoder); 986 cdv_intel_edp_panel_vdd_on(intel_encoder); 987 } 988 cdv_intel_dp_sink_dpms(intel_encoder, mode); 989 cdv_intel_dp_link_down(intel_encoder); 990 if (edp) { 991 cdv_intel_edp_panel_vdd_off(intel_encoder); 992 cdv_intel_edp_panel_off(intel_encoder); 993 } 994 } else { 995 if (edp) 996 cdv_intel_edp_panel_on(intel_encoder); 997 cdv_intel_dp_sink_dpms(intel_encoder, mode); 998 if (!(dp_reg & DP_PORT_EN)) { 999 cdv_intel_dp_start_link_train(intel_encoder); 1000 cdv_intel_dp_complete_link_train(intel_encoder); 1001 } 1002 if (edp) 1003 cdv_intel_edp_backlight_on(intel_encoder); 1004 } 1005 } 1006 1007 /* 1008 * Native read with retry for link status and receiver capability reads for 1009 * cases where the sink may still be asleep. 1010 */ 1011 static bool 1012 cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address, 1013 uint8_t *recv, int recv_bytes) 1014 { 1015 int ret, i; 1016 1017 /* 1018 * Sinks are *supposed* to come up within 1ms from an off state, 1019 * but we're also supposed to retry 3 times per the spec. 1020 */ 1021 for (i = 0; i < 3; i++) { 1022 ret = cdv_intel_dp_aux_native_read(encoder, address, recv, 1023 recv_bytes); 1024 if (ret == recv_bytes) 1025 return true; 1026 udelay(1000); 1027 } 1028 1029 return false; 1030 } 1031 1032 /* 1033 * Fetch AUX CH registers 0x202 - 0x207 which contain 1034 * link status information 1035 */ 1036 static bool 1037 cdv_intel_dp_get_link_status(struct gma_encoder *encoder) 1038 { 1039 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1040 return cdv_intel_dp_aux_native_read_retry(encoder, 1041 DP_LANE0_1_STATUS, 1042 intel_dp->link_status, 1043 DP_LINK_STATUS_SIZE); 1044 } 1045 1046 static uint8_t 1047 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1048 int r) 1049 { 1050 return link_status[r - DP_LANE0_1_STATUS]; 1051 } 1052 1053 static uint8_t 1054 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1055 int lane) 1056 { 1057 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1058 int s = ((lane & 1) ? 1059 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1060 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1061 uint8_t l = cdv_intel_dp_link_status(link_status, i); 1062 1063 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1064 } 1065 1066 static uint8_t 1067 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1068 int lane) 1069 { 1070 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1071 int s = ((lane & 1) ? 1072 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1073 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1074 uint8_t l = cdv_intel_dp_link_status(link_status, i); 1075 1076 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1077 } 1078 1079 1080 #if 0 1081 static char *voltage_names[] = { 1082 "0.4V", "0.6V", "0.8V", "1.2V" 1083 }; 1084 static char *pre_emph_names[] = { 1085 "0dB", "3.5dB", "6dB", "9.5dB" 1086 }; 1087 static char *link_train_names[] = { 1088 "pattern 1", "pattern 2", "idle", "off" 1089 }; 1090 #endif 1091 1092 #define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 1093 /* 1094 static uint8_t 1095 cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1096 { 1097 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1098 case DP_TRAIN_VOLTAGE_SWING_400: 1099 return DP_TRAIN_PRE_EMPHASIS_6; 1100 case DP_TRAIN_VOLTAGE_SWING_600: 1101 return DP_TRAIN_PRE_EMPHASIS_6; 1102 case DP_TRAIN_VOLTAGE_SWING_800: 1103 return DP_TRAIN_PRE_EMPHASIS_3_5; 1104 case DP_TRAIN_VOLTAGE_SWING_1200: 1105 default: 1106 return DP_TRAIN_PRE_EMPHASIS_0; 1107 } 1108 } 1109 */ 1110 static void 1111 cdv_intel_get_adjust_train(struct gma_encoder *encoder) 1112 { 1113 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1114 uint8_t v = 0; 1115 uint8_t p = 0; 1116 int lane; 1117 1118 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1119 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1120 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1121 1122 if (this_v > v) 1123 v = this_v; 1124 if (this_p > p) 1125 p = this_p; 1126 } 1127 1128 if (v >= CDV_DP_VOLTAGE_MAX) 1129 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1130 1131 if (p == DP_TRAIN_PRE_EMPHASIS_MASK) 1132 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1133 1134 for (lane = 0; lane < 4; lane++) 1135 intel_dp->train_set[lane] = v | p; 1136 } 1137 1138 1139 static uint8_t 1140 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1141 int lane) 1142 { 1143 int i = DP_LANE0_1_STATUS + (lane >> 1); 1144 int s = (lane & 1) * 4; 1145 uint8_t l = cdv_intel_dp_link_status(link_status, i); 1146 1147 return (l >> s) & 0xf; 1148 } 1149 1150 /* Check for clock recovery is done on all channels */ 1151 static bool 1152 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1153 { 1154 int lane; 1155 uint8_t lane_status; 1156 1157 for (lane = 0; lane < lane_count; lane++) { 1158 lane_status = cdv_intel_get_lane_status(link_status, lane); 1159 if ((lane_status & DP_LANE_CR_DONE) == 0) 1160 return false; 1161 } 1162 return true; 1163 } 1164 1165 /* Check to see if channel eq is done on all channels */ 1166 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1167 DP_LANE_CHANNEL_EQ_DONE|\ 1168 DP_LANE_SYMBOL_LOCKED) 1169 static bool 1170 cdv_intel_channel_eq_ok(struct gma_encoder *encoder) 1171 { 1172 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1173 uint8_t lane_align; 1174 uint8_t lane_status; 1175 int lane; 1176 1177 lane_align = cdv_intel_dp_link_status(intel_dp->link_status, 1178 DP_LANE_ALIGN_STATUS_UPDATED); 1179 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1180 return false; 1181 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1182 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane); 1183 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1184 return false; 1185 } 1186 return true; 1187 } 1188 1189 static bool 1190 cdv_intel_dp_set_link_train(struct gma_encoder *encoder, 1191 uint32_t dp_reg_value, 1192 uint8_t dp_train_pat) 1193 { 1194 1195 struct drm_device *dev = encoder->base.dev; 1196 int ret; 1197 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1198 1199 REG_WRITE(intel_dp->output_reg, dp_reg_value); 1200 REG_READ(intel_dp->output_reg); 1201 1202 ret = cdv_intel_dp_aux_native_write_1(encoder, 1203 DP_TRAINING_PATTERN_SET, 1204 dp_train_pat); 1205 1206 if (ret != 1) { 1207 DRM_DEBUG_KMS("Failure in setting link pattern %x\n", 1208 dp_train_pat); 1209 return false; 1210 } 1211 1212 return true; 1213 } 1214 1215 1216 static bool 1217 cdv_intel_dplink_set_level(struct gma_encoder *encoder, 1218 uint8_t dp_train_pat) 1219 { 1220 1221 int ret; 1222 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1223 1224 ret = cdv_intel_dp_aux_native_write(encoder, 1225 DP_TRAINING_LANE0_SET, 1226 intel_dp->train_set, 1227 intel_dp->lane_count); 1228 1229 if (ret != intel_dp->lane_count) { 1230 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n", 1231 intel_dp->train_set[0], intel_dp->lane_count); 1232 return false; 1233 } 1234 return true; 1235 } 1236 1237 static void 1238 cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level) 1239 { 1240 struct drm_device *dev = encoder->base.dev; 1241 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1242 struct ddi_regoff *ddi_reg; 1243 int vswing, premph, index; 1244 1245 if (intel_dp->output_reg == DP_B) 1246 ddi_reg = &ddi_DP_train_table[0]; 1247 else 1248 ddi_reg = &ddi_DP_train_table[1]; 1249 1250 vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK); 1251 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >> 1252 DP_TRAIN_PRE_EMPHASIS_SHIFT; 1253 1254 if (vswing + premph > 3) 1255 return; 1256 #ifdef CDV_FAST_LINK_TRAIN 1257 return; 1258 #endif 1259 DRM_DEBUG_KMS("Test2\n"); 1260 //return ; 1261 cdv_sb_reset(dev); 1262 /* ;Swing voltage programming 1263 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */ 1264 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A); 1265 1266 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */ 1267 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055); 1268 1269 /* ;gfx_dpio_set_reg(0x8148, 0x55338954) 1270 * The VSwing_PreEmph table is also considered based on the vswing/premp 1271 */ 1272 index = (vswing + premph) * 2; 1273 if (premph == 1 && vswing == 1) { 1274 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954); 1275 } else 1276 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]); 1277 1278 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */ 1279 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200) 1280 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040); 1281 else 1282 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040); 1283 1284 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */ 1285 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */ 1286 1287 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */ 1288 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055); 1289 1290 /* ;Pre emphasis programming 1291 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040) 1292 */ 1293 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040); 1294 1295 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */ 1296 index = 2 * premph + 1; 1297 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]); 1298 return; 1299 } 1300 1301 1302 /* Enable corresponding port and start training pattern 1 */ 1303 static void 1304 cdv_intel_dp_start_link_train(struct gma_encoder *encoder) 1305 { 1306 struct drm_device *dev = encoder->base.dev; 1307 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1308 int i; 1309 uint8_t voltage; 1310 bool clock_recovery = false; 1311 int tries; 1312 u32 reg; 1313 uint32_t DP = intel_dp->DP; 1314 1315 DP |= DP_PORT_EN; 1316 DP &= ~DP_LINK_TRAIN_MASK; 1317 1318 reg = DP; 1319 reg |= DP_LINK_TRAIN_PAT_1; 1320 /* Enable output, wait for it to become active */ 1321 REG_WRITE(intel_dp->output_reg, reg); 1322 REG_READ(intel_dp->output_reg); 1323 gma_wait_for_vblank(dev); 1324 1325 DRM_DEBUG_KMS("Link config\n"); 1326 /* Write the link configuration data */ 1327 cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET, 1328 intel_dp->link_configuration, 1329 2); 1330 1331 memset(intel_dp->train_set, 0, 4); 1332 voltage = 0; 1333 tries = 0; 1334 clock_recovery = false; 1335 1336 DRM_DEBUG_KMS("Start train\n"); 1337 reg = DP | DP_LINK_TRAIN_PAT_1; 1338 1339 1340 for (;;) { 1341 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1342 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n", 1343 intel_dp->train_set[0], 1344 intel_dp->link_configuration[0], 1345 intel_dp->link_configuration[1]); 1346 1347 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) { 1348 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n"); 1349 } 1350 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); 1351 /* Set training pattern 1 */ 1352 1353 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1); 1354 1355 udelay(200); 1356 if (!cdv_intel_dp_get_link_status(encoder)) 1357 break; 1358 1359 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n", 1360 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2], 1361 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]); 1362 1363 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1364 DRM_DEBUG_KMS("PT1 train is done\n"); 1365 clock_recovery = true; 1366 break; 1367 } 1368 1369 /* Check to see if we've tried the max voltage */ 1370 for (i = 0; i < intel_dp->lane_count; i++) 1371 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1372 break; 1373 if (i == intel_dp->lane_count) 1374 break; 1375 1376 /* Check to see if we've tried the same voltage 5 times */ 1377 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1378 ++tries; 1379 if (tries == 5) 1380 break; 1381 } else 1382 tries = 0; 1383 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1384 1385 /* Compute new intel_dp->train_set as requested by target */ 1386 cdv_intel_get_adjust_train(encoder); 1387 1388 } 1389 1390 if (!clock_recovery) { 1391 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]); 1392 } 1393 1394 intel_dp->DP = DP; 1395 } 1396 1397 static void 1398 cdv_intel_dp_complete_link_train(struct gma_encoder *encoder) 1399 { 1400 struct drm_device *dev = encoder->base.dev; 1401 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1402 bool channel_eq = false; 1403 int tries, cr_tries; 1404 u32 reg; 1405 uint32_t DP = intel_dp->DP; 1406 1407 /* channel equalization */ 1408 tries = 0; 1409 cr_tries = 0; 1410 channel_eq = false; 1411 1412 DRM_DEBUG_KMS("\n"); 1413 reg = DP | DP_LINK_TRAIN_PAT_2; 1414 1415 for (;;) { 1416 1417 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n", 1418 intel_dp->train_set[0], 1419 intel_dp->link_configuration[0], 1420 intel_dp->link_configuration[1]); 1421 /* channel eq pattern */ 1422 1423 if (!cdv_intel_dp_set_link_train(encoder, reg, 1424 DP_TRAINING_PATTERN_2)) { 1425 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n"); 1426 } 1427 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1428 1429 if (cr_tries > 5) { 1430 DRM_ERROR("failed to train DP, aborting\n"); 1431 cdv_intel_dp_link_down(encoder); 1432 break; 1433 } 1434 1435 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); 1436 1437 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2); 1438 1439 udelay(1000); 1440 if (!cdv_intel_dp_get_link_status(encoder)) 1441 break; 1442 1443 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n", 1444 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2], 1445 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]); 1446 1447 /* Make sure clock is still ok */ 1448 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1449 cdv_intel_dp_start_link_train(encoder); 1450 cr_tries++; 1451 continue; 1452 } 1453 1454 if (cdv_intel_channel_eq_ok(encoder)) { 1455 DRM_DEBUG_KMS("PT2 train is done\n"); 1456 channel_eq = true; 1457 break; 1458 } 1459 1460 /* Try 5 times, then try clock recovery if that fails */ 1461 if (tries > 5) { 1462 cdv_intel_dp_link_down(encoder); 1463 cdv_intel_dp_start_link_train(encoder); 1464 tries = 0; 1465 cr_tries++; 1466 continue; 1467 } 1468 1469 /* Compute new intel_dp->train_set as requested by target */ 1470 cdv_intel_get_adjust_train(encoder); 1471 ++tries; 1472 1473 } 1474 1475 reg = DP | DP_LINK_TRAIN_OFF; 1476 1477 REG_WRITE(intel_dp->output_reg, reg); 1478 REG_READ(intel_dp->output_reg); 1479 cdv_intel_dp_aux_native_write_1(encoder, 1480 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1481 } 1482 1483 static void 1484 cdv_intel_dp_link_down(struct gma_encoder *encoder) 1485 { 1486 struct drm_device *dev = encoder->base.dev; 1487 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1488 uint32_t DP = intel_dp->DP; 1489 1490 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1491 return; 1492 1493 DRM_DEBUG_KMS("\n"); 1494 1495 1496 { 1497 DP &= ~DP_LINK_TRAIN_MASK; 1498 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1499 } 1500 REG_READ(intel_dp->output_reg); 1501 1502 msleep(17); 1503 1504 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1505 REG_READ(intel_dp->output_reg); 1506 } 1507 1508 static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder) 1509 { 1510 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1511 enum drm_connector_status status; 1512 1513 status = connector_status_disconnected; 1514 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, 1515 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1516 { 1517 if (intel_dp->dpcd[DP_DPCD_REV] != 0) 1518 status = connector_status_connected; 1519 } 1520 if (status == connector_status_connected) 1521 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n", 1522 intel_dp->dpcd[0], intel_dp->dpcd[1], 1523 intel_dp->dpcd[2], intel_dp->dpcd[3]); 1524 return status; 1525 } 1526 1527 /** 1528 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1529 * 1530 * \return true if DP port is connected. 1531 * \return false if DP port is disconnected. 1532 */ 1533 static enum drm_connector_status 1534 cdv_intel_dp_detect(struct drm_connector *connector, bool force) 1535 { 1536 struct gma_encoder *encoder = gma_attached_encoder(connector); 1537 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1538 enum drm_connector_status status; 1539 struct edid *edid = NULL; 1540 int edp = is_edp(encoder); 1541 1542 intel_dp->has_audio = false; 1543 1544 if (edp) 1545 cdv_intel_edp_panel_vdd_on(encoder); 1546 status = cdv_dp_detect(encoder); 1547 if (status != connector_status_connected) { 1548 if (edp) 1549 cdv_intel_edp_panel_vdd_off(encoder); 1550 return status; 1551 } 1552 1553 if (intel_dp->force_audio) { 1554 intel_dp->has_audio = intel_dp->force_audio > 0; 1555 } else { 1556 edid = drm_get_edid(connector, &intel_dp->adapter); 1557 if (edid) { 1558 intel_dp->has_audio = drm_detect_monitor_audio(edid); 1559 kfree(edid); 1560 } 1561 } 1562 if (edp) 1563 cdv_intel_edp_panel_vdd_off(encoder); 1564 1565 return connector_status_connected; 1566 } 1567 1568 static int cdv_intel_dp_get_modes(struct drm_connector *connector) 1569 { 1570 struct gma_encoder *intel_encoder = gma_attached_encoder(connector); 1571 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 1572 struct edid *edid = NULL; 1573 int ret = 0; 1574 int edp = is_edp(intel_encoder); 1575 1576 1577 edid = drm_get_edid(connector, &intel_dp->adapter); 1578 if (edid) { 1579 drm_mode_connector_update_edid_property(connector, edid); 1580 ret = drm_add_edid_modes(connector, edid); 1581 kfree(edid); 1582 } 1583 1584 if (is_edp(intel_encoder)) { 1585 struct drm_device *dev = connector->dev; 1586 struct drm_psb_private *dev_priv = dev->dev_private; 1587 1588 cdv_intel_edp_panel_vdd_off(intel_encoder); 1589 if (ret) { 1590 if (edp && !intel_dp->panel_fixed_mode) { 1591 struct drm_display_mode *newmode; 1592 list_for_each_entry(newmode, &connector->probed_modes, 1593 head) { 1594 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1595 intel_dp->panel_fixed_mode = 1596 drm_mode_duplicate(dev, newmode); 1597 break; 1598 } 1599 } 1600 } 1601 1602 return ret; 1603 } 1604 if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) { 1605 intel_dp->panel_fixed_mode = 1606 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1607 if (intel_dp->panel_fixed_mode) { 1608 intel_dp->panel_fixed_mode->type |= 1609 DRM_MODE_TYPE_PREFERRED; 1610 } 1611 } 1612 if (intel_dp->panel_fixed_mode != NULL) { 1613 struct drm_display_mode *mode; 1614 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); 1615 drm_mode_probed_add(connector, mode); 1616 return 1; 1617 } 1618 } 1619 1620 return ret; 1621 } 1622 1623 static bool 1624 cdv_intel_dp_detect_audio(struct drm_connector *connector) 1625 { 1626 struct gma_encoder *encoder = gma_attached_encoder(connector); 1627 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1628 struct edid *edid; 1629 bool has_audio = false; 1630 int edp = is_edp(encoder); 1631 1632 if (edp) 1633 cdv_intel_edp_panel_vdd_on(encoder); 1634 1635 edid = drm_get_edid(connector, &intel_dp->adapter); 1636 if (edid) { 1637 has_audio = drm_detect_monitor_audio(edid); 1638 kfree(edid); 1639 } 1640 if (edp) 1641 cdv_intel_edp_panel_vdd_off(encoder); 1642 1643 return has_audio; 1644 } 1645 1646 static int 1647 cdv_intel_dp_set_property(struct drm_connector *connector, 1648 struct drm_property *property, 1649 uint64_t val) 1650 { 1651 struct drm_psb_private *dev_priv = connector->dev->dev_private; 1652 struct gma_encoder *encoder = gma_attached_encoder(connector); 1653 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1654 int ret; 1655 1656 ret = drm_object_property_set_value(&connector->base, property, val); 1657 if (ret) 1658 return ret; 1659 1660 if (property == dev_priv->force_audio_property) { 1661 int i = val; 1662 bool has_audio; 1663 1664 if (i == intel_dp->force_audio) 1665 return 0; 1666 1667 intel_dp->force_audio = i; 1668 1669 if (i == 0) 1670 has_audio = cdv_intel_dp_detect_audio(connector); 1671 else 1672 has_audio = i > 0; 1673 1674 if (has_audio == intel_dp->has_audio) 1675 return 0; 1676 1677 intel_dp->has_audio = has_audio; 1678 goto done; 1679 } 1680 1681 if (property == dev_priv->broadcast_rgb_property) { 1682 if (val == !!intel_dp->color_range) 1683 return 0; 1684 1685 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 1686 goto done; 1687 } 1688 1689 return -EINVAL; 1690 1691 done: 1692 if (encoder->base.crtc) { 1693 struct drm_crtc *crtc = encoder->base.crtc; 1694 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1695 crtc->x, crtc->y, 1696 crtc->primary->fb); 1697 } 1698 1699 return 0; 1700 } 1701 1702 static void 1703 cdv_intel_dp_destroy(struct drm_connector *connector) 1704 { 1705 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 1706 struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv; 1707 1708 if (is_edp(gma_encoder)) { 1709 /* cdv_intel_panel_destroy_backlight(connector->dev); */ 1710 if (intel_dp->panel_fixed_mode) { 1711 kfree(intel_dp->panel_fixed_mode); 1712 intel_dp->panel_fixed_mode = NULL; 1713 } 1714 } 1715 i2c_del_adapter(&intel_dp->adapter); 1716 drm_sysfs_connector_remove(connector); 1717 drm_connector_cleanup(connector); 1718 kfree(connector); 1719 } 1720 1721 static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder) 1722 { 1723 drm_encoder_cleanup(encoder); 1724 } 1725 1726 static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = { 1727 .dpms = cdv_intel_dp_dpms, 1728 .mode_fixup = cdv_intel_dp_mode_fixup, 1729 .prepare = cdv_intel_dp_prepare, 1730 .mode_set = cdv_intel_dp_mode_set, 1731 .commit = cdv_intel_dp_commit, 1732 }; 1733 1734 static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = { 1735 .dpms = drm_helper_connector_dpms, 1736 .detect = cdv_intel_dp_detect, 1737 .fill_modes = drm_helper_probe_single_connector_modes, 1738 .set_property = cdv_intel_dp_set_property, 1739 .destroy = cdv_intel_dp_destroy, 1740 }; 1741 1742 static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = { 1743 .get_modes = cdv_intel_dp_get_modes, 1744 .mode_valid = cdv_intel_dp_mode_valid, 1745 .best_encoder = gma_best_encoder, 1746 }; 1747 1748 static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = { 1749 .destroy = cdv_intel_dp_encoder_destroy, 1750 }; 1751 1752 1753 static void cdv_intel_dp_add_properties(struct drm_connector *connector) 1754 { 1755 cdv_intel_attach_force_audio_property(connector); 1756 cdv_intel_attach_broadcast_rgb_property(connector); 1757 } 1758 1759 /* check the VBT to see whether the eDP is on DP-D port */ 1760 static bool cdv_intel_dpc_is_edp(struct drm_device *dev) 1761 { 1762 struct drm_psb_private *dev_priv = dev->dev_private; 1763 struct child_device_config *p_child; 1764 int i; 1765 1766 if (!dev_priv->child_dev_num) 1767 return false; 1768 1769 for (i = 0; i < dev_priv->child_dev_num; i++) { 1770 p_child = dev_priv->child_dev + i; 1771 1772 if (p_child->dvo_port == PORT_IDPC && 1773 p_child->device_type == DEVICE_TYPE_eDP) 1774 return true; 1775 } 1776 return false; 1777 } 1778 1779 /* Cedarview display clock gating 1780 1781 We need this disable dot get correct behaviour while enabling 1782 DP/eDP. TODO - investigate if we can turn it back to normality 1783 after enabling */ 1784 static void cdv_disable_intel_clock_gating(struct drm_device *dev) 1785 { 1786 u32 reg_value; 1787 reg_value = REG_READ(DSPCLK_GATE_D); 1788 1789 reg_value |= (DPUNIT_PIPEB_GATE_DISABLE | 1790 DPUNIT_PIPEA_GATE_DISABLE | 1791 DPCUNIT_CLOCK_GATE_DISABLE | 1792 DPLSUNIT_CLOCK_GATE_DISABLE | 1793 DPOUNIT_CLOCK_GATE_DISABLE | 1794 DPIOUNIT_CLOCK_GATE_DISABLE); 1795 1796 REG_WRITE(DSPCLK_GATE_D, reg_value); 1797 1798 udelay(500); 1799 } 1800 1801 void 1802 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) 1803 { 1804 struct gma_encoder *gma_encoder; 1805 struct gma_connector *gma_connector; 1806 struct drm_connector *connector; 1807 struct drm_encoder *encoder; 1808 struct cdv_intel_dp *intel_dp; 1809 const char *name = NULL; 1810 int type = DRM_MODE_CONNECTOR_DisplayPort; 1811 1812 gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); 1813 if (!gma_encoder) 1814 return; 1815 gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); 1816 if (!gma_connector) 1817 goto err_connector; 1818 intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL); 1819 if (!intel_dp) 1820 goto err_priv; 1821 1822 if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev)) 1823 type = DRM_MODE_CONNECTOR_eDP; 1824 1825 connector = &gma_connector->base; 1826 encoder = &gma_encoder->base; 1827 1828 drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type); 1829 drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS); 1830 1831 gma_connector_attach_encoder(gma_connector, gma_encoder); 1832 1833 if (type == DRM_MODE_CONNECTOR_DisplayPort) 1834 gma_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1835 else 1836 gma_encoder->type = INTEL_OUTPUT_EDP; 1837 1838 1839 gma_encoder->dev_priv=intel_dp; 1840 intel_dp->encoder = gma_encoder; 1841 intel_dp->output_reg = output_reg; 1842 1843 drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs); 1844 drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs); 1845 1846 connector->polled = DRM_CONNECTOR_POLL_HPD; 1847 connector->interlace_allowed = false; 1848 connector->doublescan_allowed = false; 1849 1850 drm_sysfs_connector_add(connector); 1851 1852 /* Set up the DDC bus. */ 1853 switch (output_reg) { 1854 case DP_B: 1855 name = "DPDDC-B"; 1856 gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT); 1857 break; 1858 case DP_C: 1859 name = "DPDDC-C"; 1860 gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT); 1861 break; 1862 } 1863 1864 cdv_disable_intel_clock_gating(dev); 1865 1866 cdv_intel_dp_i2c_init(gma_connector, gma_encoder, name); 1867 /* FIXME:fail check */ 1868 cdv_intel_dp_add_properties(connector); 1869 1870 if (is_edp(gma_encoder)) { 1871 int ret; 1872 struct edp_power_seq cur; 1873 u32 pp_on, pp_off, pp_div; 1874 u32 pwm_ctrl; 1875 1876 pp_on = REG_READ(PP_CONTROL); 1877 pp_on &= ~PANEL_UNLOCK_MASK; 1878 pp_on |= PANEL_UNLOCK_REGS; 1879 1880 REG_WRITE(PP_CONTROL, pp_on); 1881 1882 pwm_ctrl = REG_READ(BLC_PWM_CTL2); 1883 pwm_ctrl |= PWM_PIPE_B; 1884 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl); 1885 1886 pp_on = REG_READ(PP_ON_DELAYS); 1887 pp_off = REG_READ(PP_OFF_DELAYS); 1888 pp_div = REG_READ(PP_DIVISOR); 1889 1890 /* Pull timing values out of registers */ 1891 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 1892 PANEL_POWER_UP_DELAY_SHIFT; 1893 1894 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 1895 PANEL_LIGHT_ON_DELAY_SHIFT; 1896 1897 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 1898 PANEL_LIGHT_OFF_DELAY_SHIFT; 1899 1900 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 1901 PANEL_POWER_DOWN_DELAY_SHIFT; 1902 1903 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 1904 PANEL_POWER_CYCLE_DELAY_SHIFT); 1905 1906 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 1907 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 1908 1909 1910 intel_dp->panel_power_up_delay = cur.t1_t3 / 10; 1911 intel_dp->backlight_on_delay = cur.t8 / 10; 1912 intel_dp->backlight_off_delay = cur.t9 / 10; 1913 intel_dp->panel_power_down_delay = cur.t10 / 10; 1914 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100; 1915 1916 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 1917 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 1918 intel_dp->panel_power_cycle_delay); 1919 1920 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 1921 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 1922 1923 1924 cdv_intel_edp_panel_vdd_on(gma_encoder); 1925 ret = cdv_intel_dp_aux_native_read(gma_encoder, DP_DPCD_REV, 1926 intel_dp->dpcd, 1927 sizeof(intel_dp->dpcd)); 1928 cdv_intel_edp_panel_vdd_off(gma_encoder); 1929 if (ret == 0) { 1930 /* if this fails, presume the device is a ghost */ 1931 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 1932 cdv_intel_dp_encoder_destroy(encoder); 1933 cdv_intel_dp_destroy(connector); 1934 goto err_priv; 1935 } else { 1936 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n", 1937 intel_dp->dpcd[0], intel_dp->dpcd[1], 1938 intel_dp->dpcd[2], intel_dp->dpcd[3]); 1939 1940 } 1941 /* The CDV reference driver moves pnale backlight setup into the displays that 1942 have a backlight: this is a good idea and one we should probably adopt, however 1943 we need to migrate all the drivers before we can do that */ 1944 /*cdv_intel_panel_setup_backlight(dev); */ 1945 } 1946 return; 1947 1948 err_priv: 1949 kfree(gma_connector); 1950 err_connector: 1951 kfree(gma_encoder); 1952 } 1953