1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/module.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_crtc_helper.h> 34 #include "psb_drv.h" 35 #include "psb_intel_drv.h" 36 #include "psb_intel_reg.h" 37 #include "gma_display.h" 38 #include <drm/drm_dp_helper.h> 39 40 #define _wait_for(COND, MS, W) ({ \ 41 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 42 int ret__ = 0; \ 43 while (! (COND)) { \ 44 if (time_after(jiffies, timeout__)) { \ 45 ret__ = -ETIMEDOUT; \ 46 break; \ 47 } \ 48 if (W && !in_dbg_master()) msleep(W); \ 49 } \ 50 ret__; \ 51 }) 52 53 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 54 55 #define DP_LINK_STATUS_SIZE 6 56 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 57 58 #define DP_LINK_CONFIGURATION_SIZE 9 59 60 #define CDV_FAST_LINK_TRAIN 1 61 62 struct cdv_intel_dp { 63 uint32_t output_reg; 64 uint32_t DP; 65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 66 bool has_audio; 67 int force_audio; 68 uint32_t color_range; 69 uint8_t link_bw; 70 uint8_t lane_count; 71 uint8_t dpcd[4]; 72 struct gma_encoder *encoder; 73 struct i2c_adapter adapter; 74 struct i2c_algo_dp_aux_data algo; 75 uint8_t train_set[4]; 76 uint8_t link_status[DP_LINK_STATUS_SIZE]; 77 int panel_power_up_delay; 78 int panel_power_down_delay; 79 int panel_power_cycle_delay; 80 int backlight_on_delay; 81 int backlight_off_delay; 82 struct drm_display_mode *panel_fixed_mode; /* for eDP */ 83 bool panel_on; 84 }; 85 86 struct ddi_regoff { 87 uint32_t PreEmph1; 88 uint32_t PreEmph2; 89 uint32_t VSwing1; 90 uint32_t VSwing2; 91 uint32_t VSwing3; 92 uint32_t VSwing4; 93 uint32_t VSwing5; 94 }; 95 96 static struct ddi_regoff ddi_DP_train_table[] = { 97 {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154, 98 .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150, 99 .VSwing5 = 0x8158,}, 100 {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254, 101 .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250, 102 .VSwing5 = 0x8258,}, 103 }; 104 105 static uint32_t dp_vswing_premph_table[] = { 106 0x55338954, 0x4000, 107 0x554d8954, 0x2000, 108 0x55668954, 0, 109 0x559ac0d4, 0x6000, 110 }; 111 /** 112 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 113 * @intel_dp: DP struct 114 * 115 * If a CPU or PCH DP output is attached to an eDP panel, this function 116 * will return true, and false otherwise. 117 */ 118 static bool is_edp(struct gma_encoder *encoder) 119 { 120 return encoder->type == INTEL_OUTPUT_EDP; 121 } 122 123 124 static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder); 125 static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder); 126 static void cdv_intel_dp_link_down(struct gma_encoder *encoder); 127 128 static int 129 cdv_intel_dp_max_lane_count(struct gma_encoder *encoder) 130 { 131 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 132 int max_lane_count = 4; 133 134 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 135 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; 136 switch (max_lane_count) { 137 case 1: case 2: case 4: 138 break; 139 default: 140 max_lane_count = 4; 141 } 142 } 143 return max_lane_count; 144 } 145 146 static int 147 cdv_intel_dp_max_link_bw(struct gma_encoder *encoder) 148 { 149 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 151 152 switch (max_link_bw) { 153 case DP_LINK_BW_1_62: 154 case DP_LINK_BW_2_7: 155 break; 156 default: 157 max_link_bw = DP_LINK_BW_1_62; 158 break; 159 } 160 return max_link_bw; 161 } 162 163 static int 164 cdv_intel_dp_link_clock(uint8_t link_bw) 165 { 166 if (link_bw == DP_LINK_BW_2_7) 167 return 270000; 168 else 169 return 162000; 170 } 171 172 static int 173 cdv_intel_dp_link_required(int pixel_clock, int bpp) 174 { 175 return (pixel_clock * bpp + 7) / 8; 176 } 177 178 static int 179 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes) 180 { 181 return (max_link_clock * max_lanes * 19) / 20; 182 } 183 184 static void cdv_intel_edp_panel_vdd_on(struct gma_encoder *intel_encoder) 185 { 186 struct drm_device *dev = intel_encoder->base.dev; 187 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 188 u32 pp; 189 190 if (intel_dp->panel_on) { 191 DRM_DEBUG_KMS("Skip VDD on because of panel on\n"); 192 return; 193 } 194 DRM_DEBUG_KMS("\n"); 195 196 pp = REG_READ(PP_CONTROL); 197 198 pp |= EDP_FORCE_VDD; 199 REG_WRITE(PP_CONTROL, pp); 200 REG_READ(PP_CONTROL); 201 msleep(intel_dp->panel_power_up_delay); 202 } 203 204 static void cdv_intel_edp_panel_vdd_off(struct gma_encoder *intel_encoder) 205 { 206 struct drm_device *dev = intel_encoder->base.dev; 207 u32 pp; 208 209 DRM_DEBUG_KMS("\n"); 210 pp = REG_READ(PP_CONTROL); 211 212 pp &= ~EDP_FORCE_VDD; 213 REG_WRITE(PP_CONTROL, pp); 214 REG_READ(PP_CONTROL); 215 216 } 217 218 /* Returns true if the panel was already on when called */ 219 static bool cdv_intel_edp_panel_on(struct gma_encoder *intel_encoder) 220 { 221 struct drm_device *dev = intel_encoder->base.dev; 222 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 223 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE; 224 225 if (intel_dp->panel_on) 226 return true; 227 228 DRM_DEBUG_KMS("\n"); 229 pp = REG_READ(PP_CONTROL); 230 pp &= ~PANEL_UNLOCK_MASK; 231 232 pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON); 233 REG_WRITE(PP_CONTROL, pp); 234 REG_READ(PP_CONTROL); 235 236 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { 237 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); 238 intel_dp->panel_on = false; 239 } else 240 intel_dp->panel_on = true; 241 msleep(intel_dp->panel_power_up_delay); 242 243 return false; 244 } 245 246 static void cdv_intel_edp_panel_off (struct gma_encoder *intel_encoder) 247 { 248 struct drm_device *dev = intel_encoder->base.dev; 249 u32 pp, idle_off_mask = PP_ON ; 250 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 251 252 DRM_DEBUG_KMS("\n"); 253 254 pp = REG_READ(PP_CONTROL); 255 256 if ((pp & POWER_TARGET_ON) == 0) 257 return; 258 259 intel_dp->panel_on = false; 260 pp &= ~PANEL_UNLOCK_MASK; 261 /* ILK workaround: disable reset around power sequence */ 262 263 pp &= ~POWER_TARGET_ON; 264 pp &= ~EDP_FORCE_VDD; 265 pp &= ~EDP_BLC_ENABLE; 266 REG_WRITE(PP_CONTROL, pp); 267 REG_READ(PP_CONTROL); 268 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS)); 269 270 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { 271 DRM_DEBUG_KMS("Error in turning off Panel\n"); 272 } 273 274 msleep(intel_dp->panel_power_cycle_delay); 275 DRM_DEBUG_KMS("Over\n"); 276 } 277 278 static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder) 279 { 280 struct drm_device *dev = intel_encoder->base.dev; 281 u32 pp; 282 283 DRM_DEBUG_KMS("\n"); 284 /* 285 * If we enable the backlight right away following a panel power 286 * on, we may see slight flicker as the panel syncs with the eDP 287 * link. So delay a bit to make sure the image is solid before 288 * allowing it to appear. 289 */ 290 msleep(300); 291 pp = REG_READ(PP_CONTROL); 292 293 pp |= EDP_BLC_ENABLE; 294 REG_WRITE(PP_CONTROL, pp); 295 gma_backlight_enable(dev); 296 } 297 298 static void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder) 299 { 300 struct drm_device *dev = intel_encoder->base.dev; 301 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 302 u32 pp; 303 304 DRM_DEBUG_KMS("\n"); 305 gma_backlight_disable(dev); 306 msleep(10); 307 pp = REG_READ(PP_CONTROL); 308 309 pp &= ~EDP_BLC_ENABLE; 310 REG_WRITE(PP_CONTROL, pp); 311 msleep(intel_dp->backlight_off_delay); 312 } 313 314 static int 315 cdv_intel_dp_mode_valid(struct drm_connector *connector, 316 struct drm_display_mode *mode) 317 { 318 struct gma_encoder *encoder = gma_attached_encoder(connector); 319 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 320 int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder)); 321 int max_lanes = cdv_intel_dp_max_lane_count(encoder); 322 struct drm_psb_private *dev_priv = connector->dev->dev_private; 323 324 if (is_edp(encoder) && intel_dp->panel_fixed_mode) { 325 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) 326 return MODE_PANEL; 327 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) 328 return MODE_PANEL; 329 } 330 331 /* only refuse the mode on non eDP since we have seen some weird eDP panels 332 which are outside spec tolerances but somehow work by magic */ 333 if (!is_edp(encoder) && 334 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp) 335 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))) 336 return MODE_CLOCK_HIGH; 337 338 if (is_edp(encoder)) { 339 if (cdv_intel_dp_link_required(mode->clock, 24) 340 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)) 341 return MODE_CLOCK_HIGH; 342 343 } 344 if (mode->clock < 10000) 345 return MODE_CLOCK_LOW; 346 347 return MODE_OK; 348 } 349 350 static uint32_t 351 pack_aux(uint8_t *src, int src_bytes) 352 { 353 int i; 354 uint32_t v = 0; 355 356 if (src_bytes > 4) 357 src_bytes = 4; 358 for (i = 0; i < src_bytes; i++) 359 v |= ((uint32_t) src[i]) << ((3-i) * 8); 360 return v; 361 } 362 363 static void 364 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 365 { 366 int i; 367 if (dst_bytes > 4) 368 dst_bytes = 4; 369 for (i = 0; i < dst_bytes; i++) 370 dst[i] = src >> ((3-i) * 8); 371 } 372 373 static int 374 cdv_intel_dp_aux_ch(struct gma_encoder *encoder, 375 uint8_t *send, int send_bytes, 376 uint8_t *recv, int recv_size) 377 { 378 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 379 uint32_t output_reg = intel_dp->output_reg; 380 struct drm_device *dev = encoder->base.dev; 381 uint32_t ch_ctl = output_reg + 0x10; 382 uint32_t ch_data = ch_ctl + 4; 383 int i; 384 int recv_bytes; 385 uint32_t status; 386 uint32_t aux_clock_divider; 387 int try, precharge; 388 389 /* The clock divider is based off the hrawclk, 390 * and would like to run at 2MHz. So, take the 391 * hrawclk value and divide by 2 and use that 392 * On CDV platform it uses 200MHz as hrawclk. 393 * 394 */ 395 aux_clock_divider = 200 / 2; 396 397 precharge = 4; 398 if (is_edp(encoder)) 399 precharge = 10; 400 401 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { 402 DRM_ERROR("dp_aux_ch not started status 0x%08x\n", 403 REG_READ(ch_ctl)); 404 return -EBUSY; 405 } 406 407 /* Must try at least 3 times according to DP spec */ 408 for (try = 0; try < 5; try++) { 409 /* Load the send data into the aux channel data registers */ 410 for (i = 0; i < send_bytes; i += 4) 411 REG_WRITE(ch_data + i, 412 pack_aux(send + i, send_bytes - i)); 413 414 /* Send the command and wait for it to complete */ 415 REG_WRITE(ch_ctl, 416 DP_AUX_CH_CTL_SEND_BUSY | 417 DP_AUX_CH_CTL_TIME_OUT_400us | 418 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 419 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 420 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 421 DP_AUX_CH_CTL_DONE | 422 DP_AUX_CH_CTL_TIME_OUT_ERROR | 423 DP_AUX_CH_CTL_RECEIVE_ERROR); 424 for (;;) { 425 status = REG_READ(ch_ctl); 426 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 427 break; 428 udelay(100); 429 } 430 431 /* Clear done status and any errors */ 432 REG_WRITE(ch_ctl, 433 status | 434 DP_AUX_CH_CTL_DONE | 435 DP_AUX_CH_CTL_TIME_OUT_ERROR | 436 DP_AUX_CH_CTL_RECEIVE_ERROR); 437 if (status & DP_AUX_CH_CTL_DONE) 438 break; 439 } 440 441 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 443 return -EBUSY; 444 } 445 446 /* Check for timeout or receive error. 447 * Timeouts occur when the sink is not connected 448 */ 449 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 451 return -EIO; 452 } 453 454 /* Timeouts occur when the device isn't connected, so they're 455 * "normal" -- don't fill the kernel log with these */ 456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 458 return -ETIMEDOUT; 459 } 460 461 /* Unload any bytes sent back from the other side */ 462 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 464 if (recv_bytes > recv_size) 465 recv_bytes = recv_size; 466 467 for (i = 0; i < recv_bytes; i += 4) 468 unpack_aux(REG_READ(ch_data + i), 469 recv + i, recv_bytes - i); 470 471 return recv_bytes; 472 } 473 474 /* Write data to the aux channel in native mode */ 475 static int 476 cdv_intel_dp_aux_native_write(struct gma_encoder *encoder, 477 uint16_t address, uint8_t *send, int send_bytes) 478 { 479 int ret; 480 uint8_t msg[20]; 481 int msg_bytes; 482 uint8_t ack; 483 484 if (send_bytes > 16) 485 return -1; 486 msg[0] = AUX_NATIVE_WRITE << 4; 487 msg[1] = address >> 8; 488 msg[2] = address & 0xff; 489 msg[3] = send_bytes - 1; 490 memcpy(&msg[4], send, send_bytes); 491 msg_bytes = send_bytes + 4; 492 for (;;) { 493 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1); 494 if (ret < 0) 495 return ret; 496 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 497 break; 498 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 499 udelay(100); 500 else 501 return -EIO; 502 } 503 return send_bytes; 504 } 505 506 /* Write a single byte to the aux channel in native mode */ 507 static int 508 cdv_intel_dp_aux_native_write_1(struct gma_encoder *encoder, 509 uint16_t address, uint8_t byte) 510 { 511 return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1); 512 } 513 514 /* read bytes from a native aux channel */ 515 static int 516 cdv_intel_dp_aux_native_read(struct gma_encoder *encoder, 517 uint16_t address, uint8_t *recv, int recv_bytes) 518 { 519 uint8_t msg[4]; 520 int msg_bytes; 521 uint8_t reply[20]; 522 int reply_bytes; 523 uint8_t ack; 524 int ret; 525 526 msg[0] = AUX_NATIVE_READ << 4; 527 msg[1] = address >> 8; 528 msg[2] = address & 0xff; 529 msg[3] = recv_bytes - 1; 530 531 msg_bytes = 4; 532 reply_bytes = recv_bytes + 1; 533 534 for (;;) { 535 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, 536 reply, reply_bytes); 537 if (ret == 0) 538 return -EPROTO; 539 if (ret < 0) 540 return ret; 541 ack = reply[0]; 542 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 543 memcpy(recv, reply + 1, ret - 1); 544 return ret - 1; 545 } 546 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 547 udelay(100); 548 else 549 return -EIO; 550 } 551 } 552 553 static int 554 cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 555 uint8_t write_byte, uint8_t *read_byte) 556 { 557 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 558 struct cdv_intel_dp *intel_dp = container_of(adapter, 559 struct cdv_intel_dp, 560 adapter); 561 struct gma_encoder *encoder = intel_dp->encoder; 562 uint16_t address = algo_data->address; 563 uint8_t msg[5]; 564 uint8_t reply[2]; 565 unsigned retry; 566 int msg_bytes; 567 int reply_bytes; 568 int ret; 569 570 /* Set up the command byte */ 571 if (mode & MODE_I2C_READ) 572 msg[0] = AUX_I2C_READ << 4; 573 else 574 msg[0] = AUX_I2C_WRITE << 4; 575 576 if (!(mode & MODE_I2C_STOP)) 577 msg[0] |= AUX_I2C_MOT << 4; 578 579 msg[1] = address >> 8; 580 msg[2] = address; 581 582 switch (mode) { 583 case MODE_I2C_WRITE: 584 msg[3] = 0; 585 msg[4] = write_byte; 586 msg_bytes = 5; 587 reply_bytes = 1; 588 break; 589 case MODE_I2C_READ: 590 msg[3] = 0; 591 msg_bytes = 4; 592 reply_bytes = 2; 593 break; 594 default: 595 msg_bytes = 3; 596 reply_bytes = 1; 597 break; 598 } 599 600 for (retry = 0; retry < 5; retry++) { 601 ret = cdv_intel_dp_aux_ch(encoder, 602 msg, msg_bytes, 603 reply, reply_bytes); 604 if (ret < 0) { 605 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 606 return ret; 607 } 608 609 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 610 case AUX_NATIVE_REPLY_ACK: 611 /* I2C-over-AUX Reply field is only valid 612 * when paired with AUX ACK. 613 */ 614 break; 615 case AUX_NATIVE_REPLY_NACK: 616 DRM_DEBUG_KMS("aux_ch native nack\n"); 617 return -EREMOTEIO; 618 case AUX_NATIVE_REPLY_DEFER: 619 udelay(100); 620 continue; 621 default: 622 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 623 reply[0]); 624 return -EREMOTEIO; 625 } 626 627 switch (reply[0] & AUX_I2C_REPLY_MASK) { 628 case AUX_I2C_REPLY_ACK: 629 if (mode == MODE_I2C_READ) { 630 *read_byte = reply[1]; 631 } 632 return reply_bytes - 1; 633 case AUX_I2C_REPLY_NACK: 634 DRM_DEBUG_KMS("aux_i2c nack\n"); 635 return -EREMOTEIO; 636 case AUX_I2C_REPLY_DEFER: 637 DRM_DEBUG_KMS("aux_i2c defer\n"); 638 udelay(100); 639 break; 640 default: 641 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 642 return -EREMOTEIO; 643 } 644 } 645 646 DRM_ERROR("too many retries, giving up\n"); 647 return -EREMOTEIO; 648 } 649 650 static int 651 cdv_intel_dp_i2c_init(struct gma_connector *connector, 652 struct gma_encoder *encoder, const char *name) 653 { 654 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 655 int ret; 656 657 DRM_DEBUG_KMS("i2c_init %s\n", name); 658 659 intel_dp->algo.running = false; 660 intel_dp->algo.address = 0; 661 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch; 662 663 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); 664 intel_dp->adapter.owner = THIS_MODULE; 665 intel_dp->adapter.class = I2C_CLASS_DDC; 666 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 667 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 668 intel_dp->adapter.algo_data = &intel_dp->algo; 669 intel_dp->adapter.dev.parent = connector->base.kdev; 670 671 if (is_edp(encoder)) 672 cdv_intel_edp_panel_vdd_on(encoder); 673 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 674 if (is_edp(encoder)) 675 cdv_intel_edp_panel_vdd_off(encoder); 676 677 return ret; 678 } 679 680 void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 681 struct drm_display_mode *adjusted_mode) 682 { 683 adjusted_mode->hdisplay = fixed_mode->hdisplay; 684 adjusted_mode->hsync_start = fixed_mode->hsync_start; 685 adjusted_mode->hsync_end = fixed_mode->hsync_end; 686 adjusted_mode->htotal = fixed_mode->htotal; 687 688 adjusted_mode->vdisplay = fixed_mode->vdisplay; 689 adjusted_mode->vsync_start = fixed_mode->vsync_start; 690 adjusted_mode->vsync_end = fixed_mode->vsync_end; 691 adjusted_mode->vtotal = fixed_mode->vtotal; 692 693 adjusted_mode->clock = fixed_mode->clock; 694 695 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); 696 } 697 698 static bool 699 cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode, 700 struct drm_display_mode *adjusted_mode) 701 { 702 struct drm_psb_private *dev_priv = encoder->dev->dev_private; 703 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 704 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 705 int lane_count, clock; 706 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder); 707 int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; 708 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 709 int refclock = mode->clock; 710 int bpp = 24; 711 712 if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) { 713 cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); 714 refclock = intel_dp->panel_fixed_mode->clock; 715 bpp = dev_priv->edp.bpp; 716 } 717 718 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 719 for (clock = max_clock; clock >= 0; clock--) { 720 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); 721 722 if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) { 723 intel_dp->link_bw = bws[clock]; 724 intel_dp->lane_count = lane_count; 725 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); 726 DRM_DEBUG_KMS("Display port link bw %02x lane " 727 "count %d clock %d\n", 728 intel_dp->link_bw, intel_dp->lane_count, 729 adjusted_mode->clock); 730 return true; 731 } 732 } 733 } 734 if (is_edp(intel_encoder)) { 735 /* okay we failed just pick the highest */ 736 intel_dp->lane_count = max_lane_count; 737 intel_dp->link_bw = bws[max_clock]; 738 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); 739 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 740 "count %d clock %d\n", 741 intel_dp->link_bw, intel_dp->lane_count, 742 adjusted_mode->clock); 743 744 return true; 745 } 746 return false; 747 } 748 749 struct cdv_intel_dp_m_n { 750 uint32_t tu; 751 uint32_t gmch_m; 752 uint32_t gmch_n; 753 uint32_t link_m; 754 uint32_t link_n; 755 }; 756 757 static void 758 cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den) 759 { 760 /* 761 while (*num > 0xffffff || *den > 0xffffff) { 762 *num >>= 1; 763 *den >>= 1; 764 }*/ 765 uint64_t value, m; 766 m = *num; 767 value = m * (0x800000); 768 m = do_div(value, *den); 769 *num = value; 770 *den = 0x800000; 771 } 772 773 static void 774 cdv_intel_dp_compute_m_n(int bpp, 775 int nlanes, 776 int pixel_clock, 777 int link_clock, 778 struct cdv_intel_dp_m_n *m_n) 779 { 780 m_n->tu = 64; 781 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; 782 m_n->gmch_n = link_clock * nlanes; 783 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 784 m_n->link_m = pixel_clock; 785 m_n->link_n = link_clock; 786 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 787 } 788 789 void 790 cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 791 struct drm_display_mode *adjusted_mode) 792 { 793 struct drm_device *dev = crtc->dev; 794 struct drm_psb_private *dev_priv = dev->dev_private; 795 struct drm_mode_config *mode_config = &dev->mode_config; 796 struct drm_encoder *encoder; 797 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 798 int lane_count = 4, bpp = 24; 799 struct cdv_intel_dp_m_n m_n; 800 int pipe = gma_crtc->pipe; 801 802 /* 803 * Find the lane count in the intel_encoder private 804 */ 805 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 806 struct gma_encoder *intel_encoder; 807 struct cdv_intel_dp *intel_dp; 808 809 if (encoder->crtc != crtc) 810 continue; 811 812 intel_encoder = to_gma_encoder(encoder); 813 intel_dp = intel_encoder->dev_priv; 814 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 815 lane_count = intel_dp->lane_count; 816 break; 817 } else if (is_edp(intel_encoder)) { 818 lane_count = intel_dp->lane_count; 819 bpp = dev_priv->edp.bpp; 820 break; 821 } 822 } 823 824 /* 825 * Compute the GMCH and Link ratios. The '3' here is 826 * the number of bytes_per_pixel post-LUT, which we always 827 * set up for 8-bits of R/G/B, or 3 bytes total. 828 */ 829 cdv_intel_dp_compute_m_n(bpp, lane_count, 830 mode->clock, adjusted_mode->clock, &m_n); 831 832 { 833 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 834 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 835 m_n.gmch_m); 836 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 837 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 838 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 839 } 840 } 841 842 static void 843 cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 844 struct drm_display_mode *adjusted_mode) 845 { 846 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 847 struct drm_crtc *crtc = encoder->crtc; 848 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 849 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 850 struct drm_device *dev = encoder->dev; 851 852 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 853 intel_dp->DP |= intel_dp->color_range; 854 855 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 856 intel_dp->DP |= DP_SYNC_HS_HIGH; 857 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 858 intel_dp->DP |= DP_SYNC_VS_HIGH; 859 860 intel_dp->DP |= DP_LINK_TRAIN_OFF; 861 862 switch (intel_dp->lane_count) { 863 case 1: 864 intel_dp->DP |= DP_PORT_WIDTH_1; 865 break; 866 case 2: 867 intel_dp->DP |= DP_PORT_WIDTH_2; 868 break; 869 case 4: 870 intel_dp->DP |= DP_PORT_WIDTH_4; 871 break; 872 } 873 if (intel_dp->has_audio) 874 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 875 876 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 877 intel_dp->link_configuration[0] = intel_dp->link_bw; 878 intel_dp->link_configuration[1] = intel_dp->lane_count; 879 880 /* 881 * Check for DPCD version > 1.1 and enhanced framing support 882 */ 883 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 884 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 885 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 886 intel_dp->DP |= DP_ENHANCED_FRAMING; 887 } 888 889 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 890 if (gma_crtc->pipe == 1) 891 intel_dp->DP |= DP_PIPEB_SELECT; 892 893 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN)); 894 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP); 895 if (is_edp(intel_encoder)) { 896 uint32_t pfit_control; 897 cdv_intel_edp_panel_on(intel_encoder); 898 899 if (mode->hdisplay != adjusted_mode->hdisplay || 900 mode->vdisplay != adjusted_mode->vdisplay) 901 pfit_control = PFIT_ENABLE; 902 else 903 pfit_control = 0; 904 905 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT; 906 907 REG_WRITE(PFIT_CONTROL, pfit_control); 908 } 909 } 910 911 912 /* If the sink supports it, try to set the power state appropriately */ 913 static void cdv_intel_dp_sink_dpms(struct gma_encoder *encoder, int mode) 914 { 915 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 916 int ret, i; 917 918 /* Should have a valid DPCD by this point */ 919 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 920 return; 921 922 if (mode != DRM_MODE_DPMS_ON) { 923 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER, 924 DP_SET_POWER_D3); 925 if (ret != 1) 926 DRM_DEBUG_DRIVER("failed to write sink power state\n"); 927 } else { 928 /* 929 * When turning on, we need to retry for 1ms to give the sink 930 * time to wake up. 931 */ 932 for (i = 0; i < 3; i++) { 933 ret = cdv_intel_dp_aux_native_write_1(encoder, 934 DP_SET_POWER, 935 DP_SET_POWER_D0); 936 if (ret == 1) 937 break; 938 udelay(1000); 939 } 940 } 941 } 942 943 static void cdv_intel_dp_prepare(struct drm_encoder *encoder) 944 { 945 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 946 int edp = is_edp(intel_encoder); 947 948 if (edp) { 949 cdv_intel_edp_backlight_off(intel_encoder); 950 cdv_intel_edp_panel_off(intel_encoder); 951 cdv_intel_edp_panel_vdd_on(intel_encoder); 952 } 953 /* Wake up the sink first */ 954 cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON); 955 cdv_intel_dp_link_down(intel_encoder); 956 if (edp) 957 cdv_intel_edp_panel_vdd_off(intel_encoder); 958 } 959 960 static void cdv_intel_dp_commit(struct drm_encoder *encoder) 961 { 962 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 963 int edp = is_edp(intel_encoder); 964 965 if (edp) 966 cdv_intel_edp_panel_on(intel_encoder); 967 cdv_intel_dp_start_link_train(intel_encoder); 968 cdv_intel_dp_complete_link_train(intel_encoder); 969 if (edp) 970 cdv_intel_edp_backlight_on(intel_encoder); 971 } 972 973 static void 974 cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode) 975 { 976 struct gma_encoder *intel_encoder = to_gma_encoder(encoder); 977 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 978 struct drm_device *dev = encoder->dev; 979 uint32_t dp_reg = REG_READ(intel_dp->output_reg); 980 int edp = is_edp(intel_encoder); 981 982 if (mode != DRM_MODE_DPMS_ON) { 983 if (edp) { 984 cdv_intel_edp_backlight_off(intel_encoder); 985 cdv_intel_edp_panel_vdd_on(intel_encoder); 986 } 987 cdv_intel_dp_sink_dpms(intel_encoder, mode); 988 cdv_intel_dp_link_down(intel_encoder); 989 if (edp) { 990 cdv_intel_edp_panel_vdd_off(intel_encoder); 991 cdv_intel_edp_panel_off(intel_encoder); 992 } 993 } else { 994 if (edp) 995 cdv_intel_edp_panel_on(intel_encoder); 996 cdv_intel_dp_sink_dpms(intel_encoder, mode); 997 if (!(dp_reg & DP_PORT_EN)) { 998 cdv_intel_dp_start_link_train(intel_encoder); 999 cdv_intel_dp_complete_link_train(intel_encoder); 1000 } 1001 if (edp) 1002 cdv_intel_edp_backlight_on(intel_encoder); 1003 } 1004 } 1005 1006 /* 1007 * Native read with retry for link status and receiver capability reads for 1008 * cases where the sink may still be asleep. 1009 */ 1010 static bool 1011 cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address, 1012 uint8_t *recv, int recv_bytes) 1013 { 1014 int ret, i; 1015 1016 /* 1017 * Sinks are *supposed* to come up within 1ms from an off state, 1018 * but we're also supposed to retry 3 times per the spec. 1019 */ 1020 for (i = 0; i < 3; i++) { 1021 ret = cdv_intel_dp_aux_native_read(encoder, address, recv, 1022 recv_bytes); 1023 if (ret == recv_bytes) 1024 return true; 1025 udelay(1000); 1026 } 1027 1028 return false; 1029 } 1030 1031 /* 1032 * Fetch AUX CH registers 0x202 - 0x207 which contain 1033 * link status information 1034 */ 1035 static bool 1036 cdv_intel_dp_get_link_status(struct gma_encoder *encoder) 1037 { 1038 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1039 return cdv_intel_dp_aux_native_read_retry(encoder, 1040 DP_LANE0_1_STATUS, 1041 intel_dp->link_status, 1042 DP_LINK_STATUS_SIZE); 1043 } 1044 1045 static uint8_t 1046 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1047 int r) 1048 { 1049 return link_status[r - DP_LANE0_1_STATUS]; 1050 } 1051 1052 static uint8_t 1053 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], 1054 int lane) 1055 { 1056 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1057 int s = ((lane & 1) ? 1058 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 1059 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 1060 uint8_t l = cdv_intel_dp_link_status(link_status, i); 1061 1062 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 1063 } 1064 1065 static uint8_t 1066 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], 1067 int lane) 1068 { 1069 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 1070 int s = ((lane & 1) ? 1071 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 1072 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 1073 uint8_t l = cdv_intel_dp_link_status(link_status, i); 1074 1075 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 1076 } 1077 1078 1079 #if 0 1080 static char *voltage_names[] = { 1081 "0.4V", "0.6V", "0.8V", "1.2V" 1082 }; 1083 static char *pre_emph_names[] = { 1084 "0dB", "3.5dB", "6dB", "9.5dB" 1085 }; 1086 static char *link_train_names[] = { 1087 "pattern 1", "pattern 2", "idle", "off" 1088 }; 1089 #endif 1090 1091 #define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 1092 /* 1093 static uint8_t 1094 cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing) 1095 { 1096 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1097 case DP_TRAIN_VOLTAGE_SWING_400: 1098 return DP_TRAIN_PRE_EMPHASIS_6; 1099 case DP_TRAIN_VOLTAGE_SWING_600: 1100 return DP_TRAIN_PRE_EMPHASIS_6; 1101 case DP_TRAIN_VOLTAGE_SWING_800: 1102 return DP_TRAIN_PRE_EMPHASIS_3_5; 1103 case DP_TRAIN_VOLTAGE_SWING_1200: 1104 default: 1105 return DP_TRAIN_PRE_EMPHASIS_0; 1106 } 1107 } 1108 */ 1109 static void 1110 cdv_intel_get_adjust_train(struct gma_encoder *encoder) 1111 { 1112 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1113 uint8_t v = 0; 1114 uint8_t p = 0; 1115 int lane; 1116 1117 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1118 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane); 1119 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); 1120 1121 if (this_v > v) 1122 v = this_v; 1123 if (this_p > p) 1124 p = this_p; 1125 } 1126 1127 if (v >= CDV_DP_VOLTAGE_MAX) 1128 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; 1129 1130 if (p == DP_TRAIN_PRE_EMPHASIS_MASK) 1131 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1132 1133 for (lane = 0; lane < 4; lane++) 1134 intel_dp->train_set[lane] = v | p; 1135 } 1136 1137 1138 static uint8_t 1139 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], 1140 int lane) 1141 { 1142 int i = DP_LANE0_1_STATUS + (lane >> 1); 1143 int s = (lane & 1) * 4; 1144 uint8_t l = cdv_intel_dp_link_status(link_status, i); 1145 1146 return (l >> s) & 0xf; 1147 } 1148 1149 /* Check for clock recovery is done on all channels */ 1150 static bool 1151 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) 1152 { 1153 int lane; 1154 uint8_t lane_status; 1155 1156 for (lane = 0; lane < lane_count; lane++) { 1157 lane_status = cdv_intel_get_lane_status(link_status, lane); 1158 if ((lane_status & DP_LANE_CR_DONE) == 0) 1159 return false; 1160 } 1161 return true; 1162 } 1163 1164 /* Check to see if channel eq is done on all channels */ 1165 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ 1166 DP_LANE_CHANNEL_EQ_DONE|\ 1167 DP_LANE_SYMBOL_LOCKED) 1168 static bool 1169 cdv_intel_channel_eq_ok(struct gma_encoder *encoder) 1170 { 1171 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1172 uint8_t lane_align; 1173 uint8_t lane_status; 1174 int lane; 1175 1176 lane_align = cdv_intel_dp_link_status(intel_dp->link_status, 1177 DP_LANE_ALIGN_STATUS_UPDATED); 1178 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 1179 return false; 1180 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1181 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane); 1182 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) 1183 return false; 1184 } 1185 return true; 1186 } 1187 1188 static bool 1189 cdv_intel_dp_set_link_train(struct gma_encoder *encoder, 1190 uint32_t dp_reg_value, 1191 uint8_t dp_train_pat) 1192 { 1193 1194 struct drm_device *dev = encoder->base.dev; 1195 int ret; 1196 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1197 1198 REG_WRITE(intel_dp->output_reg, dp_reg_value); 1199 REG_READ(intel_dp->output_reg); 1200 1201 ret = cdv_intel_dp_aux_native_write_1(encoder, 1202 DP_TRAINING_PATTERN_SET, 1203 dp_train_pat); 1204 1205 if (ret != 1) { 1206 DRM_DEBUG_KMS("Failure in setting link pattern %x\n", 1207 dp_train_pat); 1208 return false; 1209 } 1210 1211 return true; 1212 } 1213 1214 1215 static bool 1216 cdv_intel_dplink_set_level(struct gma_encoder *encoder, 1217 uint8_t dp_train_pat) 1218 { 1219 1220 int ret; 1221 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1222 1223 ret = cdv_intel_dp_aux_native_write(encoder, 1224 DP_TRAINING_LANE0_SET, 1225 intel_dp->train_set, 1226 intel_dp->lane_count); 1227 1228 if (ret != intel_dp->lane_count) { 1229 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n", 1230 intel_dp->train_set[0], intel_dp->lane_count); 1231 return false; 1232 } 1233 return true; 1234 } 1235 1236 static void 1237 cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level) 1238 { 1239 struct drm_device *dev = encoder->base.dev; 1240 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1241 struct ddi_regoff *ddi_reg; 1242 int vswing, premph, index; 1243 1244 if (intel_dp->output_reg == DP_B) 1245 ddi_reg = &ddi_DP_train_table[0]; 1246 else 1247 ddi_reg = &ddi_DP_train_table[1]; 1248 1249 vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK); 1250 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >> 1251 DP_TRAIN_PRE_EMPHASIS_SHIFT; 1252 1253 if (vswing + premph > 3) 1254 return; 1255 #ifdef CDV_FAST_LINK_TRAIN 1256 return; 1257 #endif 1258 DRM_DEBUG_KMS("Test2\n"); 1259 //return ; 1260 cdv_sb_reset(dev); 1261 /* ;Swing voltage programming 1262 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */ 1263 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A); 1264 1265 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */ 1266 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055); 1267 1268 /* ;gfx_dpio_set_reg(0x8148, 0x55338954) 1269 * The VSwing_PreEmph table is also considered based on the vswing/premp 1270 */ 1271 index = (vswing + premph) * 2; 1272 if (premph == 1 && vswing == 1) { 1273 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954); 1274 } else 1275 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]); 1276 1277 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */ 1278 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200) 1279 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040); 1280 else 1281 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040); 1282 1283 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */ 1284 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */ 1285 1286 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */ 1287 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055); 1288 1289 /* ;Pre emphasis programming 1290 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040) 1291 */ 1292 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040); 1293 1294 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */ 1295 index = 2 * premph + 1; 1296 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]); 1297 return; 1298 } 1299 1300 1301 /* Enable corresponding port and start training pattern 1 */ 1302 static void 1303 cdv_intel_dp_start_link_train(struct gma_encoder *encoder) 1304 { 1305 struct drm_device *dev = encoder->base.dev; 1306 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1307 int i; 1308 uint8_t voltage; 1309 bool clock_recovery = false; 1310 int tries; 1311 u32 reg; 1312 uint32_t DP = intel_dp->DP; 1313 1314 DP |= DP_PORT_EN; 1315 DP &= ~DP_LINK_TRAIN_MASK; 1316 1317 reg = DP; 1318 reg |= DP_LINK_TRAIN_PAT_1; 1319 /* Enable output, wait for it to become active */ 1320 REG_WRITE(intel_dp->output_reg, reg); 1321 REG_READ(intel_dp->output_reg); 1322 gma_wait_for_vblank(dev); 1323 1324 DRM_DEBUG_KMS("Link config\n"); 1325 /* Write the link configuration data */ 1326 cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET, 1327 intel_dp->link_configuration, 1328 2); 1329 1330 memset(intel_dp->train_set, 0, 4); 1331 voltage = 0; 1332 tries = 0; 1333 clock_recovery = false; 1334 1335 DRM_DEBUG_KMS("Start train\n"); 1336 reg = DP | DP_LINK_TRAIN_PAT_1; 1337 1338 1339 for (;;) { 1340 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1341 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n", 1342 intel_dp->train_set[0], 1343 intel_dp->link_configuration[0], 1344 intel_dp->link_configuration[1]); 1345 1346 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) { 1347 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n"); 1348 } 1349 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); 1350 /* Set training pattern 1 */ 1351 1352 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1); 1353 1354 udelay(200); 1355 if (!cdv_intel_dp_get_link_status(encoder)) 1356 break; 1357 1358 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n", 1359 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2], 1360 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]); 1361 1362 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1363 DRM_DEBUG_KMS("PT1 train is done\n"); 1364 clock_recovery = true; 1365 break; 1366 } 1367 1368 /* Check to see if we've tried the max voltage */ 1369 for (i = 0; i < intel_dp->lane_count; i++) 1370 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1371 break; 1372 if (i == intel_dp->lane_count) 1373 break; 1374 1375 /* Check to see if we've tried the same voltage 5 times */ 1376 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 1377 ++tries; 1378 if (tries == 5) 1379 break; 1380 } else 1381 tries = 0; 1382 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1383 1384 /* Compute new intel_dp->train_set as requested by target */ 1385 cdv_intel_get_adjust_train(encoder); 1386 1387 } 1388 1389 if (!clock_recovery) { 1390 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]); 1391 } 1392 1393 intel_dp->DP = DP; 1394 } 1395 1396 static void 1397 cdv_intel_dp_complete_link_train(struct gma_encoder *encoder) 1398 { 1399 struct drm_device *dev = encoder->base.dev; 1400 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1401 bool channel_eq = false; 1402 int tries, cr_tries; 1403 u32 reg; 1404 uint32_t DP = intel_dp->DP; 1405 1406 /* channel equalization */ 1407 tries = 0; 1408 cr_tries = 0; 1409 channel_eq = false; 1410 1411 DRM_DEBUG_KMS("\n"); 1412 reg = DP | DP_LINK_TRAIN_PAT_2; 1413 1414 for (;;) { 1415 1416 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n", 1417 intel_dp->train_set[0], 1418 intel_dp->link_configuration[0], 1419 intel_dp->link_configuration[1]); 1420 /* channel eq pattern */ 1421 1422 if (!cdv_intel_dp_set_link_train(encoder, reg, 1423 DP_TRAINING_PATTERN_2)) { 1424 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n"); 1425 } 1426 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1427 1428 if (cr_tries > 5) { 1429 DRM_ERROR("failed to train DP, aborting\n"); 1430 cdv_intel_dp_link_down(encoder); 1431 break; 1432 } 1433 1434 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); 1435 1436 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2); 1437 1438 udelay(1000); 1439 if (!cdv_intel_dp_get_link_status(encoder)) 1440 break; 1441 1442 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n", 1443 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2], 1444 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]); 1445 1446 /* Make sure clock is still ok */ 1447 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { 1448 cdv_intel_dp_start_link_train(encoder); 1449 cr_tries++; 1450 continue; 1451 } 1452 1453 if (cdv_intel_channel_eq_ok(encoder)) { 1454 DRM_DEBUG_KMS("PT2 train is done\n"); 1455 channel_eq = true; 1456 break; 1457 } 1458 1459 /* Try 5 times, then try clock recovery if that fails */ 1460 if (tries > 5) { 1461 cdv_intel_dp_link_down(encoder); 1462 cdv_intel_dp_start_link_train(encoder); 1463 tries = 0; 1464 cr_tries++; 1465 continue; 1466 } 1467 1468 /* Compute new intel_dp->train_set as requested by target */ 1469 cdv_intel_get_adjust_train(encoder); 1470 ++tries; 1471 1472 } 1473 1474 reg = DP | DP_LINK_TRAIN_OFF; 1475 1476 REG_WRITE(intel_dp->output_reg, reg); 1477 REG_READ(intel_dp->output_reg); 1478 cdv_intel_dp_aux_native_write_1(encoder, 1479 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1480 } 1481 1482 static void 1483 cdv_intel_dp_link_down(struct gma_encoder *encoder) 1484 { 1485 struct drm_device *dev = encoder->base.dev; 1486 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1487 uint32_t DP = intel_dp->DP; 1488 1489 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) 1490 return; 1491 1492 DRM_DEBUG_KMS("\n"); 1493 1494 1495 { 1496 DP &= ~DP_LINK_TRAIN_MASK; 1497 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1498 } 1499 REG_READ(intel_dp->output_reg); 1500 1501 msleep(17); 1502 1503 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 1504 REG_READ(intel_dp->output_reg); 1505 } 1506 1507 static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder) 1508 { 1509 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1510 enum drm_connector_status status; 1511 1512 status = connector_status_disconnected; 1513 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, 1514 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) 1515 { 1516 if (intel_dp->dpcd[DP_DPCD_REV] != 0) 1517 status = connector_status_connected; 1518 } 1519 if (status == connector_status_connected) 1520 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n", 1521 intel_dp->dpcd[0], intel_dp->dpcd[1], 1522 intel_dp->dpcd[2], intel_dp->dpcd[3]); 1523 return status; 1524 } 1525 1526 /** 1527 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 1528 * 1529 * \return true if DP port is connected. 1530 * \return false if DP port is disconnected. 1531 */ 1532 static enum drm_connector_status 1533 cdv_intel_dp_detect(struct drm_connector *connector, bool force) 1534 { 1535 struct gma_encoder *encoder = gma_attached_encoder(connector); 1536 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1537 enum drm_connector_status status; 1538 struct edid *edid = NULL; 1539 int edp = is_edp(encoder); 1540 1541 intel_dp->has_audio = false; 1542 1543 if (edp) 1544 cdv_intel_edp_panel_vdd_on(encoder); 1545 status = cdv_dp_detect(encoder); 1546 if (status != connector_status_connected) { 1547 if (edp) 1548 cdv_intel_edp_panel_vdd_off(encoder); 1549 return status; 1550 } 1551 1552 if (intel_dp->force_audio) { 1553 intel_dp->has_audio = intel_dp->force_audio > 0; 1554 } else { 1555 edid = drm_get_edid(connector, &intel_dp->adapter); 1556 if (edid) { 1557 intel_dp->has_audio = drm_detect_monitor_audio(edid); 1558 kfree(edid); 1559 } 1560 } 1561 if (edp) 1562 cdv_intel_edp_panel_vdd_off(encoder); 1563 1564 return connector_status_connected; 1565 } 1566 1567 static int cdv_intel_dp_get_modes(struct drm_connector *connector) 1568 { 1569 struct gma_encoder *intel_encoder = gma_attached_encoder(connector); 1570 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv; 1571 struct edid *edid = NULL; 1572 int ret = 0; 1573 int edp = is_edp(intel_encoder); 1574 1575 1576 edid = drm_get_edid(connector, &intel_dp->adapter); 1577 if (edid) { 1578 drm_mode_connector_update_edid_property(connector, edid); 1579 ret = drm_add_edid_modes(connector, edid); 1580 kfree(edid); 1581 } 1582 1583 if (is_edp(intel_encoder)) { 1584 struct drm_device *dev = connector->dev; 1585 struct drm_psb_private *dev_priv = dev->dev_private; 1586 1587 cdv_intel_edp_panel_vdd_off(intel_encoder); 1588 if (ret) { 1589 if (edp && !intel_dp->panel_fixed_mode) { 1590 struct drm_display_mode *newmode; 1591 list_for_each_entry(newmode, &connector->probed_modes, 1592 head) { 1593 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1594 intel_dp->panel_fixed_mode = 1595 drm_mode_duplicate(dev, newmode); 1596 break; 1597 } 1598 } 1599 } 1600 1601 return ret; 1602 } 1603 if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) { 1604 intel_dp->panel_fixed_mode = 1605 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1606 if (intel_dp->panel_fixed_mode) { 1607 intel_dp->panel_fixed_mode->type |= 1608 DRM_MODE_TYPE_PREFERRED; 1609 } 1610 } 1611 if (intel_dp->panel_fixed_mode != NULL) { 1612 struct drm_display_mode *mode; 1613 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); 1614 drm_mode_probed_add(connector, mode); 1615 return 1; 1616 } 1617 } 1618 1619 return ret; 1620 } 1621 1622 static bool 1623 cdv_intel_dp_detect_audio(struct drm_connector *connector) 1624 { 1625 struct gma_encoder *encoder = gma_attached_encoder(connector); 1626 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1627 struct edid *edid; 1628 bool has_audio = false; 1629 int edp = is_edp(encoder); 1630 1631 if (edp) 1632 cdv_intel_edp_panel_vdd_on(encoder); 1633 1634 edid = drm_get_edid(connector, &intel_dp->adapter); 1635 if (edid) { 1636 has_audio = drm_detect_monitor_audio(edid); 1637 kfree(edid); 1638 } 1639 if (edp) 1640 cdv_intel_edp_panel_vdd_off(encoder); 1641 1642 return has_audio; 1643 } 1644 1645 static int 1646 cdv_intel_dp_set_property(struct drm_connector *connector, 1647 struct drm_property *property, 1648 uint64_t val) 1649 { 1650 struct drm_psb_private *dev_priv = connector->dev->dev_private; 1651 struct gma_encoder *encoder = gma_attached_encoder(connector); 1652 struct cdv_intel_dp *intel_dp = encoder->dev_priv; 1653 int ret; 1654 1655 ret = drm_object_property_set_value(&connector->base, property, val); 1656 if (ret) 1657 return ret; 1658 1659 if (property == dev_priv->force_audio_property) { 1660 int i = val; 1661 bool has_audio; 1662 1663 if (i == intel_dp->force_audio) 1664 return 0; 1665 1666 intel_dp->force_audio = i; 1667 1668 if (i == 0) 1669 has_audio = cdv_intel_dp_detect_audio(connector); 1670 else 1671 has_audio = i > 0; 1672 1673 if (has_audio == intel_dp->has_audio) 1674 return 0; 1675 1676 intel_dp->has_audio = has_audio; 1677 goto done; 1678 } 1679 1680 if (property == dev_priv->broadcast_rgb_property) { 1681 if (val == !!intel_dp->color_range) 1682 return 0; 1683 1684 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 1685 goto done; 1686 } 1687 1688 return -EINVAL; 1689 1690 done: 1691 if (encoder->base.crtc) { 1692 struct drm_crtc *crtc = encoder->base.crtc; 1693 drm_crtc_helper_set_mode(crtc, &crtc->mode, 1694 crtc->x, crtc->y, 1695 crtc->fb); 1696 } 1697 1698 return 0; 1699 } 1700 1701 static void 1702 cdv_intel_dp_destroy(struct drm_connector *connector) 1703 { 1704 struct gma_encoder *gma_encoder = gma_attached_encoder(connector); 1705 struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv; 1706 1707 if (is_edp(gma_encoder)) { 1708 /* cdv_intel_panel_destroy_backlight(connector->dev); */ 1709 if (intel_dp->panel_fixed_mode) { 1710 kfree(intel_dp->panel_fixed_mode); 1711 intel_dp->panel_fixed_mode = NULL; 1712 } 1713 } 1714 i2c_del_adapter(&intel_dp->adapter); 1715 drm_sysfs_connector_remove(connector); 1716 drm_connector_cleanup(connector); 1717 kfree(connector); 1718 } 1719 1720 static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder) 1721 { 1722 drm_encoder_cleanup(encoder); 1723 } 1724 1725 static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = { 1726 .dpms = cdv_intel_dp_dpms, 1727 .mode_fixup = cdv_intel_dp_mode_fixup, 1728 .prepare = cdv_intel_dp_prepare, 1729 .mode_set = cdv_intel_dp_mode_set, 1730 .commit = cdv_intel_dp_commit, 1731 }; 1732 1733 static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = { 1734 .dpms = drm_helper_connector_dpms, 1735 .detect = cdv_intel_dp_detect, 1736 .fill_modes = drm_helper_probe_single_connector_modes, 1737 .set_property = cdv_intel_dp_set_property, 1738 .destroy = cdv_intel_dp_destroy, 1739 }; 1740 1741 static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = { 1742 .get_modes = cdv_intel_dp_get_modes, 1743 .mode_valid = cdv_intel_dp_mode_valid, 1744 .best_encoder = gma_best_encoder, 1745 }; 1746 1747 static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = { 1748 .destroy = cdv_intel_dp_encoder_destroy, 1749 }; 1750 1751 1752 static void cdv_intel_dp_add_properties(struct drm_connector *connector) 1753 { 1754 cdv_intel_attach_force_audio_property(connector); 1755 cdv_intel_attach_broadcast_rgb_property(connector); 1756 } 1757 1758 /* check the VBT to see whether the eDP is on DP-D port */ 1759 static bool cdv_intel_dpc_is_edp(struct drm_device *dev) 1760 { 1761 struct drm_psb_private *dev_priv = dev->dev_private; 1762 struct child_device_config *p_child; 1763 int i; 1764 1765 if (!dev_priv->child_dev_num) 1766 return false; 1767 1768 for (i = 0; i < dev_priv->child_dev_num; i++) { 1769 p_child = dev_priv->child_dev + i; 1770 1771 if (p_child->dvo_port == PORT_IDPC && 1772 p_child->device_type == DEVICE_TYPE_eDP) 1773 return true; 1774 } 1775 return false; 1776 } 1777 1778 /* Cedarview display clock gating 1779 1780 We need this disable dot get correct behaviour while enabling 1781 DP/eDP. TODO - investigate if we can turn it back to normality 1782 after enabling */ 1783 static void cdv_disable_intel_clock_gating(struct drm_device *dev) 1784 { 1785 u32 reg_value; 1786 reg_value = REG_READ(DSPCLK_GATE_D); 1787 1788 reg_value |= (DPUNIT_PIPEB_GATE_DISABLE | 1789 DPUNIT_PIPEA_GATE_DISABLE | 1790 DPCUNIT_CLOCK_GATE_DISABLE | 1791 DPLSUNIT_CLOCK_GATE_DISABLE | 1792 DPOUNIT_CLOCK_GATE_DISABLE | 1793 DPIOUNIT_CLOCK_GATE_DISABLE); 1794 1795 REG_WRITE(DSPCLK_GATE_D, reg_value); 1796 1797 udelay(500); 1798 } 1799 1800 void 1801 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg) 1802 { 1803 struct gma_encoder *gma_encoder; 1804 struct gma_connector *gma_connector; 1805 struct drm_connector *connector; 1806 struct drm_encoder *encoder; 1807 struct cdv_intel_dp *intel_dp; 1808 const char *name = NULL; 1809 int type = DRM_MODE_CONNECTOR_DisplayPort; 1810 1811 gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL); 1812 if (!gma_encoder) 1813 return; 1814 gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL); 1815 if (!gma_connector) 1816 goto err_connector; 1817 intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL); 1818 if (!intel_dp) 1819 goto err_priv; 1820 1821 if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev)) 1822 type = DRM_MODE_CONNECTOR_eDP; 1823 1824 connector = &gma_connector->base; 1825 encoder = &gma_encoder->base; 1826 1827 drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type); 1828 drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS); 1829 1830 gma_connector_attach_encoder(gma_connector, gma_encoder); 1831 1832 if (type == DRM_MODE_CONNECTOR_DisplayPort) 1833 gma_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 1834 else 1835 gma_encoder->type = INTEL_OUTPUT_EDP; 1836 1837 1838 gma_encoder->dev_priv=intel_dp; 1839 intel_dp->encoder = gma_encoder; 1840 intel_dp->output_reg = output_reg; 1841 1842 drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs); 1843 drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs); 1844 1845 connector->polled = DRM_CONNECTOR_POLL_HPD; 1846 connector->interlace_allowed = false; 1847 connector->doublescan_allowed = false; 1848 1849 drm_sysfs_connector_add(connector); 1850 1851 /* Set up the DDC bus. */ 1852 switch (output_reg) { 1853 case DP_B: 1854 name = "DPDDC-B"; 1855 gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT); 1856 break; 1857 case DP_C: 1858 name = "DPDDC-C"; 1859 gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT); 1860 break; 1861 } 1862 1863 cdv_disable_intel_clock_gating(dev); 1864 1865 cdv_intel_dp_i2c_init(gma_connector, gma_encoder, name); 1866 /* FIXME:fail check */ 1867 cdv_intel_dp_add_properties(connector); 1868 1869 if (is_edp(gma_encoder)) { 1870 int ret; 1871 struct edp_power_seq cur; 1872 u32 pp_on, pp_off, pp_div; 1873 u32 pwm_ctrl; 1874 1875 pp_on = REG_READ(PP_CONTROL); 1876 pp_on &= ~PANEL_UNLOCK_MASK; 1877 pp_on |= PANEL_UNLOCK_REGS; 1878 1879 REG_WRITE(PP_CONTROL, pp_on); 1880 1881 pwm_ctrl = REG_READ(BLC_PWM_CTL2); 1882 pwm_ctrl |= PWM_PIPE_B; 1883 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl); 1884 1885 pp_on = REG_READ(PP_ON_DELAYS); 1886 pp_off = REG_READ(PP_OFF_DELAYS); 1887 pp_div = REG_READ(PP_DIVISOR); 1888 1889 /* Pull timing values out of registers */ 1890 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 1891 PANEL_POWER_UP_DELAY_SHIFT; 1892 1893 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 1894 PANEL_LIGHT_ON_DELAY_SHIFT; 1895 1896 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 1897 PANEL_LIGHT_OFF_DELAY_SHIFT; 1898 1899 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 1900 PANEL_POWER_DOWN_DELAY_SHIFT; 1901 1902 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 1903 PANEL_POWER_CYCLE_DELAY_SHIFT); 1904 1905 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 1906 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 1907 1908 1909 intel_dp->panel_power_up_delay = cur.t1_t3 / 10; 1910 intel_dp->backlight_on_delay = cur.t8 / 10; 1911 intel_dp->backlight_off_delay = cur.t9 / 10; 1912 intel_dp->panel_power_down_delay = cur.t10 / 10; 1913 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100; 1914 1915 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 1916 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 1917 intel_dp->panel_power_cycle_delay); 1918 1919 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 1920 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 1921 1922 1923 cdv_intel_edp_panel_vdd_on(gma_encoder); 1924 ret = cdv_intel_dp_aux_native_read(gma_encoder, DP_DPCD_REV, 1925 intel_dp->dpcd, 1926 sizeof(intel_dp->dpcd)); 1927 cdv_intel_edp_panel_vdd_off(gma_encoder); 1928 if (ret == 0) { 1929 /* if this fails, presume the device is a ghost */ 1930 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 1931 cdv_intel_dp_encoder_destroy(encoder); 1932 cdv_intel_dp_destroy(connector); 1933 goto err_priv; 1934 } else { 1935 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n", 1936 intel_dp->dpcd[0], intel_dp->dpcd[1], 1937 intel_dp->dpcd[2], intel_dp->dpcd[3]); 1938 1939 } 1940 /* The CDV reference driver moves pnale backlight setup into the displays that 1941 have a backlight: this is a good idea and one we should probably adopt, however 1942 we need to migrate all the drivers before we can do that */ 1943 /*cdv_intel_panel_setup_backlight(dev); */ 1944 } 1945 return; 1946 1947 err_priv: 1948 kfree(gma_connector); 1949 err_connector: 1950 kfree(gma_encoder); 1951 } 1952