1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21 #include <linux/i2c.h> 22 23 #include <drm/drmP.h> 24 #include "framebuffer.h" 25 #include "psb_drv.h" 26 #include "psb_intel_drv.h" 27 #include "psb_intel_reg.h" 28 #include "gma_display.h" 29 #include "power.h" 30 #include "cdv_device.h" 31 32 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, 33 struct drm_crtc *crtc, int target, 34 int refclk, struct gma_clock_t *best_clock); 35 36 37 #define CDV_LIMIT_SINGLE_LVDS_96 0 38 #define CDV_LIMIT_SINGLE_LVDS_100 1 39 #define CDV_LIMIT_DAC_HDMI_27 2 40 #define CDV_LIMIT_DAC_HDMI_96 3 41 #define CDV_LIMIT_DP_27 4 42 #define CDV_LIMIT_DP_100 5 43 44 static const struct gma_limit_t cdv_intel_limits[] = { 45 { /* CDV_SINGLE_LVDS_96MHz */ 46 .dot = {.min = 20000, .max = 115500}, 47 .vco = {.min = 1800000, .max = 3600000}, 48 .n = {.min = 2, .max = 6}, 49 .m = {.min = 60, .max = 160}, 50 .m1 = {.min = 0, .max = 0}, 51 .m2 = {.min = 58, .max = 158}, 52 .p = {.min = 28, .max = 140}, 53 .p1 = {.min = 2, .max = 10}, 54 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, 55 .find_pll = gma_find_best_pll, 56 }, 57 { /* CDV_SINGLE_LVDS_100MHz */ 58 .dot = {.min = 20000, .max = 115500}, 59 .vco = {.min = 1800000, .max = 3600000}, 60 .n = {.min = 2, .max = 6}, 61 .m = {.min = 60, .max = 160}, 62 .m1 = {.min = 0, .max = 0}, 63 .m2 = {.min = 58, .max = 158}, 64 .p = {.min = 28, .max = 140}, 65 .p1 = {.min = 2, .max = 10}, 66 /* The single-channel range is 25-112Mhz, and dual-channel 67 * is 80-224Mhz. Prefer single channel as much as possible. 68 */ 69 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, 70 .find_pll = gma_find_best_pll, 71 }, 72 { /* CDV_DAC_HDMI_27MHz */ 73 .dot = {.min = 20000, .max = 400000}, 74 .vco = {.min = 1809000, .max = 3564000}, 75 .n = {.min = 1, .max = 1}, 76 .m = {.min = 67, .max = 132}, 77 .m1 = {.min = 0, .max = 0}, 78 .m2 = {.min = 65, .max = 130}, 79 .p = {.min = 5, .max = 90}, 80 .p1 = {.min = 1, .max = 9}, 81 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, 82 .find_pll = gma_find_best_pll, 83 }, 84 { /* CDV_DAC_HDMI_96MHz */ 85 .dot = {.min = 20000, .max = 400000}, 86 .vco = {.min = 1800000, .max = 3600000}, 87 .n = {.min = 2, .max = 6}, 88 .m = {.min = 60, .max = 160}, 89 .m1 = {.min = 0, .max = 0}, 90 .m2 = {.min = 58, .max = 158}, 91 .p = {.min = 5, .max = 100}, 92 .p1 = {.min = 1, .max = 10}, 93 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, 94 .find_pll = gma_find_best_pll, 95 }, 96 { /* CDV_DP_27MHz */ 97 .dot = {.min = 160000, .max = 272000}, 98 .vco = {.min = 1809000, .max = 3564000}, 99 .n = {.min = 1, .max = 1}, 100 .m = {.min = 67, .max = 132}, 101 .m1 = {.min = 0, .max = 0}, 102 .m2 = {.min = 65, .max = 130}, 103 .p = {.min = 5, .max = 90}, 104 .p1 = {.min = 1, .max = 9}, 105 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, 106 .find_pll = cdv_intel_find_dp_pll, 107 }, 108 { /* CDV_DP_100MHz */ 109 .dot = {.min = 160000, .max = 272000}, 110 .vco = {.min = 1800000, .max = 3600000}, 111 .n = {.min = 2, .max = 6}, 112 .m = {.min = 60, .max = 164}, 113 .m1 = {.min = 0, .max = 0}, 114 .m2 = {.min = 58, .max = 162}, 115 .p = {.min = 5, .max = 100}, 116 .p1 = {.min = 1, .max = 10}, 117 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, 118 .find_pll = cdv_intel_find_dp_pll, 119 } 120 }; 121 122 #define _wait_for(COND, MS, W) ({ \ 123 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 124 int ret__ = 0; \ 125 while (!(COND)) { \ 126 if (time_after(jiffies, timeout__)) { \ 127 ret__ = -ETIMEDOUT; \ 128 break; \ 129 } \ 130 if (W && !in_dbg_master()) \ 131 msleep(W); \ 132 } \ 133 ret__; \ 134 }) 135 136 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 137 138 139 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) 140 { 141 int ret; 142 143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 144 if (ret) { 145 DRM_ERROR("timeout waiting for SB to idle before read\n"); 146 return ret; 147 } 148 149 REG_WRITE(SB_ADDR, reg); 150 REG_WRITE(SB_PCKT, 151 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | 152 SET_FIELD(SB_DEST_DPLL, SB_DEST) | 153 SET_FIELD(0xf, SB_BYTE_ENABLE)); 154 155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 156 if (ret) { 157 DRM_ERROR("timeout waiting for SB to idle after read\n"); 158 return ret; 159 } 160 161 *val = REG_READ(SB_DATA); 162 163 return 0; 164 } 165 166 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) 167 { 168 int ret; 169 static bool dpio_debug = true; 170 u32 temp; 171 172 if (dpio_debug) { 173 if (cdv_sb_read(dev, reg, &temp) == 0) 174 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); 175 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); 176 } 177 178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 179 if (ret) { 180 DRM_ERROR("timeout waiting for SB to idle before write\n"); 181 return ret; 182 } 183 184 REG_WRITE(SB_ADDR, reg); 185 REG_WRITE(SB_DATA, val); 186 REG_WRITE(SB_PCKT, 187 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | 188 SET_FIELD(SB_DEST_DPLL, SB_DEST) | 189 SET_FIELD(0xf, SB_BYTE_ENABLE)); 190 191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 192 if (ret) { 193 DRM_ERROR("timeout waiting for SB to idle after write\n"); 194 return ret; 195 } 196 197 if (dpio_debug) { 198 if (cdv_sb_read(dev, reg, &temp) == 0) 199 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); 200 } 201 202 return 0; 203 } 204 205 /* Reset the DPIO configuration register. The BIOS does this at every 206 * mode set. 207 */ 208 void cdv_sb_reset(struct drm_device *dev) 209 { 210 211 REG_WRITE(DPIO_CFG, 0); 212 REG_READ(DPIO_CFG); 213 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 214 } 215 216 /* Unlike most Intel display engines, on Cedarview the DPLL registers 217 * are behind this sideband bus. They must be programmed while the 218 * DPLL reference clock is on in the DPLL control register, but before 219 * the DPLL is enabled in the DPLL control register. 220 */ 221 static int 222 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, 223 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) 224 { 225 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 226 int pipe = gma_crtc->pipe; 227 u32 m, n_vco, p; 228 int ret = 0; 229 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 230 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB; 231 u32 ref_value; 232 u32 lane_reg, lane_value; 233 234 cdv_sb_reset(dev); 235 236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); 237 238 udelay(100); 239 240 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ 241 ref_value = 0x68A701; 242 243 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value); 244 245 /* We don't know what the other fields of these regs are, so 246 * leave them in place. 247 */ 248 /* 249 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk 250 * for the pipe A/B. Display spec 1.06 has wrong definition. 251 * Correct definition is like below: 252 * 253 * refclka mean use clock from same PLL 254 * 255 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll 256 * 257 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA 258 * 259 */ 260 ret = cdv_sb_read(dev, ref_sfr, &ref_value); 261 if (ret) 262 return ret; 263 ref_value &= ~(REF_CLK_MASK); 264 265 /* use DPLL_A for pipeB on CRT/HDMI */ 266 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) { 267 DRM_DEBUG_KMS("use DPLLA for pipe B\n"); 268 ref_value |= REF_CLK_DPLLA; 269 } else { 270 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); 271 ref_value |= REF_CLK_DPLL; 272 } 273 ret = cdv_sb_write(dev, ref_sfr, ref_value); 274 if (ret) 275 return ret; 276 277 ret = cdv_sb_read(dev, SB_M(pipe), &m); 278 if (ret) 279 return ret; 280 m &= ~SB_M_DIVIDER_MASK; 281 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); 282 ret = cdv_sb_write(dev, SB_M(pipe), m); 283 if (ret) 284 return ret; 285 286 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco); 287 if (ret) 288 return ret; 289 290 /* Follow the BIOS to program the N_DIVIDER REG */ 291 n_vco &= 0xFFFF; 292 n_vco |= 0x107; 293 n_vco &= ~(SB_N_VCO_SEL_MASK | 294 SB_N_DIVIDER_MASK | 295 SB_N_CB_TUNE_MASK); 296 297 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); 298 299 if (clock->vco < 2250000) { 300 n_vco |= (2 << SB_N_CB_TUNE_SHIFT); 301 n_vco |= (0 << SB_N_VCO_SEL_SHIFT); 302 } else if (clock->vco < 2750000) { 303 n_vco |= (1 << SB_N_CB_TUNE_SHIFT); 304 n_vco |= (1 << SB_N_VCO_SEL_SHIFT); 305 } else if (clock->vco < 3300000) { 306 n_vco |= (0 << SB_N_CB_TUNE_SHIFT); 307 n_vco |= (2 << SB_N_VCO_SEL_SHIFT); 308 } else { 309 n_vco |= (0 << SB_N_CB_TUNE_SHIFT); 310 n_vco |= (3 << SB_N_VCO_SEL_SHIFT); 311 } 312 313 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco); 314 if (ret) 315 return ret; 316 317 ret = cdv_sb_read(dev, SB_P(pipe), &p); 318 if (ret) 319 return ret; 320 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK); 321 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); 322 switch (clock->p2) { 323 case 5: 324 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); 325 break; 326 case 10: 327 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); 328 break; 329 case 14: 330 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); 331 break; 332 case 7: 333 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); 334 break; 335 default: 336 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); 337 return -EINVAL; 338 } 339 ret = cdv_sb_write(dev, SB_P(pipe), p); 340 if (ret) 341 return ret; 342 343 if (ddi_select) { 344 if ((ddi_select & DDI_MASK) == DDI0_SELECT) { 345 lane_reg = PSB_LANE0; 346 cdv_sb_read(dev, lane_reg, &lane_value); 347 lane_value &= ~(LANE_PLL_MASK); 348 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 349 cdv_sb_write(dev, lane_reg, lane_value); 350 351 lane_reg = PSB_LANE1; 352 cdv_sb_read(dev, lane_reg, &lane_value); 353 lane_value &= ~(LANE_PLL_MASK); 354 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 355 cdv_sb_write(dev, lane_reg, lane_value); 356 } else { 357 lane_reg = PSB_LANE2; 358 cdv_sb_read(dev, lane_reg, &lane_value); 359 lane_value &= ~(LANE_PLL_MASK); 360 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 361 cdv_sb_write(dev, lane_reg, lane_value); 362 363 lane_reg = PSB_LANE3; 364 cdv_sb_read(dev, lane_reg, &lane_value); 365 lane_value &= ~(LANE_PLL_MASK); 366 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 367 cdv_sb_write(dev, lane_reg, lane_value); 368 } 369 } 370 return 0; 371 } 372 373 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc, 374 int refclk) 375 { 376 const struct gma_limit_t *limit; 377 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 378 /* 379 * Now only single-channel LVDS is supported on CDV. If it is 380 * incorrect, please add the dual-channel LVDS. 381 */ 382 if (refclk == 96000) 383 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; 384 else 385 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; 386 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 387 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 388 if (refclk == 27000) 389 limit = &cdv_intel_limits[CDV_LIMIT_DP_27]; 390 else 391 limit = &cdv_intel_limits[CDV_LIMIT_DP_100]; 392 } else { 393 if (refclk == 27000) 394 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27]; 395 else 396 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96]; 397 } 398 return limit; 399 } 400 401 /* m1 is reserved as 0 in CDV, n is a ring counter */ 402 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) 403 { 404 clock->m = clock->m2 + 2; 405 clock->p = clock->p1 * clock->p2; 406 clock->vco = (refclk * clock->m) / clock->n; 407 clock->dot = clock->vco / clock->p; 408 } 409 410 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, 411 struct drm_crtc *crtc, int target, 412 int refclk, 413 struct gma_clock_t *best_clock) 414 { 415 struct gma_clock_t clock; 416 if (refclk == 27000) { 417 if (target < 200000) { 418 clock.p1 = 2; 419 clock.p2 = 10; 420 clock.n = 1; 421 clock.m1 = 0; 422 clock.m2 = 118; 423 } else { 424 clock.p1 = 1; 425 clock.p2 = 10; 426 clock.n = 1; 427 clock.m1 = 0; 428 clock.m2 = 98; 429 } 430 } else if (refclk == 100000) { 431 if (target < 200000) { 432 clock.p1 = 2; 433 clock.p2 = 10; 434 clock.n = 5; 435 clock.m1 = 0; 436 clock.m2 = 160; 437 } else { 438 clock.p1 = 1; 439 clock.p2 = 10; 440 clock.n = 5; 441 clock.m1 = 0; 442 clock.m2 = 133; 443 } 444 } else 445 return false; 446 clock.m = clock.m2 + 2; 447 clock.p = clock.p1 * clock.p2; 448 clock.vco = (refclk * clock.m) / clock.n; 449 clock.dot = clock.vco / clock.p; 450 memcpy(best_clock, &clock, sizeof(struct gma_clock_t)); 451 return true; 452 } 453 454 #define FIFO_PIPEA (1 << 0) 455 #define FIFO_PIPEB (1 << 1) 456 457 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe) 458 { 459 struct drm_crtc *crtc; 460 struct drm_psb_private *dev_priv = dev->dev_private; 461 struct gma_crtc *gma_crtc = NULL; 462 463 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 464 gma_crtc = to_gma_crtc(crtc); 465 466 if (crtc->fb == NULL || !gma_crtc->active) 467 return false; 468 return true; 469 } 470 471 static bool cdv_intel_single_pipe_active (struct drm_device *dev) 472 { 473 uint32_t pipe_enabled = 0; 474 475 if (cdv_intel_pipe_enabled(dev, 0)) 476 pipe_enabled |= FIFO_PIPEA; 477 478 if (cdv_intel_pipe_enabled(dev, 1)) 479 pipe_enabled |= FIFO_PIPEB; 480 481 482 DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled); 483 484 if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB) 485 return true; 486 else 487 return false; 488 } 489 490 static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc) 491 { 492 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 493 struct drm_mode_config *mode_config = &dev->mode_config; 494 struct drm_connector *connector; 495 496 if (gma_crtc->pipe != 1) 497 return false; 498 499 list_for_each_entry(connector, &mode_config->connector_list, head) { 500 struct gma_encoder *gma_encoder = 501 gma_attached_encoder(connector); 502 503 if (!connector->encoder 504 || connector->encoder->crtc != crtc) 505 continue; 506 507 if (gma_encoder->type == INTEL_OUTPUT_LVDS) 508 return true; 509 } 510 511 return false; 512 } 513 514 void cdv_disable_sr(struct drm_device *dev) 515 { 516 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { 517 518 /* Disable self-refresh before adjust WM */ 519 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); 520 REG_READ(FW_BLC_SELF); 521 522 gma_wait_for_vblank(dev); 523 524 /* Cedarview workaround to write ovelay plane, which force to leave 525 * MAX_FIFO state. 526 */ 527 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); 528 REG_READ(OV_OVADD); 529 530 gma_wait_for_vblank(dev); 531 } 532 533 } 534 535 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc) 536 { 537 struct drm_psb_private *dev_priv = dev->dev_private; 538 539 if (cdv_intel_single_pipe_active(dev)) { 540 u32 fw; 541 542 fw = REG_READ(DSPFW1); 543 fw &= ~DSP_FIFO_SR_WM_MASK; 544 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT); 545 fw &= ~CURSOR_B_FIFO_WM_MASK; 546 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT); 547 REG_WRITE(DSPFW1, fw); 548 549 fw = REG_READ(DSPFW2); 550 fw &= ~CURSOR_A_FIFO_WM_MASK; 551 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT); 552 fw &= ~DSP_PLANE_C_FIFO_WM_MASK; 553 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT); 554 REG_WRITE(DSPFW2, fw); 555 556 REG_WRITE(DSPFW3, 0x36000000); 557 558 /* ignore FW4 */ 559 560 if (is_pipeb_lvds(dev, crtc)) { 561 REG_WRITE(DSPFW5, 0x00040330); 562 } else { 563 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) | 564 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) | 565 (3 << CURSOR_B_FIFO_WM1_SHIFT) | 566 (4 << CURSOR_FIFO_SR_WM1_SHIFT); 567 REG_WRITE(DSPFW5, fw); 568 } 569 570 REG_WRITE(DSPFW6, 0x10); 571 572 gma_wait_for_vblank(dev); 573 574 /* enable self-refresh for single pipe active */ 575 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 576 REG_READ(FW_BLC_SELF); 577 gma_wait_for_vblank(dev); 578 579 } else { 580 581 /* HW team suggested values... */ 582 REG_WRITE(DSPFW1, 0x3f880808); 583 REG_WRITE(DSPFW2, 0x0b020202); 584 REG_WRITE(DSPFW3, 0x24000000); 585 REG_WRITE(DSPFW4, 0x08030202); 586 REG_WRITE(DSPFW5, 0x01010101); 587 REG_WRITE(DSPFW6, 0x1d0); 588 589 gma_wait_for_vblank(dev); 590 591 dev_priv->ops->disable_sr(dev); 592 } 593 } 594 595 /** 596 * Return the pipe currently connected to the panel fitter, 597 * or -1 if the panel fitter is not present or not in use 598 */ 599 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev) 600 { 601 u32 pfit_control; 602 603 pfit_control = REG_READ(PFIT_CONTROL); 604 605 /* See if the panel fitter is in use */ 606 if ((pfit_control & PFIT_ENABLE) == 0) 607 return -1; 608 return (pfit_control >> 29) & 0x3; 609 } 610 611 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, 612 struct drm_display_mode *mode, 613 struct drm_display_mode *adjusted_mode, 614 int x, int y, 615 struct drm_framebuffer *old_fb) 616 { 617 struct drm_device *dev = crtc->dev; 618 struct drm_psb_private *dev_priv = dev->dev_private; 619 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 620 int pipe = gma_crtc->pipe; 621 const struct psb_offset *map = &dev_priv->regmap[pipe]; 622 int refclk; 623 struct gma_clock_t clock; 624 u32 dpll = 0, dspcntr, pipeconf; 625 bool ok; 626 bool is_crt = false, is_lvds = false, is_tv = false; 627 bool is_hdmi = false, is_dp = false; 628 struct drm_mode_config *mode_config = &dev->mode_config; 629 struct drm_connector *connector; 630 const struct gma_limit_t *limit; 631 u32 ddi_select = 0; 632 bool is_edp = false; 633 634 list_for_each_entry(connector, &mode_config->connector_list, head) { 635 struct gma_encoder *gma_encoder = 636 gma_attached_encoder(connector); 637 638 if (!connector->encoder 639 || connector->encoder->crtc != crtc) 640 continue; 641 642 ddi_select = gma_encoder->ddi_select; 643 switch (gma_encoder->type) { 644 case INTEL_OUTPUT_LVDS: 645 is_lvds = true; 646 break; 647 case INTEL_OUTPUT_TVOUT: 648 is_tv = true; 649 break; 650 case INTEL_OUTPUT_ANALOG: 651 is_crt = true; 652 break; 653 case INTEL_OUTPUT_HDMI: 654 is_hdmi = true; 655 break; 656 case INTEL_OUTPUT_DISPLAYPORT: 657 is_dp = true; 658 break; 659 case INTEL_OUTPUT_EDP: 660 is_edp = true; 661 break; 662 default: 663 DRM_ERROR("invalid output type.\n"); 664 return 0; 665 } 666 } 667 668 if (dev_priv->dplla_96mhz) 669 /* low-end sku, 96/100 mhz */ 670 refclk = 96000; 671 else 672 /* high-end sku, 27/100 mhz */ 673 refclk = 27000; 674 if (is_dp || is_edp) { 675 /* 676 * Based on the spec the low-end SKU has only CRT/LVDS. So it is 677 * unnecessary to consider it for DP/eDP. 678 * On the high-end SKU, it will use the 27/100M reference clk 679 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise 680 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose 681 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. 682 */ 683 if (pipe == 0) 684 refclk = 27000; 685 else 686 refclk = 100000; 687 } 688 689 if (is_lvds && dev_priv->lvds_use_ssc) { 690 refclk = dev_priv->lvds_ssc_freq * 1000; 691 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); 692 } 693 694 drm_mode_debug_printmodeline(adjusted_mode); 695 696 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 697 698 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 699 &clock); 700 if (!ok) { 701 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 702 adjusted_mode->clock, clock.dot); 703 return 0; 704 } 705 706 dpll = DPLL_VGA_MODE_DIS; 707 if (is_tv) { 708 /* XXX: just matching BIOS for now */ 709 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 710 dpll |= 3; 711 } 712 /* dpll |= PLL_REF_INPUT_DREFCLK; */ 713 714 if (is_dp || is_edp) { 715 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); 716 } else { 717 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); 718 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0); 719 REG_WRITE(PIPE_DP_LINK_M(pipe), 0); 720 REG_WRITE(PIPE_DP_LINK_N(pipe), 0); 721 } 722 723 dpll |= DPLL_SYNCLOCK_ENABLE; 724 /* if (is_lvds) 725 dpll |= DPLLB_MODE_LVDS; 726 else 727 dpll |= DPLLB_MODE_DAC_SERIAL; */ 728 /* dpll |= (2 << 11); */ 729 730 /* setup pipeconf */ 731 pipeconf = REG_READ(map->conf); 732 733 pipeconf &= ~(PIPE_BPC_MASK); 734 if (is_edp) { 735 switch (dev_priv->edp.bpp) { 736 case 24: 737 pipeconf |= PIPE_8BPC; 738 break; 739 case 18: 740 pipeconf |= PIPE_6BPC; 741 break; 742 case 30: 743 pipeconf |= PIPE_10BPC; 744 break; 745 default: 746 pipeconf |= PIPE_8BPC; 747 break; 748 } 749 } else if (is_lvds) { 750 /* the BPC will be 6 if it is 18-bit LVDS panel */ 751 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) 752 pipeconf |= PIPE_8BPC; 753 else 754 pipeconf |= PIPE_6BPC; 755 } else 756 pipeconf |= PIPE_8BPC; 757 758 /* Set up the display plane register */ 759 dspcntr = DISPPLANE_GAMMA_ENABLE; 760 761 if (pipe == 0) 762 dspcntr |= DISPPLANE_SEL_PIPE_A; 763 else 764 dspcntr |= DISPPLANE_SEL_PIPE_B; 765 766 dspcntr |= DISPLAY_PLANE_ENABLE; 767 pipeconf |= PIPEACONF_ENABLE; 768 769 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); 770 REG_READ(map->dpll); 771 772 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select); 773 774 udelay(150); 775 776 777 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 778 * This is an exception to the general rule that mode_set doesn't turn 779 * things on. 780 */ 781 if (is_lvds) { 782 u32 lvds = REG_READ(LVDS); 783 784 lvds |= 785 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | 786 LVDS_PIPEB_SELECT; 787 /* Set the B0-B3 data pairs corresponding to 788 * whether we're going to 789 * set the DPLLs for dual-channel mode or not. 790 */ 791 if (clock.p2 == 7) 792 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 793 else 794 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 795 796 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 797 * appropriately here, but we need to look more 798 * thoroughly into how panels behave in the two modes. 799 */ 800 801 REG_WRITE(LVDS, lvds); 802 REG_READ(LVDS); 803 } 804 805 dpll |= DPLL_VCO_ENABLE; 806 807 /* Disable the panel fitter if it was on our pipe */ 808 if (cdv_intel_panel_fitter_pipe(dev) == pipe) 809 REG_WRITE(PFIT_CONTROL, 0); 810 811 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 812 drm_mode_debug_printmodeline(mode); 813 814 REG_WRITE(map->dpll, 815 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); 816 REG_READ(map->dpll); 817 /* Wait for the clocks to stabilize. */ 818 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ 819 820 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { 821 dev_err(dev->dev, "Failed to get DPLL lock\n"); 822 return -EBUSY; 823 } 824 825 { 826 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 827 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); 828 } 829 830 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 831 ((adjusted_mode->crtc_htotal - 1) << 16)); 832 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 833 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 834 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 835 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 836 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 837 ((adjusted_mode->crtc_vtotal - 1) << 16)); 838 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 839 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 840 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 841 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 842 /* pipesrc and dspsize control the size that is scaled from, 843 * which should always be the user's requested size. 844 */ 845 REG_WRITE(map->size, 846 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 847 REG_WRITE(map->pos, 0); 848 REG_WRITE(map->src, 849 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 850 REG_WRITE(map->conf, pipeconf); 851 REG_READ(map->conf); 852 853 gma_wait_for_vblank(dev); 854 855 REG_WRITE(map->cntr, dspcntr); 856 857 /* Flush the plane changes */ 858 { 859 struct drm_crtc_helper_funcs *crtc_funcs = 860 crtc->helper_private; 861 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 862 } 863 864 gma_wait_for_vblank(dev); 865 866 return 0; 867 } 868 869 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 870 871 /* FIXME: why are we using this, should it be cdv_ in this tree ? */ 872 873 static void i8xx_clock(int refclk, struct gma_clock_t *clock) 874 { 875 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 876 clock->p = clock->p1 * clock->p2; 877 clock->vco = refclk * clock->m / (clock->n + 2); 878 clock->dot = clock->vco / clock->p; 879 } 880 881 /* Returns the clock of the currently programmed mode of the given pipe. */ 882 static int cdv_intel_crtc_clock_get(struct drm_device *dev, 883 struct drm_crtc *crtc) 884 { 885 struct drm_psb_private *dev_priv = dev->dev_private; 886 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 887 int pipe = gma_crtc->pipe; 888 const struct psb_offset *map = &dev_priv->regmap[pipe]; 889 u32 dpll; 890 u32 fp; 891 struct gma_clock_t clock; 892 bool is_lvds; 893 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 894 895 if (gma_power_begin(dev, false)) { 896 dpll = REG_READ(map->dpll); 897 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 898 fp = REG_READ(map->fp0); 899 else 900 fp = REG_READ(map->fp1); 901 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 902 gma_power_end(dev); 903 } else { 904 dpll = p->dpll; 905 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 906 fp = p->fp0; 907 else 908 fp = p->fp1; 909 910 is_lvds = (pipe == 1) && 911 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); 912 } 913 914 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 915 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 916 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 917 918 if (is_lvds) { 919 clock.p1 = 920 ffs((dpll & 921 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 922 DPLL_FPA01_P1_POST_DIV_SHIFT); 923 if (clock.p1 == 0) { 924 clock.p1 = 4; 925 dev_err(dev->dev, "PLL %d\n", dpll); 926 } 927 clock.p2 = 14; 928 929 if ((dpll & PLL_REF_INPUT_MASK) == 930 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 931 /* XXX: might not be 66MHz */ 932 i8xx_clock(66000, &clock); 933 } else 934 i8xx_clock(48000, &clock); 935 } else { 936 if (dpll & PLL_P1_DIVIDE_BY_TWO) 937 clock.p1 = 2; 938 else { 939 clock.p1 = 940 ((dpll & 941 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 942 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 943 } 944 if (dpll & PLL_P2_DIVIDE_BY_4) 945 clock.p2 = 4; 946 else 947 clock.p2 = 2; 948 949 i8xx_clock(48000, &clock); 950 } 951 952 /* XXX: It would be nice to validate the clocks, but we can't reuse 953 * i830PllIsValid() because it relies on the xf86_config connector 954 * configuration being accurate, which it isn't necessarily. 955 */ 956 957 return clock.dot; 958 } 959 960 /** Returns the currently programmed mode of the given pipe. */ 961 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, 962 struct drm_crtc *crtc) 963 { 964 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 965 int pipe = gma_crtc->pipe; 966 struct drm_psb_private *dev_priv = dev->dev_private; 967 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 968 const struct psb_offset *map = &dev_priv->regmap[pipe]; 969 struct drm_display_mode *mode; 970 int htot; 971 int hsync; 972 int vtot; 973 int vsync; 974 975 if (gma_power_begin(dev, false)) { 976 htot = REG_READ(map->htotal); 977 hsync = REG_READ(map->hsync); 978 vtot = REG_READ(map->vtotal); 979 vsync = REG_READ(map->vsync); 980 gma_power_end(dev); 981 } else { 982 htot = p->htotal; 983 hsync = p->hsync; 984 vtot = p->vtotal; 985 vsync = p->vsync; 986 } 987 988 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 989 if (!mode) 990 return NULL; 991 992 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); 993 mode->hdisplay = (htot & 0xffff) + 1; 994 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 995 mode->hsync_start = (hsync & 0xffff) + 1; 996 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 997 mode->vdisplay = (vtot & 0xffff) + 1; 998 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 999 mode->vsync_start = (vsync & 0xffff) + 1; 1000 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 1001 1002 drm_mode_set_name(mode); 1003 drm_mode_set_crtcinfo(mode, 0); 1004 1005 return mode; 1006 } 1007 1008 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { 1009 .dpms = gma_crtc_dpms, 1010 .mode_fixup = gma_crtc_mode_fixup, 1011 .mode_set = cdv_intel_crtc_mode_set, 1012 .mode_set_base = gma_pipe_set_base, 1013 .prepare = gma_crtc_prepare, 1014 .commit = gma_crtc_commit, 1015 .disable = gma_crtc_disable, 1016 }; 1017 1018 const struct drm_crtc_funcs cdv_intel_crtc_funcs = { 1019 .save = gma_crtc_save, 1020 .restore = gma_crtc_restore, 1021 .cursor_set = gma_crtc_cursor_set, 1022 .cursor_move = gma_crtc_cursor_move, 1023 .gamma_set = gma_crtc_gamma_set, 1024 .set_config = gma_crtc_set_config, 1025 .destroy = gma_crtc_destroy, 1026 }; 1027 1028 const struct gma_clock_funcs cdv_clock_funcs = { 1029 .clock = cdv_intel_clock, 1030 .limit = cdv_intel_limit, 1031 .pll_is_valid = gma_pll_is_valid, 1032 }; 1033