1 /* 2 * Copyright © 2006-2011 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * Authors: 18 * Eric Anholt <eric@anholt.net> 19 */ 20 21 #include <linux/delay.h> 22 #include <linux/i2c.h> 23 24 #include <drm/drm_crtc.h> 25 26 #include "cdv_device.h" 27 #include "framebuffer.h" 28 #include "gma_display.h" 29 #include "power.h" 30 #include "psb_drv.h" 31 #include "psb_intel_drv.h" 32 #include "psb_intel_reg.h" 33 34 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, 35 struct drm_crtc *crtc, int target, 36 int refclk, struct gma_clock_t *best_clock); 37 38 39 #define CDV_LIMIT_SINGLE_LVDS_96 0 40 #define CDV_LIMIT_SINGLE_LVDS_100 1 41 #define CDV_LIMIT_DAC_HDMI_27 2 42 #define CDV_LIMIT_DAC_HDMI_96 3 43 #define CDV_LIMIT_DP_27 4 44 #define CDV_LIMIT_DP_100 5 45 46 static const struct gma_limit_t cdv_intel_limits[] = { 47 { /* CDV_SINGLE_LVDS_96MHz */ 48 .dot = {.min = 20000, .max = 115500}, 49 .vco = {.min = 1800000, .max = 3600000}, 50 .n = {.min = 2, .max = 6}, 51 .m = {.min = 60, .max = 160}, 52 .m1 = {.min = 0, .max = 0}, 53 .m2 = {.min = 58, .max = 158}, 54 .p = {.min = 28, .max = 140}, 55 .p1 = {.min = 2, .max = 10}, 56 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, 57 .find_pll = gma_find_best_pll, 58 }, 59 { /* CDV_SINGLE_LVDS_100MHz */ 60 .dot = {.min = 20000, .max = 115500}, 61 .vco = {.min = 1800000, .max = 3600000}, 62 .n = {.min = 2, .max = 6}, 63 .m = {.min = 60, .max = 160}, 64 .m1 = {.min = 0, .max = 0}, 65 .m2 = {.min = 58, .max = 158}, 66 .p = {.min = 28, .max = 140}, 67 .p1 = {.min = 2, .max = 10}, 68 /* The single-channel range is 25-112Mhz, and dual-channel 69 * is 80-224Mhz. Prefer single channel as much as possible. 70 */ 71 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14}, 72 .find_pll = gma_find_best_pll, 73 }, 74 { /* CDV_DAC_HDMI_27MHz */ 75 .dot = {.min = 20000, .max = 400000}, 76 .vco = {.min = 1809000, .max = 3564000}, 77 .n = {.min = 1, .max = 1}, 78 .m = {.min = 67, .max = 132}, 79 .m1 = {.min = 0, .max = 0}, 80 .m2 = {.min = 65, .max = 130}, 81 .p = {.min = 5, .max = 90}, 82 .p1 = {.min = 1, .max = 9}, 83 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, 84 .find_pll = gma_find_best_pll, 85 }, 86 { /* CDV_DAC_HDMI_96MHz */ 87 .dot = {.min = 20000, .max = 400000}, 88 .vco = {.min = 1800000, .max = 3600000}, 89 .n = {.min = 2, .max = 6}, 90 .m = {.min = 60, .max = 160}, 91 .m1 = {.min = 0, .max = 0}, 92 .m2 = {.min = 58, .max = 158}, 93 .p = {.min = 5, .max = 100}, 94 .p1 = {.min = 1, .max = 10}, 95 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5}, 96 .find_pll = gma_find_best_pll, 97 }, 98 { /* CDV_DP_27MHz */ 99 .dot = {.min = 160000, .max = 272000}, 100 .vco = {.min = 1809000, .max = 3564000}, 101 .n = {.min = 1, .max = 1}, 102 .m = {.min = 67, .max = 132}, 103 .m1 = {.min = 0, .max = 0}, 104 .m2 = {.min = 65, .max = 130}, 105 .p = {.min = 5, .max = 90}, 106 .p1 = {.min = 1, .max = 9}, 107 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, 108 .find_pll = cdv_intel_find_dp_pll, 109 }, 110 { /* CDV_DP_100MHz */ 111 .dot = {.min = 160000, .max = 272000}, 112 .vco = {.min = 1800000, .max = 3600000}, 113 .n = {.min = 2, .max = 6}, 114 .m = {.min = 60, .max = 164}, 115 .m1 = {.min = 0, .max = 0}, 116 .m2 = {.min = 58, .max = 162}, 117 .p = {.min = 5, .max = 100}, 118 .p1 = {.min = 1, .max = 10}, 119 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10}, 120 .find_pll = cdv_intel_find_dp_pll, 121 } 122 }; 123 124 #define _wait_for(COND, MS, W) ({ \ 125 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 126 int ret__ = 0; \ 127 while (!(COND)) { \ 128 if (time_after(jiffies, timeout__)) { \ 129 ret__ = -ETIMEDOUT; \ 130 break; \ 131 } \ 132 if (W && !in_dbg_master()) \ 133 msleep(W); \ 134 } \ 135 ret__; \ 136 }) 137 138 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 139 140 141 int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val) 142 { 143 int ret; 144 145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 146 if (ret) { 147 DRM_ERROR("timeout waiting for SB to idle before read\n"); 148 return ret; 149 } 150 151 REG_WRITE(SB_ADDR, reg); 152 REG_WRITE(SB_PCKT, 153 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | 154 SET_FIELD(SB_DEST_DPLL, SB_DEST) | 155 SET_FIELD(0xf, SB_BYTE_ENABLE)); 156 157 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 158 if (ret) { 159 DRM_ERROR("timeout waiting for SB to idle after read\n"); 160 return ret; 161 } 162 163 *val = REG_READ(SB_DATA); 164 165 return 0; 166 } 167 168 int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val) 169 { 170 int ret; 171 static bool dpio_debug = true; 172 u32 temp; 173 174 if (dpio_debug) { 175 if (cdv_sb_read(dev, reg, &temp) == 0) 176 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); 177 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); 178 } 179 180 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 181 if (ret) { 182 DRM_ERROR("timeout waiting for SB to idle before write\n"); 183 return ret; 184 } 185 186 REG_WRITE(SB_ADDR, reg); 187 REG_WRITE(SB_DATA, val); 188 REG_WRITE(SB_PCKT, 189 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | 190 SET_FIELD(SB_DEST_DPLL, SB_DEST) | 191 SET_FIELD(0xf, SB_BYTE_ENABLE)); 192 193 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); 194 if (ret) { 195 DRM_ERROR("timeout waiting for SB to idle after write\n"); 196 return ret; 197 } 198 199 if (dpio_debug) { 200 if (cdv_sb_read(dev, reg, &temp) == 0) 201 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); 202 } 203 204 return 0; 205 } 206 207 /* Reset the DPIO configuration register. The BIOS does this at every 208 * mode set. 209 */ 210 void cdv_sb_reset(struct drm_device *dev) 211 { 212 213 REG_WRITE(DPIO_CFG, 0); 214 REG_READ(DPIO_CFG); 215 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 216 } 217 218 /* Unlike most Intel display engines, on Cedarview the DPLL registers 219 * are behind this sideband bus. They must be programmed while the 220 * DPLL reference clock is on in the DPLL control register, but before 221 * the DPLL is enabled in the DPLL control register. 222 */ 223 static int 224 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, 225 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select) 226 { 227 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 228 int pipe = gma_crtc->pipe; 229 u32 m, n_vco, p; 230 int ret = 0; 231 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 232 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB; 233 u32 ref_value; 234 u32 lane_reg, lane_value; 235 236 cdv_sb_reset(dev); 237 238 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); 239 240 udelay(100); 241 242 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ 243 ref_value = 0x68A701; 244 245 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value); 246 247 /* We don't know what the other fields of these regs are, so 248 * leave them in place. 249 */ 250 /* 251 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk 252 * for the pipe A/B. Display spec 1.06 has wrong definition. 253 * Correct definition is like below: 254 * 255 * refclka mean use clock from same PLL 256 * 257 * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll 258 * 259 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA 260 * 261 */ 262 ret = cdv_sb_read(dev, ref_sfr, &ref_value); 263 if (ret) 264 return ret; 265 ref_value &= ~(REF_CLK_MASK); 266 267 /* use DPLL_A for pipeB on CRT/HDMI */ 268 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) { 269 DRM_DEBUG_KMS("use DPLLA for pipe B\n"); 270 ref_value |= REF_CLK_DPLLA; 271 } else { 272 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); 273 ref_value |= REF_CLK_DPLL; 274 } 275 ret = cdv_sb_write(dev, ref_sfr, ref_value); 276 if (ret) 277 return ret; 278 279 ret = cdv_sb_read(dev, SB_M(pipe), &m); 280 if (ret) 281 return ret; 282 m &= ~SB_M_DIVIDER_MASK; 283 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); 284 ret = cdv_sb_write(dev, SB_M(pipe), m); 285 if (ret) 286 return ret; 287 288 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco); 289 if (ret) 290 return ret; 291 292 /* Follow the BIOS to program the N_DIVIDER REG */ 293 n_vco &= 0xFFFF; 294 n_vco |= 0x107; 295 n_vco &= ~(SB_N_VCO_SEL_MASK | 296 SB_N_DIVIDER_MASK | 297 SB_N_CB_TUNE_MASK); 298 299 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); 300 301 if (clock->vco < 2250000) { 302 n_vco |= (2 << SB_N_CB_TUNE_SHIFT); 303 n_vco |= (0 << SB_N_VCO_SEL_SHIFT); 304 } else if (clock->vco < 2750000) { 305 n_vco |= (1 << SB_N_CB_TUNE_SHIFT); 306 n_vco |= (1 << SB_N_VCO_SEL_SHIFT); 307 } else if (clock->vco < 3300000) { 308 n_vco |= (0 << SB_N_CB_TUNE_SHIFT); 309 n_vco |= (2 << SB_N_VCO_SEL_SHIFT); 310 } else { 311 n_vco |= (0 << SB_N_CB_TUNE_SHIFT); 312 n_vco |= (3 << SB_N_VCO_SEL_SHIFT); 313 } 314 315 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco); 316 if (ret) 317 return ret; 318 319 ret = cdv_sb_read(dev, SB_P(pipe), &p); 320 if (ret) 321 return ret; 322 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK); 323 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); 324 switch (clock->p2) { 325 case 5: 326 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); 327 break; 328 case 10: 329 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); 330 break; 331 case 14: 332 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); 333 break; 334 case 7: 335 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); 336 break; 337 default: 338 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); 339 return -EINVAL; 340 } 341 ret = cdv_sb_write(dev, SB_P(pipe), p); 342 if (ret) 343 return ret; 344 345 if (ddi_select) { 346 if ((ddi_select & DDI_MASK) == DDI0_SELECT) { 347 lane_reg = PSB_LANE0; 348 cdv_sb_read(dev, lane_reg, &lane_value); 349 lane_value &= ~(LANE_PLL_MASK); 350 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 351 cdv_sb_write(dev, lane_reg, lane_value); 352 353 lane_reg = PSB_LANE1; 354 cdv_sb_read(dev, lane_reg, &lane_value); 355 lane_value &= ~(LANE_PLL_MASK); 356 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 357 cdv_sb_write(dev, lane_reg, lane_value); 358 } else { 359 lane_reg = PSB_LANE2; 360 cdv_sb_read(dev, lane_reg, &lane_value); 361 lane_value &= ~(LANE_PLL_MASK); 362 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 363 cdv_sb_write(dev, lane_reg, lane_value); 364 365 lane_reg = PSB_LANE3; 366 cdv_sb_read(dev, lane_reg, &lane_value); 367 lane_value &= ~(LANE_PLL_MASK); 368 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); 369 cdv_sb_write(dev, lane_reg, lane_value); 370 } 371 } 372 return 0; 373 } 374 375 static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc, 376 int refclk) 377 { 378 const struct gma_limit_t *limit; 379 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 380 /* 381 * Now only single-channel LVDS is supported on CDV. If it is 382 * incorrect, please add the dual-channel LVDS. 383 */ 384 if (refclk == 96000) 385 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96]; 386 else 387 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100]; 388 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 389 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 390 if (refclk == 27000) 391 limit = &cdv_intel_limits[CDV_LIMIT_DP_27]; 392 else 393 limit = &cdv_intel_limits[CDV_LIMIT_DP_100]; 394 } else { 395 if (refclk == 27000) 396 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27]; 397 else 398 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96]; 399 } 400 return limit; 401 } 402 403 /* m1 is reserved as 0 in CDV, n is a ring counter */ 404 static void cdv_intel_clock(int refclk, struct gma_clock_t *clock) 405 { 406 clock->m = clock->m2 + 2; 407 clock->p = clock->p1 * clock->p2; 408 clock->vco = (refclk * clock->m) / clock->n; 409 clock->dot = clock->vco / clock->p; 410 } 411 412 static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit, 413 struct drm_crtc *crtc, int target, 414 int refclk, 415 struct gma_clock_t *best_clock) 416 { 417 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 418 struct gma_clock_t clock; 419 420 switch (refclk) { 421 case 27000: 422 if (target < 200000) { 423 clock.p1 = 2; 424 clock.p2 = 10; 425 clock.n = 1; 426 clock.m1 = 0; 427 clock.m2 = 118; 428 } else { 429 clock.p1 = 1; 430 clock.p2 = 10; 431 clock.n = 1; 432 clock.m1 = 0; 433 clock.m2 = 98; 434 } 435 break; 436 437 case 100000: 438 if (target < 200000) { 439 clock.p1 = 2; 440 clock.p2 = 10; 441 clock.n = 5; 442 clock.m1 = 0; 443 clock.m2 = 160; 444 } else { 445 clock.p1 = 1; 446 clock.p2 = 10; 447 clock.n = 5; 448 clock.m1 = 0; 449 clock.m2 = 133; 450 } 451 break; 452 453 default: 454 return false; 455 } 456 457 gma_crtc->clock_funcs->clock(refclk, &clock); 458 memcpy(best_clock, &clock, sizeof(struct gma_clock_t)); 459 return true; 460 } 461 462 #define FIFO_PIPEA (1 << 0) 463 #define FIFO_PIPEB (1 << 1) 464 465 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe) 466 { 467 struct drm_crtc *crtc; 468 struct drm_psb_private *dev_priv = dev->dev_private; 469 struct gma_crtc *gma_crtc = NULL; 470 471 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 472 gma_crtc = to_gma_crtc(crtc); 473 474 if (crtc->primary->fb == NULL || !gma_crtc->active) 475 return false; 476 return true; 477 } 478 479 void cdv_disable_sr(struct drm_device *dev) 480 { 481 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { 482 483 /* Disable self-refresh before adjust WM */ 484 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); 485 REG_READ(FW_BLC_SELF); 486 487 gma_wait_for_vblank(dev); 488 489 /* Cedarview workaround to write ovelay plane, which force to leave 490 * MAX_FIFO state. 491 */ 492 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); 493 REG_READ(OV_OVADD); 494 495 gma_wait_for_vblank(dev); 496 } 497 498 } 499 500 void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc) 501 { 502 struct drm_psb_private *dev_priv = dev->dev_private; 503 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 504 505 /* Is only one pipe enabled? */ 506 if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) { 507 u32 fw; 508 509 fw = REG_READ(DSPFW1); 510 fw &= ~DSP_FIFO_SR_WM_MASK; 511 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT); 512 fw &= ~CURSOR_B_FIFO_WM_MASK; 513 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT); 514 REG_WRITE(DSPFW1, fw); 515 516 fw = REG_READ(DSPFW2); 517 fw &= ~CURSOR_A_FIFO_WM_MASK; 518 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT); 519 fw &= ~DSP_PLANE_C_FIFO_WM_MASK; 520 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT); 521 REG_WRITE(DSPFW2, fw); 522 523 REG_WRITE(DSPFW3, 0x36000000); 524 525 /* ignore FW4 */ 526 527 /* Is pipe b lvds ? */ 528 if (gma_crtc->pipe == 1 && 529 gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 530 REG_WRITE(DSPFW5, 0x00040330); 531 } else { 532 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) | 533 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) | 534 (3 << CURSOR_B_FIFO_WM1_SHIFT) | 535 (4 << CURSOR_FIFO_SR_WM1_SHIFT); 536 REG_WRITE(DSPFW5, fw); 537 } 538 539 REG_WRITE(DSPFW6, 0x10); 540 541 gma_wait_for_vblank(dev); 542 543 /* enable self-refresh for single pipe active */ 544 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 545 REG_READ(FW_BLC_SELF); 546 gma_wait_for_vblank(dev); 547 548 } else { 549 550 /* HW team suggested values... */ 551 REG_WRITE(DSPFW1, 0x3f880808); 552 REG_WRITE(DSPFW2, 0x0b020202); 553 REG_WRITE(DSPFW3, 0x24000000); 554 REG_WRITE(DSPFW4, 0x08030202); 555 REG_WRITE(DSPFW5, 0x01010101); 556 REG_WRITE(DSPFW6, 0x1d0); 557 558 gma_wait_for_vblank(dev); 559 560 dev_priv->ops->disable_sr(dev); 561 } 562 } 563 564 /** 565 * Return the pipe currently connected to the panel fitter, 566 * or -1 if the panel fitter is not present or not in use 567 */ 568 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev) 569 { 570 u32 pfit_control; 571 572 pfit_control = REG_READ(PFIT_CONTROL); 573 574 /* See if the panel fitter is in use */ 575 if ((pfit_control & PFIT_ENABLE) == 0) 576 return -1; 577 return (pfit_control >> 29) & 0x3; 578 } 579 580 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, 581 struct drm_display_mode *mode, 582 struct drm_display_mode *adjusted_mode, 583 int x, int y, 584 struct drm_framebuffer *old_fb) 585 { 586 struct drm_device *dev = crtc->dev; 587 struct drm_psb_private *dev_priv = dev->dev_private; 588 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 589 int pipe = gma_crtc->pipe; 590 const struct psb_offset *map = &dev_priv->regmap[pipe]; 591 int refclk; 592 struct gma_clock_t clock; 593 u32 dpll = 0, dspcntr, pipeconf; 594 bool ok; 595 bool is_crt = false, is_lvds = false, is_tv = false; 596 bool is_hdmi = false, is_dp = false; 597 struct drm_mode_config *mode_config = &dev->mode_config; 598 struct drm_connector *connector; 599 const struct gma_limit_t *limit; 600 u32 ddi_select = 0; 601 bool is_edp = false; 602 603 list_for_each_entry(connector, &mode_config->connector_list, head) { 604 struct gma_encoder *gma_encoder = 605 gma_attached_encoder(connector); 606 607 if (!connector->encoder 608 || connector->encoder->crtc != crtc) 609 continue; 610 611 ddi_select = gma_encoder->ddi_select; 612 switch (gma_encoder->type) { 613 case INTEL_OUTPUT_LVDS: 614 is_lvds = true; 615 break; 616 case INTEL_OUTPUT_TVOUT: 617 is_tv = true; 618 break; 619 case INTEL_OUTPUT_ANALOG: 620 is_crt = true; 621 break; 622 case INTEL_OUTPUT_HDMI: 623 is_hdmi = true; 624 break; 625 case INTEL_OUTPUT_DISPLAYPORT: 626 is_dp = true; 627 break; 628 case INTEL_OUTPUT_EDP: 629 is_edp = true; 630 break; 631 default: 632 DRM_ERROR("invalid output type.\n"); 633 return 0; 634 } 635 } 636 637 if (dev_priv->dplla_96mhz) 638 /* low-end sku, 96/100 mhz */ 639 refclk = 96000; 640 else 641 /* high-end sku, 27/100 mhz */ 642 refclk = 27000; 643 if (is_dp || is_edp) { 644 /* 645 * Based on the spec the low-end SKU has only CRT/LVDS. So it is 646 * unnecessary to consider it for DP/eDP. 647 * On the high-end SKU, it will use the 27/100M reference clk 648 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise 649 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose 650 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. 651 */ 652 if (pipe == 0) 653 refclk = 27000; 654 else 655 refclk = 100000; 656 } 657 658 if (is_lvds && dev_priv->lvds_use_ssc) { 659 refclk = dev_priv->lvds_ssc_freq * 1000; 660 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); 661 } 662 663 drm_mode_debug_printmodeline(adjusted_mode); 664 665 limit = gma_crtc->clock_funcs->limit(crtc, refclk); 666 667 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, 668 &clock); 669 if (!ok) { 670 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d", 671 adjusted_mode->clock, clock.dot); 672 return 0; 673 } 674 675 dpll = DPLL_VGA_MODE_DIS; 676 if (is_tv) { 677 /* XXX: just matching BIOS for now */ 678 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 679 dpll |= 3; 680 } 681 /* dpll |= PLL_REF_INPUT_DREFCLK; */ 682 683 if (is_dp || is_edp) { 684 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); 685 } else { 686 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0); 687 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0); 688 REG_WRITE(PIPE_DP_LINK_M(pipe), 0); 689 REG_WRITE(PIPE_DP_LINK_N(pipe), 0); 690 } 691 692 dpll |= DPLL_SYNCLOCK_ENABLE; 693 /* if (is_lvds) 694 dpll |= DPLLB_MODE_LVDS; 695 else 696 dpll |= DPLLB_MODE_DAC_SERIAL; */ 697 /* dpll |= (2 << 11); */ 698 699 /* setup pipeconf */ 700 pipeconf = REG_READ(map->conf); 701 702 pipeconf &= ~(PIPE_BPC_MASK); 703 if (is_edp) { 704 switch (dev_priv->edp.bpp) { 705 case 24: 706 pipeconf |= PIPE_8BPC; 707 break; 708 case 18: 709 pipeconf |= PIPE_6BPC; 710 break; 711 case 30: 712 pipeconf |= PIPE_10BPC; 713 break; 714 default: 715 pipeconf |= PIPE_8BPC; 716 break; 717 } 718 } else if (is_lvds) { 719 /* the BPC will be 6 if it is 18-bit LVDS panel */ 720 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) 721 pipeconf |= PIPE_8BPC; 722 else 723 pipeconf |= PIPE_6BPC; 724 } else 725 pipeconf |= PIPE_8BPC; 726 727 /* Set up the display plane register */ 728 dspcntr = DISPPLANE_GAMMA_ENABLE; 729 730 if (pipe == 0) 731 dspcntr |= DISPPLANE_SEL_PIPE_A; 732 else 733 dspcntr |= DISPPLANE_SEL_PIPE_B; 734 735 dspcntr |= DISPLAY_PLANE_ENABLE; 736 pipeconf |= PIPEACONF_ENABLE; 737 738 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); 739 REG_READ(map->dpll); 740 741 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select); 742 743 udelay(150); 744 745 746 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 747 * This is an exception to the general rule that mode_set doesn't turn 748 * things on. 749 */ 750 if (is_lvds) { 751 u32 lvds = REG_READ(LVDS); 752 753 lvds |= 754 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | 755 LVDS_PIPEB_SELECT; 756 /* Set the B0-B3 data pairs corresponding to 757 * whether we're going to 758 * set the DPLLs for dual-channel mode or not. 759 */ 760 if (clock.p2 == 7) 761 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 762 else 763 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 764 765 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 766 * appropriately here, but we need to look more 767 * thoroughly into how panels behave in the two modes. 768 */ 769 770 REG_WRITE(LVDS, lvds); 771 REG_READ(LVDS); 772 } 773 774 dpll |= DPLL_VCO_ENABLE; 775 776 /* Disable the panel fitter if it was on our pipe */ 777 if (cdv_intel_panel_fitter_pipe(dev) == pipe) 778 REG_WRITE(PFIT_CONTROL, 0); 779 780 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 781 drm_mode_debug_printmodeline(mode); 782 783 REG_WRITE(map->dpll, 784 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); 785 REG_READ(map->dpll); 786 /* Wait for the clocks to stabilize. */ 787 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */ 788 789 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { 790 dev_err(dev->dev, "Failed to get DPLL lock\n"); 791 return -EBUSY; 792 } 793 794 { 795 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 796 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); 797 } 798 799 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | 800 ((adjusted_mode->crtc_htotal - 1) << 16)); 801 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | 802 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 803 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | 804 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 805 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | 806 ((adjusted_mode->crtc_vtotal - 1) << 16)); 807 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | 808 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 809 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | 810 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 811 /* pipesrc and dspsize control the size that is scaled from, 812 * which should always be the user's requested size. 813 */ 814 REG_WRITE(map->size, 815 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 816 REG_WRITE(map->pos, 0); 817 REG_WRITE(map->src, 818 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 819 REG_WRITE(map->conf, pipeconf); 820 REG_READ(map->conf); 821 822 gma_wait_for_vblank(dev); 823 824 REG_WRITE(map->cntr, dspcntr); 825 826 /* Flush the plane changes */ 827 { 828 const struct drm_crtc_helper_funcs *crtc_funcs = 829 crtc->helper_private; 830 crtc_funcs->mode_set_base(crtc, x, y, old_fb); 831 } 832 833 gma_wait_for_vblank(dev); 834 835 return 0; 836 } 837 838 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ 839 840 /* FIXME: why are we using this, should it be cdv_ in this tree ? */ 841 842 static void i8xx_clock(int refclk, struct gma_clock_t *clock) 843 { 844 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 845 clock->p = clock->p1 * clock->p2; 846 clock->vco = refclk * clock->m / (clock->n + 2); 847 clock->dot = clock->vco / clock->p; 848 } 849 850 /* Returns the clock of the currently programmed mode of the given pipe. */ 851 static int cdv_intel_crtc_clock_get(struct drm_device *dev, 852 struct drm_crtc *crtc) 853 { 854 struct drm_psb_private *dev_priv = dev->dev_private; 855 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 856 int pipe = gma_crtc->pipe; 857 const struct psb_offset *map = &dev_priv->regmap[pipe]; 858 u32 dpll; 859 u32 fp; 860 struct gma_clock_t clock; 861 bool is_lvds; 862 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 863 864 if (gma_power_begin(dev, false)) { 865 dpll = REG_READ(map->dpll); 866 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 867 fp = REG_READ(map->fp0); 868 else 869 fp = REG_READ(map->fp1); 870 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 871 gma_power_end(dev); 872 } else { 873 dpll = p->dpll; 874 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 875 fp = p->fp0; 876 else 877 fp = p->fp1; 878 879 is_lvds = (pipe == 1) && 880 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); 881 } 882 883 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 884 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 885 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 886 887 if (is_lvds) { 888 clock.p1 = 889 ffs((dpll & 890 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 891 DPLL_FPA01_P1_POST_DIV_SHIFT); 892 if (clock.p1 == 0) { 893 clock.p1 = 4; 894 dev_err(dev->dev, "PLL %d\n", dpll); 895 } 896 clock.p2 = 14; 897 898 if ((dpll & PLL_REF_INPUT_MASK) == 899 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 900 /* XXX: might not be 66MHz */ 901 i8xx_clock(66000, &clock); 902 } else 903 i8xx_clock(48000, &clock); 904 } else { 905 if (dpll & PLL_P1_DIVIDE_BY_TWO) 906 clock.p1 = 2; 907 else { 908 clock.p1 = 909 ((dpll & 910 DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 911 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 912 } 913 if (dpll & PLL_P2_DIVIDE_BY_4) 914 clock.p2 = 4; 915 else 916 clock.p2 = 2; 917 918 i8xx_clock(48000, &clock); 919 } 920 921 /* XXX: It would be nice to validate the clocks, but we can't reuse 922 * i830PllIsValid() because it relies on the xf86_config connector 923 * configuration being accurate, which it isn't necessarily. 924 */ 925 926 return clock.dot; 927 } 928 929 /** Returns the currently programmed mode of the given pipe. */ 930 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, 931 struct drm_crtc *crtc) 932 { 933 struct gma_crtc *gma_crtc = to_gma_crtc(crtc); 934 int pipe = gma_crtc->pipe; 935 struct drm_psb_private *dev_priv = dev->dev_private; 936 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; 937 const struct psb_offset *map = &dev_priv->regmap[pipe]; 938 struct drm_display_mode *mode; 939 int htot; 940 int hsync; 941 int vtot; 942 int vsync; 943 944 if (gma_power_begin(dev, false)) { 945 htot = REG_READ(map->htotal); 946 hsync = REG_READ(map->hsync); 947 vtot = REG_READ(map->vtotal); 948 vsync = REG_READ(map->vsync); 949 gma_power_end(dev); 950 } else { 951 htot = p->htotal; 952 hsync = p->hsync; 953 vtot = p->vtotal; 954 vsync = p->vsync; 955 } 956 957 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 958 if (!mode) 959 return NULL; 960 961 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); 962 mode->hdisplay = (htot & 0xffff) + 1; 963 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 964 mode->hsync_start = (hsync & 0xffff) + 1; 965 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 966 mode->vdisplay = (vtot & 0xffff) + 1; 967 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 968 mode->vsync_start = (vsync & 0xffff) + 1; 969 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 970 971 drm_mode_set_name(mode); 972 drm_mode_set_crtcinfo(mode, 0); 973 974 return mode; 975 } 976 977 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = { 978 .dpms = gma_crtc_dpms, 979 .mode_set = cdv_intel_crtc_mode_set, 980 .mode_set_base = gma_pipe_set_base, 981 .prepare = gma_crtc_prepare, 982 .commit = gma_crtc_commit, 983 .disable = gma_crtc_disable, 984 }; 985 986 const struct drm_crtc_funcs cdv_intel_crtc_funcs = { 987 .cursor_set = gma_crtc_cursor_set, 988 .cursor_move = gma_crtc_cursor_move, 989 .gamma_set = gma_crtc_gamma_set, 990 .set_config = gma_crtc_set_config, 991 .destroy = gma_crtc_destroy, 992 }; 993 994 const struct gma_clock_funcs cdv_clock_funcs = { 995 .clock = cdv_intel_clock, 996 .limit = cdv_intel_limit, 997 .pll_is_valid = gma_pll_is_valid, 998 }; 999