1 /************************************************************************** 2 * Copyright (c) 2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 #include <linux/backlight.h> 21 #include <linux/delay.h> 22 23 #include <drm/drm.h> 24 25 #include "cdv_device.h" 26 #include "gma_device.h" 27 #include "intel_bios.h" 28 #include "psb_drv.h" 29 #include "psb_intel_reg.h" 30 #include "psb_reg.h" 31 32 #define VGA_SR_INDEX 0x3c4 33 #define VGA_SR_DATA 0x3c5 34 35 static void cdv_disable_vga(struct drm_device *dev) 36 { 37 u8 sr1; 38 u32 vga_reg; 39 40 vga_reg = VGACNTRL; 41 42 outb(1, VGA_SR_INDEX); 43 sr1 = inb(VGA_SR_DATA); 44 outb(sr1 | 1<<5, VGA_SR_DATA); 45 udelay(300); 46 47 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 48 REG_READ(vga_reg); 49 } 50 51 static int cdv_output_init(struct drm_device *dev) 52 { 53 struct drm_psb_private *dev_priv = dev->dev_private; 54 55 drm_mode_create_scaling_mode_property(dev); 56 57 cdv_disable_vga(dev); 58 59 cdv_intel_crt_init(dev, &dev_priv->mode_dev); 60 cdv_intel_lvds_init(dev, &dev_priv->mode_dev); 61 62 /* These bits indicate HDMI not SDVO on CDV */ 63 if (REG_READ(SDVOB) & SDVO_DETECTED) { 64 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); 65 if (REG_READ(DP_B) & DP_DETECTED) 66 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B); 67 } 68 69 if (REG_READ(SDVOC) & SDVO_DETECTED) { 70 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); 71 if (REG_READ(DP_C) & DP_DETECTED) 72 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C); 73 } 74 return 0; 75 } 76 77 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 78 79 /* 80 * Cedartrail Backlght Interfaces 81 */ 82 83 static struct backlight_device *cdv_backlight_device; 84 85 static int cdv_backlight_combination_mode(struct drm_device *dev) 86 { 87 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 88 } 89 90 static u32 cdv_get_max_backlight(struct drm_device *dev) 91 { 92 u32 max = REG_READ(BLC_PWM_CTL); 93 94 if (max == 0) { 95 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); 96 /* i915 does this, I believe which means that we should not 97 * smash PWM control as firmware will take control of it. */ 98 return 1; 99 } 100 101 max >>= 16; 102 if (cdv_backlight_combination_mode(dev)) 103 max *= 0xff; 104 return max; 105 } 106 107 static int cdv_get_brightness(struct backlight_device *bd) 108 { 109 struct drm_device *dev = bl_get_data(bd); 110 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 111 112 if (cdv_backlight_combination_mode(dev)) { 113 u8 lbpc; 114 115 val &= ~1; 116 pci_read_config_byte(dev->pdev, 0xF4, &lbpc); 117 val *= lbpc; 118 } 119 return (val * 100)/cdv_get_max_backlight(dev); 120 121 } 122 123 static int cdv_set_brightness(struct backlight_device *bd) 124 { 125 struct drm_device *dev = bl_get_data(bd); 126 int level = bd->props.brightness; 127 u32 blc_pwm_ctl; 128 129 /* Percentage 1-100% being valid */ 130 if (level < 1) 131 level = 1; 132 133 level *= cdv_get_max_backlight(dev); 134 level /= 100; 135 136 if (cdv_backlight_combination_mode(dev)) { 137 u32 max = cdv_get_max_backlight(dev); 138 u8 lbpc; 139 140 lbpc = level * 0xfe / max + 1; 141 level /= lbpc; 142 143 pci_write_config_byte(dev->pdev, 0xF4, lbpc); 144 } 145 146 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 147 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 148 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 149 return 0; 150 } 151 152 static const struct backlight_ops cdv_ops = { 153 .get_brightness = cdv_get_brightness, 154 .update_status = cdv_set_brightness, 155 }; 156 157 static int cdv_backlight_init(struct drm_device *dev) 158 { 159 struct drm_psb_private *dev_priv = dev->dev_private; 160 struct backlight_properties props; 161 162 memset(&props, 0, sizeof(struct backlight_properties)); 163 props.max_brightness = 100; 164 props.type = BACKLIGHT_PLATFORM; 165 166 cdv_backlight_device = backlight_device_register("psb-bl", 167 NULL, (void *)dev, &cdv_ops, &props); 168 if (IS_ERR(cdv_backlight_device)) 169 return PTR_ERR(cdv_backlight_device); 170 171 cdv_backlight_device->props.brightness = 172 cdv_get_brightness(cdv_backlight_device); 173 backlight_update_status(cdv_backlight_device); 174 dev_priv->backlight_device = cdv_backlight_device; 175 dev_priv->backlight_enabled = true; 176 return 0; 177 } 178 179 #endif 180 181 /* 182 * Provide the Cedarview specific chip logic and low level methods 183 * for power management 184 * 185 * FIXME: we need to implement the apm/ospm base management bits 186 * for this and the MID devices. 187 */ 188 189 static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset) 190 { 191 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 192 uint32_t ret_val = 0; 193 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 194 pci_write_config_dword(pci_root, 0xD0, mcr); 195 pci_read_config_dword(pci_root, 0xD4, &ret_val); 196 pci_dev_put(pci_root); 197 return ret_val; 198 } 199 200 static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset, 201 u32 value) 202 { 203 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 204 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 205 pci_write_config_dword(pci_root, 0xD4, value); 206 pci_write_config_dword(pci_root, 0xD0, mcr); 207 pci_dev_put(pci_root); 208 } 209 210 #define PSB_PM_SSC 0x20 211 #define PSB_PM_SSS 0x30 212 #define PSB_PWRGT_GFX_ON 0x02 213 #define PSB_PWRGT_GFX_OFF 0x01 214 #define PSB_PWRGT_GFX_D0 0x00 215 #define PSB_PWRGT_GFX_D3 0x03 216 217 static void cdv_init_pm(struct drm_device *dev) 218 { 219 struct drm_psb_private *dev_priv = dev->dev_private; 220 u32 pwr_cnt; 221 int domain = pci_domain_nr(dev->pdev->bus); 222 int i; 223 224 dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 225 PSB_APMBA) & 0xFFFF; 226 dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 227 PSB_OSPMBA) & 0xFFFF; 228 229 /* Power status */ 230 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 231 232 /* Enable the GPU */ 233 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 234 pwr_cnt |= PSB_PWRGT_GFX_ON; 235 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 236 237 /* Wait for the GPU power */ 238 for (i = 0; i < 5; i++) { 239 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 240 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0) 241 return; 242 udelay(10); 243 } 244 dev_err(dev->dev, "GPU: power management timed out.\n"); 245 } 246 247 static void cdv_errata(struct drm_device *dev) 248 { 249 /* Disable bonus launch. 250 * CPU and GPU competes for memory and display misses updates and 251 * flickers. Worst with dual core, dual displays. 252 * 253 * Fixes were done to Win 7 gfx driver to disable a feature called 254 * Bonus Launch to work around the issue, by degrading 255 * performance. 256 */ 257 CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108); 258 } 259 260 /** 261 * cdv_save_display_registers - save registers lost on suspend 262 * @dev: our DRM device 263 * 264 * Save the state we need in order to be able to restore the interface 265 * upon resume from suspend 266 */ 267 static int cdv_save_display_registers(struct drm_device *dev) 268 { 269 struct drm_psb_private *dev_priv = dev->dev_private; 270 struct psb_save_area *regs = &dev_priv->regs; 271 struct drm_connector *connector; 272 273 dev_dbg(dev->dev, "Saving GPU registers.\n"); 274 275 pci_read_config_byte(dev->pdev, 0xF4, ®s->cdv.saveLBB); 276 277 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); 278 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); 279 280 regs->cdv.saveDSPARB = REG_READ(DSPARB); 281 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); 282 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); 283 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); 284 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); 285 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); 286 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); 287 288 regs->cdv.saveADPA = REG_READ(ADPA); 289 290 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 291 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 292 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 293 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 294 regs->cdv.saveLVDS = REG_READ(LVDS); 295 296 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); 297 298 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); 299 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); 300 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); 301 302 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); 303 304 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); 305 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); 306 307 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 308 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); 309 310 return 0; 311 } 312 313 /** 314 * cdv_restore_display_registers - restore lost register state 315 * @dev: our DRM device 316 * 317 * Restore register state that was lost during suspend and resume. 318 * 319 * FIXME: review 320 */ 321 static int cdv_restore_display_registers(struct drm_device *dev) 322 { 323 struct drm_psb_private *dev_priv = dev->dev_private; 324 struct psb_save_area *regs = &dev_priv->regs; 325 struct drm_connector *connector; 326 u32 temp; 327 328 pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB); 329 330 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 331 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 332 333 /* BIOS does below anyway */ 334 REG_WRITE(DPIO_CFG, 0); 335 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 336 337 temp = REG_READ(DPLL_A); 338 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 339 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 340 REG_READ(DPLL_A); 341 } 342 343 temp = REG_READ(DPLL_B); 344 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 345 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 346 REG_READ(DPLL_B); 347 } 348 349 udelay(500); 350 351 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 352 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); 353 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); 354 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); 355 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); 356 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); 357 358 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); 359 REG_WRITE(ADPA, regs->cdv.saveADPA); 360 361 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); 362 REG_WRITE(LVDS, regs->cdv.saveLVDS); 363 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); 364 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); 365 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); 366 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); 367 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); 368 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); 369 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); 370 371 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); 372 373 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); 374 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); 375 376 /* Fix arbitration bug */ 377 cdv_errata(dev); 378 379 drm_mode_config_reset(dev); 380 381 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 382 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 383 384 /* Resume the modeset for every activated CRTC */ 385 drm_helper_resume_force_mode(dev); 386 return 0; 387 } 388 389 static int cdv_power_down(struct drm_device *dev) 390 { 391 struct drm_psb_private *dev_priv = dev->dev_private; 392 u32 pwr_cnt, pwr_mask, pwr_sts; 393 int tries = 5; 394 395 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 396 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 397 pwr_cnt |= PSB_PWRGT_GFX_OFF; 398 pwr_mask = PSB_PWRGT_GFX_MASK; 399 400 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 401 402 while (tries--) { 403 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 404 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3) 405 return 0; 406 udelay(10); 407 } 408 return 0; 409 } 410 411 static int cdv_power_up(struct drm_device *dev) 412 { 413 struct drm_psb_private *dev_priv = dev->dev_private; 414 u32 pwr_cnt, pwr_mask, pwr_sts; 415 int tries = 5; 416 417 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 418 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 419 pwr_cnt |= PSB_PWRGT_GFX_ON; 420 pwr_mask = PSB_PWRGT_GFX_MASK; 421 422 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 423 424 while (tries--) { 425 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 426 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0) 427 return 0; 428 udelay(10); 429 } 430 return 0; 431 } 432 433 static void cdv_hotplug_work_func(struct work_struct *work) 434 { 435 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, 436 hotplug_work); 437 struct drm_device *dev = dev_priv->dev; 438 439 /* Just fire off a uevent and let userspace tell us what to do */ 440 drm_helper_hpd_irq_event(dev); 441 } 442 443 /* The core driver has received a hotplug IRQ. We are in IRQ context 444 so extract the needed information and kick off queued processing */ 445 446 static int cdv_hotplug_event(struct drm_device *dev) 447 { 448 struct drm_psb_private *dev_priv = dev->dev_private; 449 schedule_work(&dev_priv->hotplug_work); 450 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 451 return 1; 452 } 453 454 static void cdv_hotplug_enable(struct drm_device *dev, bool on) 455 { 456 if (on) { 457 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); 458 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN | 459 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN; 460 REG_WRITE(PORT_HOTPLUG_EN, hotplug); 461 } else { 462 REG_WRITE(PORT_HOTPLUG_EN, 0); 463 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 464 } 465 } 466 467 static const char *force_audio_names[] = { 468 "off", 469 "auto", 470 "on", 471 }; 472 473 void cdv_intel_attach_force_audio_property(struct drm_connector *connector) 474 { 475 struct drm_device *dev = connector->dev; 476 struct drm_psb_private *dev_priv = dev->dev_private; 477 struct drm_property *prop; 478 int i; 479 480 prop = dev_priv->force_audio_property; 481 if (prop == NULL) { 482 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 483 "audio", 484 ARRAY_SIZE(force_audio_names)); 485 if (prop == NULL) 486 return; 487 488 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++) 489 drm_property_add_enum(prop, i-1, force_audio_names[i]); 490 491 dev_priv->force_audio_property = prop; 492 } 493 drm_object_attach_property(&connector->base, prop, 0); 494 } 495 496 497 static const char *broadcast_rgb_names[] = { 498 "Full", 499 "Limited 16:235", 500 }; 501 502 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector) 503 { 504 struct drm_device *dev = connector->dev; 505 struct drm_psb_private *dev_priv = dev->dev_private; 506 struct drm_property *prop; 507 int i; 508 509 prop = dev_priv->broadcast_rgb_property; 510 if (prop == NULL) { 511 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 512 "Broadcast RGB", 513 ARRAY_SIZE(broadcast_rgb_names)); 514 if (prop == NULL) 515 return; 516 517 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++) 518 drm_property_add_enum(prop, i, broadcast_rgb_names[i]); 519 520 dev_priv->broadcast_rgb_property = prop; 521 } 522 523 drm_object_attach_property(&connector->base, prop, 0); 524 } 525 526 /* Cedarview */ 527 static const struct psb_offset cdv_regmap[2] = { 528 { 529 .fp0 = FPA0, 530 .fp1 = FPA1, 531 .cntr = DSPACNTR, 532 .conf = PIPEACONF, 533 .src = PIPEASRC, 534 .dpll = DPLL_A, 535 .dpll_md = DPLL_A_MD, 536 .htotal = HTOTAL_A, 537 .hblank = HBLANK_A, 538 .hsync = HSYNC_A, 539 .vtotal = VTOTAL_A, 540 .vblank = VBLANK_A, 541 .vsync = VSYNC_A, 542 .stride = DSPASTRIDE, 543 .size = DSPASIZE, 544 .pos = DSPAPOS, 545 .base = DSPABASE, 546 .surf = DSPASURF, 547 .addr = DSPABASE, 548 .status = PIPEASTAT, 549 .linoff = DSPALINOFF, 550 .tileoff = DSPATILEOFF, 551 .palette = PALETTE_A, 552 }, 553 { 554 .fp0 = FPB0, 555 .fp1 = FPB1, 556 .cntr = DSPBCNTR, 557 .conf = PIPEBCONF, 558 .src = PIPEBSRC, 559 .dpll = DPLL_B, 560 .dpll_md = DPLL_B_MD, 561 .htotal = HTOTAL_B, 562 .hblank = HBLANK_B, 563 .hsync = HSYNC_B, 564 .vtotal = VTOTAL_B, 565 .vblank = VBLANK_B, 566 .vsync = VSYNC_B, 567 .stride = DSPBSTRIDE, 568 .size = DSPBSIZE, 569 .pos = DSPBPOS, 570 .base = DSPBBASE, 571 .surf = DSPBSURF, 572 .addr = DSPBBASE, 573 .status = PIPEBSTAT, 574 .linoff = DSPBLINOFF, 575 .tileoff = DSPBTILEOFF, 576 .palette = PALETTE_B, 577 } 578 }; 579 580 static int cdv_chip_setup(struct drm_device *dev) 581 { 582 struct drm_psb_private *dev_priv = dev->dev_private; 583 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 584 585 if (pci_enable_msi(dev->pdev)) 586 dev_warn(dev->dev, "Enabling MSI failed!\n"); 587 dev_priv->regmap = cdv_regmap; 588 gma_get_core_freq(dev); 589 psb_intel_opregion_init(dev); 590 psb_intel_init_bios(dev); 591 cdv_hotplug_enable(dev, false); 592 return 0; 593 } 594 595 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ 596 597 const struct psb_ops cdv_chip_ops = { 598 .name = "GMA3600/3650", 599 .accel_2d = 0, 600 .pipes = 2, 601 .crtcs = 2, 602 .hdmi_mask = (1 << 0) | (1 << 1), 603 .lvds_mask = (1 << 1), 604 .sdvo_mask = (1 << 0), 605 .cursor_needs_phys = 0, 606 .sgx_offset = MRST_SGX_OFFSET, 607 .chip_setup = cdv_chip_setup, 608 .errata = cdv_errata, 609 610 .crtc_helper = &cdv_intel_helper_funcs, 611 .crtc_funcs = &cdv_intel_crtc_funcs, 612 .clock_funcs = &cdv_clock_funcs, 613 614 .output_init = cdv_output_init, 615 .hotplug = cdv_hotplug_event, 616 .hotplug_enable = cdv_hotplug_enable, 617 618 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 619 .backlight_init = cdv_backlight_init, 620 #endif 621 622 .init_pm = cdv_init_pm, 623 .save_regs = cdv_save_display_registers, 624 .restore_regs = cdv_restore_display_registers, 625 .save_crtc = gma_crtc_save, 626 .restore_crtc = gma_crtc_restore, 627 .power_down = cdv_power_down, 628 .power_up = cdv_power_up, 629 .update_wm = cdv_update_wm, 630 .disable_sr = cdv_disable_sr, 631 }; 632