1 /************************************************************************** 2 * Copyright (c) 2011, Intel Corporation. 3 * All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 **************************************************************************/ 19 20 #include <linux/backlight.h> 21 #include <drm/drmP.h> 22 #include <drm/drm.h> 23 #include "gma_drm.h" 24 #include "psb_drv.h" 25 #include "psb_reg.h" 26 #include "psb_intel_reg.h" 27 #include "intel_bios.h" 28 #include "cdv_device.h" 29 30 #define VGA_SR_INDEX 0x3c4 31 #define VGA_SR_DATA 0x3c5 32 33 static void cdv_disable_vga(struct drm_device *dev) 34 { 35 u8 sr1; 36 u32 vga_reg; 37 38 vga_reg = VGACNTRL; 39 40 outb(1, VGA_SR_INDEX); 41 sr1 = inb(VGA_SR_DATA); 42 outb(sr1 | 1<<5, VGA_SR_DATA); 43 udelay(300); 44 45 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 46 REG_READ(vga_reg); 47 } 48 49 static int cdv_output_init(struct drm_device *dev) 50 { 51 struct drm_psb_private *dev_priv = dev->dev_private; 52 53 drm_mode_create_scaling_mode_property(dev); 54 55 cdv_disable_vga(dev); 56 57 cdv_intel_crt_init(dev, &dev_priv->mode_dev); 58 cdv_intel_lvds_init(dev, &dev_priv->mode_dev); 59 60 /* These bits indicate HDMI not SDVO on CDV */ 61 if (REG_READ(SDVOB) & SDVO_DETECTED) 62 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); 63 if (REG_READ(SDVOC) & SDVO_DETECTED) 64 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); 65 return 0; 66 } 67 68 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 69 70 /* 71 * Cedartrail Backlght Interfaces 72 */ 73 74 static struct backlight_device *cdv_backlight_device; 75 76 static int cdv_backlight_combination_mode(struct drm_device *dev) 77 { 78 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 79 } 80 81 static int cdv_get_brightness(struct backlight_device *bd) 82 { 83 struct drm_device *dev = bl_get_data(bd); 84 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 85 86 if (cdv_backlight_combination_mode(dev)) { 87 u8 lbpc; 88 89 val &= ~1; 90 pci_read_config_byte(dev->pdev, 0xF4, &lbpc); 91 val *= lbpc; 92 } 93 return val; 94 } 95 96 static u32 cdv_get_max_backlight(struct drm_device *dev) 97 { 98 u32 max = REG_READ(BLC_PWM_CTL); 99 100 if (max == 0) { 101 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); 102 /* i915 does this, I believe which means that we should not 103 * smash PWM control as firmware will take control of it. */ 104 return 1; 105 } 106 107 max >>= 16; 108 if (cdv_backlight_combination_mode(dev)) 109 max *= 0xff; 110 return max; 111 } 112 113 static int cdv_set_brightness(struct backlight_device *bd) 114 { 115 struct drm_device *dev = bl_get_data(bd); 116 int level = bd->props.brightness; 117 u32 blc_pwm_ctl; 118 119 /* Percentage 1-100% being valid */ 120 if (level < 1) 121 level = 1; 122 123 if (cdv_backlight_combination_mode(dev)) { 124 u32 max = cdv_get_max_backlight(dev); 125 u8 lbpc; 126 127 lbpc = level * 0xfe / max + 1; 128 level /= lbpc; 129 130 pci_write_config_byte(dev->pdev, 0xF4, lbpc); 131 } 132 133 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 134 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 135 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 136 return 0; 137 } 138 139 static const struct backlight_ops cdv_ops = { 140 .get_brightness = cdv_get_brightness, 141 .update_status = cdv_set_brightness, 142 }; 143 144 static int cdv_backlight_init(struct drm_device *dev) 145 { 146 struct drm_psb_private *dev_priv = dev->dev_private; 147 struct backlight_properties props; 148 149 memset(&props, 0, sizeof(struct backlight_properties)); 150 props.max_brightness = 100; 151 props.type = BACKLIGHT_PLATFORM; 152 153 cdv_backlight_device = backlight_device_register("psb-bl", 154 NULL, (void *)dev, &cdv_ops, &props); 155 if (IS_ERR(cdv_backlight_device)) 156 return PTR_ERR(cdv_backlight_device); 157 158 cdv_backlight_device->props.brightness = 159 cdv_get_brightness(cdv_backlight_device); 160 cdv_backlight_device->props.max_brightness = cdv_get_max_backlight(dev); 161 backlight_update_status(cdv_backlight_device); 162 dev_priv->backlight_device = cdv_backlight_device; 163 return 0; 164 } 165 166 #endif 167 168 /* 169 * Provide the Cedarview specific chip logic and low level methods 170 * for power management 171 * 172 * FIXME: we need to implement the apm/ospm base management bits 173 * for this and the MID devices. 174 */ 175 176 static inline u32 CDV_MSG_READ32(uint port, uint offset) 177 { 178 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 179 uint32_t ret_val = 0; 180 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 181 pci_write_config_dword(pci_root, 0xD0, mcr); 182 pci_read_config_dword(pci_root, 0xD4, &ret_val); 183 pci_dev_put(pci_root); 184 return ret_val; 185 } 186 187 static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value) 188 { 189 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 190 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 191 pci_write_config_dword(pci_root, 0xD4, value); 192 pci_write_config_dword(pci_root, 0xD0, mcr); 193 pci_dev_put(pci_root); 194 } 195 196 #define PSB_PM_SSC 0x20 197 #define PSB_PM_SSS 0x30 198 #define PSB_PWRGT_GFX_ON 0x02 199 #define PSB_PWRGT_GFX_OFF 0x01 200 #define PSB_PWRGT_GFX_D0 0x00 201 #define PSB_PWRGT_GFX_D3 0x03 202 203 static void cdv_init_pm(struct drm_device *dev) 204 { 205 struct drm_psb_private *dev_priv = dev->dev_private; 206 u32 pwr_cnt; 207 int i; 208 209 dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT, 210 PSB_APMBA) & 0xFFFF; 211 dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT, 212 PSB_OSPMBA) & 0xFFFF; 213 214 /* Power status */ 215 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 216 217 /* Enable the GPU */ 218 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 219 pwr_cnt |= PSB_PWRGT_GFX_ON; 220 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 221 222 /* Wait for the GPU power */ 223 for (i = 0; i < 5; i++) { 224 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 225 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0) 226 return; 227 udelay(10); 228 } 229 dev_err(dev->dev, "GPU: power management timed out.\n"); 230 } 231 232 static void cdv_errata(struct drm_device *dev) 233 { 234 /* Disable bonus launch. 235 * CPU and GPU competes for memory and display misses updates and 236 * flickers. Worst with dual core, dual displays. 237 * 238 * Fixes were done to Win 7 gfx driver to disable a feature called 239 * Bonus Launch to work around the issue, by degrading 240 * performance. 241 */ 242 CDV_MSG_WRITE32(3, 0x30, 0x08027108); 243 } 244 245 /** 246 * cdv_save_display_registers - save registers lost on suspend 247 * @dev: our DRM device 248 * 249 * Save the state we need in order to be able to restore the interface 250 * upon resume from suspend 251 */ 252 static int cdv_save_display_registers(struct drm_device *dev) 253 { 254 struct drm_psb_private *dev_priv = dev->dev_private; 255 struct psb_save_area *regs = &dev_priv->regs; 256 struct drm_connector *connector; 257 258 dev_dbg(dev->dev, "Saving GPU registers.\n"); 259 260 pci_read_config_byte(dev->pdev, 0xF4, ®s->cdv.saveLBB); 261 262 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); 263 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); 264 265 regs->cdv.saveDSPARB = REG_READ(DSPARB); 266 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); 267 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); 268 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); 269 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); 270 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); 271 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); 272 273 regs->cdv.saveADPA = REG_READ(ADPA); 274 275 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 276 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 277 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 278 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 279 regs->cdv.saveLVDS = REG_READ(LVDS); 280 281 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); 282 283 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); 284 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); 285 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); 286 287 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); 288 289 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); 290 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); 291 292 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 293 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); 294 295 return 0; 296 } 297 298 /** 299 * cdv_restore_display_registers - restore lost register state 300 * @dev: our DRM device 301 * 302 * Restore register state that was lost during suspend and resume. 303 * 304 * FIXME: review 305 */ 306 static int cdv_restore_display_registers(struct drm_device *dev) 307 { 308 struct drm_psb_private *dev_priv = dev->dev_private; 309 struct psb_save_area *regs = &dev_priv->regs; 310 struct drm_connector *connector; 311 u32 temp; 312 313 pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB); 314 315 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 316 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 317 318 /* BIOS does below anyway */ 319 REG_WRITE(DPIO_CFG, 0); 320 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 321 322 temp = REG_READ(DPLL_A); 323 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 324 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 325 REG_READ(DPLL_A); 326 } 327 328 temp = REG_READ(DPLL_B); 329 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 330 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 331 REG_READ(DPLL_B); 332 } 333 334 udelay(500); 335 336 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 337 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); 338 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); 339 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); 340 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); 341 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); 342 343 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); 344 REG_WRITE(ADPA, regs->cdv.saveADPA); 345 346 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); 347 REG_WRITE(LVDS, regs->cdv.saveLVDS); 348 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); 349 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); 350 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); 351 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); 352 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); 353 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); 354 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); 355 356 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); 357 358 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); 359 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); 360 361 /* Fix arbitration bug */ 362 cdv_errata(dev); 363 364 drm_mode_config_reset(dev); 365 366 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 367 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 368 369 /* Resume the modeset for every activated CRTC */ 370 drm_helper_resume_force_mode(dev); 371 return 0; 372 } 373 374 static int cdv_power_down(struct drm_device *dev) 375 { 376 struct drm_psb_private *dev_priv = dev->dev_private; 377 u32 pwr_cnt, pwr_mask, pwr_sts; 378 int tries = 5; 379 380 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 381 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 382 pwr_cnt |= PSB_PWRGT_GFX_OFF; 383 pwr_mask = PSB_PWRGT_GFX_MASK; 384 385 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 386 387 while (tries--) { 388 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 389 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3) 390 return 0; 391 udelay(10); 392 } 393 return 0; 394 } 395 396 static int cdv_power_up(struct drm_device *dev) 397 { 398 struct drm_psb_private *dev_priv = dev->dev_private; 399 u32 pwr_cnt, pwr_mask, pwr_sts; 400 int tries = 5; 401 402 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 403 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 404 pwr_cnt |= PSB_PWRGT_GFX_ON; 405 pwr_mask = PSB_PWRGT_GFX_MASK; 406 407 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 408 409 while (tries--) { 410 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 411 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0) 412 return 0; 413 udelay(10); 414 } 415 return 0; 416 } 417 418 /* FIXME ? - shared with Poulsbo */ 419 static void cdv_get_core_freq(struct drm_device *dev) 420 { 421 uint32_t clock; 422 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); 423 struct drm_psb_private *dev_priv = dev->dev_private; 424 425 pci_write_config_dword(pci_root, 0xD0, 0xD0050300); 426 pci_read_config_dword(pci_root, 0xD4, &clock); 427 pci_dev_put(pci_root); 428 429 switch (clock & 0x07) { 430 case 0: 431 dev_priv->core_freq = 100; 432 break; 433 case 1: 434 dev_priv->core_freq = 133; 435 break; 436 case 2: 437 dev_priv->core_freq = 150; 438 break; 439 case 3: 440 dev_priv->core_freq = 178; 441 break; 442 case 4: 443 dev_priv->core_freq = 200; 444 break; 445 case 5: 446 case 6: 447 case 7: 448 dev_priv->core_freq = 266; 449 default: 450 dev_priv->core_freq = 0; 451 } 452 } 453 454 static void cdv_hotplug_work_func(struct work_struct *work) 455 { 456 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, 457 hotplug_work); 458 struct drm_device *dev = dev_priv->dev; 459 460 /* Just fire off a uevent and let userspace tell us what to do */ 461 drm_helper_hpd_irq_event(dev); 462 } 463 464 /* The core driver has received a hotplug IRQ. We are in IRQ context 465 so extract the needed information and kick off queued processing */ 466 467 static int cdv_hotplug_event(struct drm_device *dev) 468 { 469 struct drm_psb_private *dev_priv = dev->dev_private; 470 schedule_work(&dev_priv->hotplug_work); 471 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 472 return 1; 473 } 474 475 static void cdv_hotplug_enable(struct drm_device *dev, bool on) 476 { 477 if (on) { 478 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); 479 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN | 480 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN; 481 REG_WRITE(PORT_HOTPLUG_EN, hotplug); 482 } else { 483 REG_WRITE(PORT_HOTPLUG_EN, 0); 484 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 485 } 486 } 487 488 /* Cedarview */ 489 static const struct psb_offset cdv_regmap[2] = { 490 { 491 .fp0 = FPA0, 492 .fp1 = FPA1, 493 .cntr = DSPACNTR, 494 .conf = PIPEACONF, 495 .src = PIPEASRC, 496 .dpll = DPLL_A, 497 .dpll_md = DPLL_A_MD, 498 .htotal = HTOTAL_A, 499 .hblank = HBLANK_A, 500 .hsync = HSYNC_A, 501 .vtotal = VTOTAL_A, 502 .vblank = VBLANK_A, 503 .vsync = VSYNC_A, 504 .stride = DSPASTRIDE, 505 .size = DSPASIZE, 506 .pos = DSPAPOS, 507 .base = DSPABASE, 508 .surf = DSPASURF, 509 .addr = DSPABASE, 510 .status = PIPEASTAT, 511 .linoff = DSPALINOFF, 512 .tileoff = DSPATILEOFF, 513 .palette = PALETTE_A, 514 }, 515 { 516 .fp0 = FPB0, 517 .fp1 = FPB1, 518 .cntr = DSPBCNTR, 519 .conf = PIPEBCONF, 520 .src = PIPEBSRC, 521 .dpll = DPLL_B, 522 .dpll_md = DPLL_B_MD, 523 .htotal = HTOTAL_B, 524 .hblank = HBLANK_B, 525 .hsync = HSYNC_B, 526 .vtotal = VTOTAL_B, 527 .vblank = VBLANK_B, 528 .vsync = VSYNC_B, 529 .stride = DSPBSTRIDE, 530 .size = DSPBSIZE, 531 .pos = DSPBPOS, 532 .base = DSPBBASE, 533 .surf = DSPBSURF, 534 .addr = DSPBBASE, 535 .status = PIPEBSTAT, 536 .linoff = DSPBLINOFF, 537 .tileoff = DSPBTILEOFF, 538 .palette = PALETTE_B, 539 } 540 }; 541 542 static int cdv_chip_setup(struct drm_device *dev) 543 { 544 struct drm_psb_private *dev_priv = dev->dev_private; 545 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 546 547 if (pci_enable_msi(dev->pdev)) 548 dev_warn(dev->dev, "Enabling MSI failed!\n"); 549 dev_priv->regmap = cdv_regmap; 550 cdv_get_core_freq(dev); 551 psb_intel_opregion_init(dev); 552 psb_intel_init_bios(dev); 553 cdv_hotplug_enable(dev, false); 554 return 0; 555 } 556 557 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ 558 559 const struct psb_ops cdv_chip_ops = { 560 .name = "GMA3600/3650", 561 .accel_2d = 0, 562 .pipes = 2, 563 .crtcs = 2, 564 .hdmi_mask = (1 << 0) | (1 << 1), 565 .lvds_mask = (1 << 1), 566 .cursor_needs_phys = 0, 567 .sgx_offset = MRST_SGX_OFFSET, 568 .chip_setup = cdv_chip_setup, 569 .errata = cdv_errata, 570 571 .crtc_helper = &cdv_intel_helper_funcs, 572 .crtc_funcs = &cdv_intel_crtc_funcs, 573 574 .output_init = cdv_output_init, 575 .hotplug = cdv_hotplug_event, 576 .hotplug_enable = cdv_hotplug_enable, 577 578 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 579 .backlight_init = cdv_backlight_init, 580 #endif 581 582 .init_pm = cdv_init_pm, 583 .save_regs = cdv_save_display_registers, 584 .restore_regs = cdv_restore_display_registers, 585 .power_down = cdv_power_down, 586 .power_up = cdv_power_up, 587 }; 588