1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 #include <linux/delay.h> 9 10 #include <drm/drm.h> 11 12 #include "cdv_device.h" 13 #include "gma_device.h" 14 #include "intel_bios.h" 15 #include "psb_drv.h" 16 #include "psb_intel_reg.h" 17 #include "psb_reg.h" 18 19 #define VGA_SR_INDEX 0x3c4 20 #define VGA_SR_DATA 0x3c5 21 22 static void cdv_disable_vga(struct drm_device *dev) 23 { 24 u8 sr1; 25 u32 vga_reg; 26 27 vga_reg = VGACNTRL; 28 29 outb(1, VGA_SR_INDEX); 30 sr1 = inb(VGA_SR_DATA); 31 outb(sr1 | 1<<5, VGA_SR_DATA); 32 udelay(300); 33 34 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 35 REG_READ(vga_reg); 36 } 37 38 static int cdv_output_init(struct drm_device *dev) 39 { 40 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 41 42 drm_mode_create_scaling_mode_property(dev); 43 44 cdv_disable_vga(dev); 45 46 cdv_intel_crt_init(dev, &dev_priv->mode_dev); 47 cdv_intel_lvds_init(dev, &dev_priv->mode_dev); 48 49 /* These bits indicate HDMI not SDVO on CDV */ 50 if (REG_READ(SDVOB) & SDVO_DETECTED) { 51 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); 52 if (REG_READ(DP_B) & DP_DETECTED) 53 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B); 54 } 55 56 if (REG_READ(SDVOC) & SDVO_DETECTED) { 57 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); 58 if (REG_READ(DP_C) & DP_DETECTED) 59 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C); 60 } 61 return 0; 62 } 63 64 /* 65 * Cedartrail Backlght Interfaces 66 */ 67 68 static int cdv_backlight_combination_mode(struct drm_device *dev) 69 { 70 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 71 } 72 73 static u32 cdv_get_max_backlight(struct drm_device *dev) 74 { 75 u32 max = REG_READ(BLC_PWM_CTL); 76 77 if (max == 0) { 78 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); 79 /* i915 does this, I believe which means that we should not 80 * smash PWM control as firmware will take control of it. */ 81 return 1; 82 } 83 84 max >>= 16; 85 if (cdv_backlight_combination_mode(dev)) 86 max *= 0xff; 87 return max; 88 } 89 90 static int cdv_get_brightness(struct drm_device *dev) 91 { 92 struct pci_dev *pdev = to_pci_dev(dev->dev); 93 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 94 95 if (cdv_backlight_combination_mode(dev)) { 96 u8 lbpc; 97 98 val &= ~1; 99 pci_read_config_byte(pdev, 0xF4, &lbpc); 100 val *= lbpc; 101 } 102 return (val * 100)/cdv_get_max_backlight(dev); 103 } 104 105 static void cdv_set_brightness(struct drm_device *dev, int level) 106 { 107 struct pci_dev *pdev = to_pci_dev(dev->dev); 108 u32 blc_pwm_ctl; 109 110 level *= cdv_get_max_backlight(dev); 111 level /= 100; 112 113 if (cdv_backlight_combination_mode(dev)) { 114 u32 max = cdv_get_max_backlight(dev); 115 u8 lbpc; 116 117 lbpc = level * 0xfe / max + 1; 118 level /= lbpc; 119 120 pci_write_config_byte(pdev, 0xF4, lbpc); 121 } 122 123 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 124 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 125 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 126 } 127 128 static int cdv_backlight_init(struct drm_device *dev) 129 { 130 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 131 132 dev_priv->backlight_level = cdv_get_brightness(dev); 133 cdv_set_brightness(dev, dev_priv->backlight_level); 134 135 return 0; 136 } 137 138 /* 139 * Provide the Cedarview specific chip logic and low level methods 140 * for power management 141 * 142 * FIXME: we need to implement the apm/ospm base management bits 143 * for this and the MID devices. 144 */ 145 146 static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset) 147 { 148 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 149 uint32_t ret_val = 0; 150 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 151 pci_write_config_dword(pci_root, 0xD0, mcr); 152 pci_read_config_dword(pci_root, 0xD4, &ret_val); 153 pci_dev_put(pci_root); 154 return ret_val; 155 } 156 157 static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset, 158 u32 value) 159 { 160 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 161 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 162 pci_write_config_dword(pci_root, 0xD4, value); 163 pci_write_config_dword(pci_root, 0xD0, mcr); 164 pci_dev_put(pci_root); 165 } 166 167 #define PSB_PM_SSC 0x20 168 #define PSB_PM_SSS 0x30 169 #define PSB_PWRGT_GFX_ON 0x02 170 #define PSB_PWRGT_GFX_OFF 0x01 171 #define PSB_PWRGT_GFX_D0 0x00 172 #define PSB_PWRGT_GFX_D3 0x03 173 174 static void cdv_init_pm(struct drm_device *dev) 175 { 176 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 177 struct pci_dev *pdev = to_pci_dev(dev->dev); 178 u32 pwr_cnt; 179 int domain = pci_domain_nr(pdev->bus); 180 int i; 181 182 dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 183 PSB_APMBA) & 0xFFFF; 184 dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 185 PSB_OSPMBA) & 0xFFFF; 186 187 /* Power status */ 188 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 189 190 /* Enable the GPU */ 191 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 192 pwr_cnt |= PSB_PWRGT_GFX_ON; 193 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 194 195 /* Wait for the GPU power */ 196 for (i = 0; i < 5; i++) { 197 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 198 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0) 199 return; 200 udelay(10); 201 } 202 dev_err(dev->dev, "GPU: power management timed out.\n"); 203 } 204 205 static void cdv_errata(struct drm_device *dev) 206 { 207 struct pci_dev *pdev = to_pci_dev(dev->dev); 208 209 /* Disable bonus launch. 210 * CPU and GPU competes for memory and display misses updates and 211 * flickers. Worst with dual core, dual displays. 212 * 213 * Fixes were done to Win 7 gfx driver to disable a feature called 214 * Bonus Launch to work around the issue, by degrading 215 * performance. 216 */ 217 CDV_MSG_WRITE32(pci_domain_nr(pdev->bus), 3, 0x30, 0x08027108); 218 } 219 220 /** 221 * cdv_save_display_registers - save registers lost on suspend 222 * @dev: our DRM device 223 * 224 * Save the state we need in order to be able to restore the interface 225 * upon resume from suspend 226 */ 227 static int cdv_save_display_registers(struct drm_device *dev) 228 { 229 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 230 struct pci_dev *pdev = to_pci_dev(dev->dev); 231 struct psb_save_area *regs = &dev_priv->regs; 232 struct drm_connector_list_iter conn_iter; 233 struct drm_connector *connector; 234 235 dev_dbg(dev->dev, "Saving GPU registers.\n"); 236 237 pci_read_config_byte(pdev, 0xF4, ®s->cdv.saveLBB); 238 239 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); 240 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); 241 242 regs->cdv.saveDSPARB = REG_READ(DSPARB); 243 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); 244 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); 245 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); 246 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); 247 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); 248 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); 249 250 regs->cdv.saveADPA = REG_READ(ADPA); 251 252 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 253 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 254 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 255 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 256 regs->cdv.saveLVDS = REG_READ(LVDS); 257 258 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); 259 260 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); 261 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); 262 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); 263 264 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); 265 266 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); 267 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); 268 269 drm_connector_list_iter_begin(dev, &conn_iter); 270 drm_for_each_connector_iter(connector, &conn_iter) 271 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); 272 drm_connector_list_iter_end(&conn_iter); 273 274 return 0; 275 } 276 277 /** 278 * cdv_restore_display_registers - restore lost register state 279 * @dev: our DRM device 280 * 281 * Restore register state that was lost during suspend and resume. 282 * 283 * FIXME: review 284 */ 285 static int cdv_restore_display_registers(struct drm_device *dev) 286 { 287 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 288 struct pci_dev *pdev = to_pci_dev(dev->dev); 289 struct psb_save_area *regs = &dev_priv->regs; 290 struct drm_connector_list_iter conn_iter; 291 struct drm_connector *connector; 292 u32 temp; 293 294 pci_write_config_byte(pdev, 0xF4, regs->cdv.saveLBB); 295 296 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 297 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 298 299 /* BIOS does below anyway */ 300 REG_WRITE(DPIO_CFG, 0); 301 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 302 303 temp = REG_READ(DPLL_A); 304 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 305 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 306 REG_READ(DPLL_A); 307 } 308 309 temp = REG_READ(DPLL_B); 310 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 311 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 312 REG_READ(DPLL_B); 313 } 314 315 udelay(500); 316 317 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 318 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); 319 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); 320 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); 321 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); 322 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); 323 324 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); 325 REG_WRITE(ADPA, regs->cdv.saveADPA); 326 327 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); 328 REG_WRITE(LVDS, regs->cdv.saveLVDS); 329 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); 330 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); 331 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); 332 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); 333 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); 334 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); 335 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); 336 337 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); 338 339 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); 340 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); 341 342 /* Fix arbitration bug */ 343 cdv_errata(dev); 344 345 drm_mode_config_reset(dev); 346 347 drm_connector_list_iter_begin(dev, &conn_iter); 348 drm_for_each_connector_iter(connector, &conn_iter) 349 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 350 drm_connector_list_iter_end(&conn_iter); 351 352 /* Resume the modeset for every activated CRTC */ 353 drm_helper_resume_force_mode(dev); 354 return 0; 355 } 356 357 static int cdv_power_down(struct drm_device *dev) 358 { 359 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 360 u32 pwr_cnt, pwr_mask, pwr_sts; 361 int tries = 5; 362 363 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 364 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 365 pwr_cnt |= PSB_PWRGT_GFX_OFF; 366 pwr_mask = PSB_PWRGT_GFX_MASK; 367 368 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 369 370 while (tries--) { 371 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 372 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3) 373 return 0; 374 udelay(10); 375 } 376 return 0; 377 } 378 379 static int cdv_power_up(struct drm_device *dev) 380 { 381 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 382 u32 pwr_cnt, pwr_mask, pwr_sts; 383 int tries = 5; 384 385 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 386 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 387 pwr_cnt |= PSB_PWRGT_GFX_ON; 388 pwr_mask = PSB_PWRGT_GFX_MASK; 389 390 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 391 392 while (tries--) { 393 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 394 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0) 395 return 0; 396 udelay(10); 397 } 398 return 0; 399 } 400 401 static void cdv_hotplug_work_func(struct work_struct *work) 402 { 403 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, 404 hotplug_work); 405 struct drm_device *dev = &dev_priv->dev; 406 407 /* Just fire off a uevent and let userspace tell us what to do */ 408 drm_helper_hpd_irq_event(dev); 409 } 410 411 /* The core driver has received a hotplug IRQ. We are in IRQ context 412 so extract the needed information and kick off queued processing */ 413 414 static int cdv_hotplug_event(struct drm_device *dev) 415 { 416 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 417 schedule_work(&dev_priv->hotplug_work); 418 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 419 return 1; 420 } 421 422 static void cdv_hotplug_enable(struct drm_device *dev, bool on) 423 { 424 if (on) { 425 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); 426 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN | 427 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN; 428 REG_WRITE(PORT_HOTPLUG_EN, hotplug); 429 } else { 430 REG_WRITE(PORT_HOTPLUG_EN, 0); 431 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 432 } 433 } 434 435 static const char *force_audio_names[] = { 436 "off", 437 "auto", 438 "on", 439 }; 440 441 void cdv_intel_attach_force_audio_property(struct drm_connector *connector) 442 { 443 struct drm_device *dev = connector->dev; 444 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 445 struct drm_property *prop; 446 int i; 447 448 prop = dev_priv->force_audio_property; 449 if (prop == NULL) { 450 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 451 "audio", 452 ARRAY_SIZE(force_audio_names)); 453 if (prop == NULL) 454 return; 455 456 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++) 457 drm_property_add_enum(prop, i-1, force_audio_names[i]); 458 459 dev_priv->force_audio_property = prop; 460 } 461 drm_object_attach_property(&connector->base, prop, 0); 462 } 463 464 465 static const char *broadcast_rgb_names[] = { 466 "Full", 467 "Limited 16:235", 468 }; 469 470 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector) 471 { 472 struct drm_device *dev = connector->dev; 473 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 474 struct drm_property *prop; 475 int i; 476 477 prop = dev_priv->broadcast_rgb_property; 478 if (prop == NULL) { 479 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 480 "Broadcast RGB", 481 ARRAY_SIZE(broadcast_rgb_names)); 482 if (prop == NULL) 483 return; 484 485 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++) 486 drm_property_add_enum(prop, i, broadcast_rgb_names[i]); 487 488 dev_priv->broadcast_rgb_property = prop; 489 } 490 491 drm_object_attach_property(&connector->base, prop, 0); 492 } 493 494 /* Cedarview */ 495 static const struct psb_offset cdv_regmap[2] = { 496 { 497 .fp0 = FPA0, 498 .fp1 = FPA1, 499 .cntr = DSPACNTR, 500 .conf = PIPEACONF, 501 .src = PIPEASRC, 502 .dpll = DPLL_A, 503 .dpll_md = DPLL_A_MD, 504 .htotal = HTOTAL_A, 505 .hblank = HBLANK_A, 506 .hsync = HSYNC_A, 507 .vtotal = VTOTAL_A, 508 .vblank = VBLANK_A, 509 .vsync = VSYNC_A, 510 .stride = DSPASTRIDE, 511 .size = DSPASIZE, 512 .pos = DSPAPOS, 513 .base = DSPABASE, 514 .surf = DSPASURF, 515 .addr = DSPABASE, 516 .status = PIPEASTAT, 517 .linoff = DSPALINOFF, 518 .tileoff = DSPATILEOFF, 519 .palette = PALETTE_A, 520 }, 521 { 522 .fp0 = FPB0, 523 .fp1 = FPB1, 524 .cntr = DSPBCNTR, 525 .conf = PIPEBCONF, 526 .src = PIPEBSRC, 527 .dpll = DPLL_B, 528 .dpll_md = DPLL_B_MD, 529 .htotal = HTOTAL_B, 530 .hblank = HBLANK_B, 531 .hsync = HSYNC_B, 532 .vtotal = VTOTAL_B, 533 .vblank = VBLANK_B, 534 .vsync = VSYNC_B, 535 .stride = DSPBSTRIDE, 536 .size = DSPBSIZE, 537 .pos = DSPBPOS, 538 .base = DSPBBASE, 539 .surf = DSPBSURF, 540 .addr = DSPBBASE, 541 .status = PIPEBSTAT, 542 .linoff = DSPBLINOFF, 543 .tileoff = DSPBTILEOFF, 544 .palette = PALETTE_B, 545 } 546 }; 547 548 static int cdv_chip_setup(struct drm_device *dev) 549 { 550 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); 551 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 552 553 dev_priv->use_msi = true; 554 dev_priv->regmap = cdv_regmap; 555 gma_get_core_freq(dev); 556 psb_intel_opregion_init(dev); 557 psb_intel_init_bios(dev); 558 cdv_hotplug_enable(dev, false); 559 return 0; 560 } 561 562 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ 563 564 const struct psb_ops cdv_chip_ops = { 565 .name = "GMA3600/3650", 566 .pipes = 2, 567 .crtcs = 2, 568 .hdmi_mask = (1 << 0) | (1 << 1), 569 .lvds_mask = (1 << 1), 570 .sdvo_mask = (1 << 0), 571 .cursor_needs_phys = 0, 572 .sgx_offset = MRST_SGX_OFFSET, 573 .chip_setup = cdv_chip_setup, 574 .errata = cdv_errata, 575 576 .crtc_helper = &cdv_intel_helper_funcs, 577 .clock_funcs = &cdv_clock_funcs, 578 579 .output_init = cdv_output_init, 580 .hotplug = cdv_hotplug_event, 581 .hotplug_enable = cdv_hotplug_enable, 582 583 .backlight_init = cdv_backlight_init, 584 .backlight_get = cdv_get_brightness, 585 .backlight_set = cdv_set_brightness, 586 .backlight_name = "psb-bl", 587 588 .init_pm = cdv_init_pm, 589 .save_regs = cdv_save_display_registers, 590 .restore_regs = cdv_restore_display_registers, 591 .save_crtc = gma_crtc_save, 592 .restore_crtc = gma_crtc_restore, 593 .power_down = cdv_power_down, 594 .power_up = cdv_power_up, 595 .update_wm = cdv_update_wm, 596 .disable_sr = cdv_disable_sr, 597 }; 598