1 // SPDX-License-Identifier: GPL-2.0-only 2 /************************************************************************** 3 * Copyright (c) 2011, Intel Corporation. 4 * All Rights Reserved. 5 * 6 **************************************************************************/ 7 8 #include <linux/backlight.h> 9 #include <drm/drmP.h> 10 #include <drm/drm.h> 11 #include <drm/gma_drm.h> 12 #include "psb_drv.h" 13 #include "psb_reg.h" 14 #include "psb_intel_reg.h" 15 #include "intel_bios.h" 16 #include "cdv_device.h" 17 #include "gma_device.h" 18 19 #define VGA_SR_INDEX 0x3c4 20 #define VGA_SR_DATA 0x3c5 21 22 static void cdv_disable_vga(struct drm_device *dev) 23 { 24 u8 sr1; 25 u32 vga_reg; 26 27 vga_reg = VGACNTRL; 28 29 outb(1, VGA_SR_INDEX); 30 sr1 = inb(VGA_SR_DATA); 31 outb(sr1 | 1<<5, VGA_SR_DATA); 32 udelay(300); 33 34 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 35 REG_READ(vga_reg); 36 } 37 38 static int cdv_output_init(struct drm_device *dev) 39 { 40 struct drm_psb_private *dev_priv = dev->dev_private; 41 42 drm_mode_create_scaling_mode_property(dev); 43 44 cdv_disable_vga(dev); 45 46 cdv_intel_crt_init(dev, &dev_priv->mode_dev); 47 cdv_intel_lvds_init(dev, &dev_priv->mode_dev); 48 49 /* These bits indicate HDMI not SDVO on CDV */ 50 if (REG_READ(SDVOB) & SDVO_DETECTED) { 51 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB); 52 if (REG_READ(DP_B) & DP_DETECTED) 53 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B); 54 } 55 56 if (REG_READ(SDVOC) & SDVO_DETECTED) { 57 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC); 58 if (REG_READ(DP_C) & DP_DETECTED) 59 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C); 60 } 61 return 0; 62 } 63 64 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 65 66 /* 67 * Cedartrail Backlght Interfaces 68 */ 69 70 static struct backlight_device *cdv_backlight_device; 71 72 static int cdv_backlight_combination_mode(struct drm_device *dev) 73 { 74 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 75 } 76 77 static u32 cdv_get_max_backlight(struct drm_device *dev) 78 { 79 u32 max = REG_READ(BLC_PWM_CTL); 80 81 if (max == 0) { 82 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n"); 83 /* i915 does this, I believe which means that we should not 84 * smash PWM control as firmware will take control of it. */ 85 return 1; 86 } 87 88 max >>= 16; 89 if (cdv_backlight_combination_mode(dev)) 90 max *= 0xff; 91 return max; 92 } 93 94 static int cdv_get_brightness(struct backlight_device *bd) 95 { 96 struct drm_device *dev = bl_get_data(bd); 97 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 98 99 if (cdv_backlight_combination_mode(dev)) { 100 u8 lbpc; 101 102 val &= ~1; 103 pci_read_config_byte(dev->pdev, 0xF4, &lbpc); 104 val *= lbpc; 105 } 106 return (val * 100)/cdv_get_max_backlight(dev); 107 108 } 109 110 static int cdv_set_brightness(struct backlight_device *bd) 111 { 112 struct drm_device *dev = bl_get_data(bd); 113 int level = bd->props.brightness; 114 u32 blc_pwm_ctl; 115 116 /* Percentage 1-100% being valid */ 117 if (level < 1) 118 level = 1; 119 120 level *= cdv_get_max_backlight(dev); 121 level /= 100; 122 123 if (cdv_backlight_combination_mode(dev)) { 124 u32 max = cdv_get_max_backlight(dev); 125 u8 lbpc; 126 127 lbpc = level * 0xfe / max + 1; 128 level /= lbpc; 129 130 pci_write_config_byte(dev->pdev, 0xF4, lbpc); 131 } 132 133 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 134 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 135 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 136 return 0; 137 } 138 139 static const struct backlight_ops cdv_ops = { 140 .get_brightness = cdv_get_brightness, 141 .update_status = cdv_set_brightness, 142 }; 143 144 static int cdv_backlight_init(struct drm_device *dev) 145 { 146 struct drm_psb_private *dev_priv = dev->dev_private; 147 struct backlight_properties props; 148 149 memset(&props, 0, sizeof(struct backlight_properties)); 150 props.max_brightness = 100; 151 props.type = BACKLIGHT_PLATFORM; 152 153 cdv_backlight_device = backlight_device_register("psb-bl", 154 NULL, (void *)dev, &cdv_ops, &props); 155 if (IS_ERR(cdv_backlight_device)) 156 return PTR_ERR(cdv_backlight_device); 157 158 cdv_backlight_device->props.brightness = 159 cdv_get_brightness(cdv_backlight_device); 160 backlight_update_status(cdv_backlight_device); 161 dev_priv->backlight_device = cdv_backlight_device; 162 dev_priv->backlight_enabled = true; 163 return 0; 164 } 165 166 #endif 167 168 /* 169 * Provide the Cedarview specific chip logic and low level methods 170 * for power management 171 * 172 * FIXME: we need to implement the apm/ospm base management bits 173 * for this and the MID devices. 174 */ 175 176 static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset) 177 { 178 int mcr = (0x10<<24) | (port << 16) | (offset << 8); 179 uint32_t ret_val = 0; 180 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 181 pci_write_config_dword(pci_root, 0xD0, mcr); 182 pci_read_config_dword(pci_root, 0xD4, &ret_val); 183 pci_dev_put(pci_root); 184 return ret_val; 185 } 186 187 static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset, 188 u32 value) 189 { 190 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; 191 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0); 192 pci_write_config_dword(pci_root, 0xD4, value); 193 pci_write_config_dword(pci_root, 0xD0, mcr); 194 pci_dev_put(pci_root); 195 } 196 197 #define PSB_PM_SSC 0x20 198 #define PSB_PM_SSS 0x30 199 #define PSB_PWRGT_GFX_ON 0x02 200 #define PSB_PWRGT_GFX_OFF 0x01 201 #define PSB_PWRGT_GFX_D0 0x00 202 #define PSB_PWRGT_GFX_D3 0x03 203 204 static void cdv_init_pm(struct drm_device *dev) 205 { 206 struct drm_psb_private *dev_priv = dev->dev_private; 207 u32 pwr_cnt; 208 int domain = pci_domain_nr(dev->pdev->bus); 209 int i; 210 211 dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 212 PSB_APMBA) & 0xFFFF; 213 dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT, 214 PSB_OSPMBA) & 0xFFFF; 215 216 /* Power status */ 217 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 218 219 /* Enable the GPU */ 220 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 221 pwr_cnt |= PSB_PWRGT_GFX_ON; 222 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 223 224 /* Wait for the GPU power */ 225 for (i = 0; i < 5; i++) { 226 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 227 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0) 228 return; 229 udelay(10); 230 } 231 dev_err(dev->dev, "GPU: power management timed out.\n"); 232 } 233 234 static void cdv_errata(struct drm_device *dev) 235 { 236 /* Disable bonus launch. 237 * CPU and GPU competes for memory and display misses updates and 238 * flickers. Worst with dual core, dual displays. 239 * 240 * Fixes were done to Win 7 gfx driver to disable a feature called 241 * Bonus Launch to work around the issue, by degrading 242 * performance. 243 */ 244 CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108); 245 } 246 247 /** 248 * cdv_save_display_registers - save registers lost on suspend 249 * @dev: our DRM device 250 * 251 * Save the state we need in order to be able to restore the interface 252 * upon resume from suspend 253 */ 254 static int cdv_save_display_registers(struct drm_device *dev) 255 { 256 struct drm_psb_private *dev_priv = dev->dev_private; 257 struct psb_save_area *regs = &dev_priv->regs; 258 struct drm_connector *connector; 259 260 dev_dbg(dev->dev, "Saving GPU registers.\n"); 261 262 pci_read_config_byte(dev->pdev, 0xF4, ®s->cdv.saveLBB); 263 264 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); 265 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); 266 267 regs->cdv.saveDSPARB = REG_READ(DSPARB); 268 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); 269 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); 270 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); 271 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); 272 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); 273 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); 274 275 regs->cdv.saveADPA = REG_READ(ADPA); 276 277 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); 278 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); 279 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); 280 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); 281 regs->cdv.saveLVDS = REG_READ(LVDS); 282 283 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); 284 285 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); 286 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); 287 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); 288 289 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); 290 291 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); 292 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); 293 294 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 295 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF); 296 297 return 0; 298 } 299 300 /** 301 * cdv_restore_display_registers - restore lost register state 302 * @dev: our DRM device 303 * 304 * Restore register state that was lost during suspend and resume. 305 * 306 * FIXME: review 307 */ 308 static int cdv_restore_display_registers(struct drm_device *dev) 309 { 310 struct drm_psb_private *dev_priv = dev->dev_private; 311 struct psb_save_area *regs = &dev_priv->regs; 312 struct drm_connector *connector; 313 u32 temp; 314 315 pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB); 316 317 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 318 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 319 320 /* BIOS does below anyway */ 321 REG_WRITE(DPIO_CFG, 0); 322 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 323 324 temp = REG_READ(DPLL_A); 325 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 326 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 327 REG_READ(DPLL_A); 328 } 329 330 temp = REG_READ(DPLL_B); 331 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) { 332 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 333 REG_READ(DPLL_B); 334 } 335 336 udelay(500); 337 338 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 339 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]); 340 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]); 341 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]); 342 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]); 343 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]); 344 345 REG_WRITE(DSPARB, regs->cdv.saveDSPARB); 346 REG_WRITE(ADPA, regs->cdv.saveADPA); 347 348 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); 349 REG_WRITE(LVDS, regs->cdv.saveLVDS); 350 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL); 351 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS); 352 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); 353 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS); 354 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS); 355 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE); 356 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL); 357 358 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL); 359 360 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER); 361 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR); 362 363 /* Fix arbitration bug */ 364 cdv_errata(dev); 365 366 drm_mode_config_reset(dev); 367 368 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 369 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 370 371 /* Resume the modeset for every activated CRTC */ 372 drm_helper_resume_force_mode(dev); 373 return 0; 374 } 375 376 static int cdv_power_down(struct drm_device *dev) 377 { 378 struct drm_psb_private *dev_priv = dev->dev_private; 379 u32 pwr_cnt, pwr_mask, pwr_sts; 380 int tries = 5; 381 382 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 383 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 384 pwr_cnt |= PSB_PWRGT_GFX_OFF; 385 pwr_mask = PSB_PWRGT_GFX_MASK; 386 387 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 388 389 while (tries--) { 390 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 391 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3) 392 return 0; 393 udelay(10); 394 } 395 return 0; 396 } 397 398 static int cdv_power_up(struct drm_device *dev) 399 { 400 struct drm_psb_private *dev_priv = dev->dev_private; 401 u32 pwr_cnt, pwr_mask, pwr_sts; 402 int tries = 5; 403 404 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD); 405 pwr_cnt &= ~PSB_PWRGT_GFX_MASK; 406 pwr_cnt |= PSB_PWRGT_GFX_ON; 407 pwr_mask = PSB_PWRGT_GFX_MASK; 408 409 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD); 410 411 while (tries--) { 412 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS); 413 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0) 414 return 0; 415 udelay(10); 416 } 417 return 0; 418 } 419 420 static void cdv_hotplug_work_func(struct work_struct *work) 421 { 422 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private, 423 hotplug_work); 424 struct drm_device *dev = dev_priv->dev; 425 426 /* Just fire off a uevent and let userspace tell us what to do */ 427 drm_helper_hpd_irq_event(dev); 428 } 429 430 /* The core driver has received a hotplug IRQ. We are in IRQ context 431 so extract the needed information and kick off queued processing */ 432 433 static int cdv_hotplug_event(struct drm_device *dev) 434 { 435 struct drm_psb_private *dev_priv = dev->dev_private; 436 schedule_work(&dev_priv->hotplug_work); 437 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 438 return 1; 439 } 440 441 static void cdv_hotplug_enable(struct drm_device *dev, bool on) 442 { 443 if (on) { 444 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); 445 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN | 446 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN; 447 REG_WRITE(PORT_HOTPLUG_EN, hotplug); 448 } else { 449 REG_WRITE(PORT_HOTPLUG_EN, 0); 450 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); 451 } 452 } 453 454 static const char *force_audio_names[] = { 455 "off", 456 "auto", 457 "on", 458 }; 459 460 void cdv_intel_attach_force_audio_property(struct drm_connector *connector) 461 { 462 struct drm_device *dev = connector->dev; 463 struct drm_psb_private *dev_priv = dev->dev_private; 464 struct drm_property *prop; 465 int i; 466 467 prop = dev_priv->force_audio_property; 468 if (prop == NULL) { 469 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 470 "audio", 471 ARRAY_SIZE(force_audio_names)); 472 if (prop == NULL) 473 return; 474 475 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++) 476 drm_property_add_enum(prop, i-1, force_audio_names[i]); 477 478 dev_priv->force_audio_property = prop; 479 } 480 drm_object_attach_property(&connector->base, prop, 0); 481 } 482 483 484 static const char *broadcast_rgb_names[] = { 485 "Full", 486 "Limited 16:235", 487 }; 488 489 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector) 490 { 491 struct drm_device *dev = connector->dev; 492 struct drm_psb_private *dev_priv = dev->dev_private; 493 struct drm_property *prop; 494 int i; 495 496 prop = dev_priv->broadcast_rgb_property; 497 if (prop == NULL) { 498 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM, 499 "Broadcast RGB", 500 ARRAY_SIZE(broadcast_rgb_names)); 501 if (prop == NULL) 502 return; 503 504 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++) 505 drm_property_add_enum(prop, i, broadcast_rgb_names[i]); 506 507 dev_priv->broadcast_rgb_property = prop; 508 } 509 510 drm_object_attach_property(&connector->base, prop, 0); 511 } 512 513 /* Cedarview */ 514 static const struct psb_offset cdv_regmap[2] = { 515 { 516 .fp0 = FPA0, 517 .fp1 = FPA1, 518 .cntr = DSPACNTR, 519 .conf = PIPEACONF, 520 .src = PIPEASRC, 521 .dpll = DPLL_A, 522 .dpll_md = DPLL_A_MD, 523 .htotal = HTOTAL_A, 524 .hblank = HBLANK_A, 525 .hsync = HSYNC_A, 526 .vtotal = VTOTAL_A, 527 .vblank = VBLANK_A, 528 .vsync = VSYNC_A, 529 .stride = DSPASTRIDE, 530 .size = DSPASIZE, 531 .pos = DSPAPOS, 532 .base = DSPABASE, 533 .surf = DSPASURF, 534 .addr = DSPABASE, 535 .status = PIPEASTAT, 536 .linoff = DSPALINOFF, 537 .tileoff = DSPATILEOFF, 538 .palette = PALETTE_A, 539 }, 540 { 541 .fp0 = FPB0, 542 .fp1 = FPB1, 543 .cntr = DSPBCNTR, 544 .conf = PIPEBCONF, 545 .src = PIPEBSRC, 546 .dpll = DPLL_B, 547 .dpll_md = DPLL_B_MD, 548 .htotal = HTOTAL_B, 549 .hblank = HBLANK_B, 550 .hsync = HSYNC_B, 551 .vtotal = VTOTAL_B, 552 .vblank = VBLANK_B, 553 .vsync = VSYNC_B, 554 .stride = DSPBSTRIDE, 555 .size = DSPBSIZE, 556 .pos = DSPBPOS, 557 .base = DSPBBASE, 558 .surf = DSPBSURF, 559 .addr = DSPBBASE, 560 .status = PIPEBSTAT, 561 .linoff = DSPBLINOFF, 562 .tileoff = DSPBTILEOFF, 563 .palette = PALETTE_B, 564 } 565 }; 566 567 static int cdv_chip_setup(struct drm_device *dev) 568 { 569 struct drm_psb_private *dev_priv = dev->dev_private; 570 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); 571 572 if (pci_enable_msi(dev->pdev)) 573 dev_warn(dev->dev, "Enabling MSI failed!\n"); 574 dev_priv->regmap = cdv_regmap; 575 gma_get_core_freq(dev); 576 psb_intel_opregion_init(dev); 577 psb_intel_init_bios(dev); 578 cdv_hotplug_enable(dev, false); 579 return 0; 580 } 581 582 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */ 583 584 const struct psb_ops cdv_chip_ops = { 585 .name = "GMA3600/3650", 586 .accel_2d = 0, 587 .pipes = 2, 588 .crtcs = 2, 589 .hdmi_mask = (1 << 0) | (1 << 1), 590 .lvds_mask = (1 << 1), 591 .sdvo_mask = (1 << 0), 592 .cursor_needs_phys = 0, 593 .sgx_offset = MRST_SGX_OFFSET, 594 .chip_setup = cdv_chip_setup, 595 .errata = cdv_errata, 596 597 .crtc_helper = &cdv_intel_helper_funcs, 598 .crtc_funcs = &cdv_intel_crtc_funcs, 599 .clock_funcs = &cdv_clock_funcs, 600 601 .output_init = cdv_output_init, 602 .hotplug = cdv_hotplug_event, 603 .hotplug_enable = cdv_hotplug_enable, 604 605 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 606 .backlight_init = cdv_backlight_init, 607 #endif 608 609 .init_pm = cdv_init_pm, 610 .save_regs = cdv_save_display_registers, 611 .restore_regs = cdv_restore_display_registers, 612 .save_crtc = gma_crtc_save, 613 .restore_crtc = gma_crtc_restore, 614 .power_down = cdv_power_down, 615 .power_up = cdv_power_up, 616 .update_wm = cdv_update_wm, 617 .disable_sr = cdv_disable_sr, 618 }; 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