1109eee2fSJianwei Wang /* 2109eee2fSJianwei Wang * Copyright 2015 Freescale Semiconductor, Inc. 3109eee2fSJianwei Wang * 4109eee2fSJianwei Wang * Freescale DCU drm device driver 5109eee2fSJianwei Wang * 6109eee2fSJianwei Wang * This program is free software; you can redistribute it and/or modify 7109eee2fSJianwei Wang * it under the terms of the GNU General Public License as published by 8109eee2fSJianwei Wang * the Free Software Foundation; either version 2 of the License, or 9109eee2fSJianwei Wang * (at your option) any later version. 10109eee2fSJianwei Wang */ 11109eee2fSJianwei Wang 12109eee2fSJianwei Wang #ifndef __FSL_DCU_DRM_DRV_H__ 13109eee2fSJianwei Wang #define __FSL_DCU_DRM_DRV_H__ 14109eee2fSJianwei Wang 15109eee2fSJianwei Wang #include "fsl_dcu_drm_crtc.h" 16109eee2fSJianwei Wang #include "fsl_dcu_drm_output.h" 17109eee2fSJianwei Wang #include "fsl_dcu_drm_plane.h" 18109eee2fSJianwei Wang 19109eee2fSJianwei Wang #define DCU_DCU_MODE 0x0010 20109eee2fSJianwei Wang #define DCU_MODE_BLEND_ITER(x) ((x) << 20) 21109eee2fSJianwei Wang #define DCU_MODE_RASTER_EN BIT(14) 22109eee2fSJianwei Wang #define DCU_MODE_DCU_MODE(x) (x) 23109eee2fSJianwei Wang #define DCU_MODE_DCU_MODE_MASK 0x03 24109eee2fSJianwei Wang #define DCU_MODE_OFF 0 25109eee2fSJianwei Wang #define DCU_MODE_NORMAL 1 26109eee2fSJianwei Wang #define DCU_MODE_TEST 2 27109eee2fSJianwei Wang #define DCU_MODE_COLORBAR 3 28109eee2fSJianwei Wang 29109eee2fSJianwei Wang #define DCU_BGND 0x0014 30109eee2fSJianwei Wang #define DCU_BGND_R(x) ((x) << 16) 31109eee2fSJianwei Wang #define DCU_BGND_G(x) ((x) << 8) 32109eee2fSJianwei Wang #define DCU_BGND_B(x) (x) 33109eee2fSJianwei Wang 34109eee2fSJianwei Wang #define DCU_DISP_SIZE 0x0018 35109eee2fSJianwei Wang #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 36109eee2fSJianwei Wang /*Regisiter value 1/16 of horizontal resolution*/ 37109eee2fSJianwei Wang #define DCU_DISP_SIZE_DELTA_X(x) ((x) >> 4) 38109eee2fSJianwei Wang 39109eee2fSJianwei Wang #define DCU_HSYN_PARA 0x001c 40109eee2fSJianwei Wang #define DCU_HSYN_PARA_BP(x) ((x) << 22) 41109eee2fSJianwei Wang #define DCU_HSYN_PARA_PW(x) ((x) << 11) 42109eee2fSJianwei Wang #define DCU_HSYN_PARA_FP(x) (x) 43109eee2fSJianwei Wang 44109eee2fSJianwei Wang #define DCU_VSYN_PARA 0x0020 45109eee2fSJianwei Wang #define DCU_VSYN_PARA_BP(x) ((x) << 22) 46109eee2fSJianwei Wang #define DCU_VSYN_PARA_PW(x) ((x) << 11) 47109eee2fSJianwei Wang #define DCU_VSYN_PARA_FP(x) (x) 48109eee2fSJianwei Wang 49109eee2fSJianwei Wang #define DCU_SYN_POL 0x0024 50109eee2fSJianwei Wang #define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) 51109eee2fSJianwei Wang #define DCU_SYN_POL_NEG_REMAIN (0 << 5) 52109eee2fSJianwei Wang #define DCU_SYN_POL_INV_VS_LOW BIT(1) 53109eee2fSJianwei Wang #define DCU_SYN_POL_INV_HS_LOW BIT(0) 54109eee2fSJianwei Wang 55109eee2fSJianwei Wang #define DCU_THRESHOLD 0x0028 56109eee2fSJianwei Wang #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) 57109eee2fSJianwei Wang #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) 58109eee2fSJianwei Wang #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) 59109eee2fSJianwei Wang #define BF_VS_VAL 0x03 60109eee2fSJianwei Wang #define BUF_MAX_VAL 0x78 61109eee2fSJianwei Wang #define BUF_MIN_VAL 0x0a 62109eee2fSJianwei Wang 63109eee2fSJianwei Wang #define DCU_INT_STATUS 0x002C 64109eee2fSJianwei Wang #define DCU_INT_STATUS_VSYNC BIT(0) 65109eee2fSJianwei Wang #define DCU_INT_STATUS_UNDRUN BIT(1) 66109eee2fSJianwei Wang #define DCU_INT_STATUS_LSBFVS BIT(2) 67109eee2fSJianwei Wang #define DCU_INT_STATUS_VBLANK BIT(3) 68109eee2fSJianwei Wang #define DCU_INT_STATUS_CRCREADY BIT(4) 69109eee2fSJianwei Wang #define DCU_INT_STATUS_CRCOVERFLOW BIT(5) 70109eee2fSJianwei Wang #define DCU_INT_STATUS_P1FIFOLO BIT(6) 71109eee2fSJianwei Wang #define DCU_INT_STATUS_P1FIFOHI BIT(7) 72109eee2fSJianwei Wang #define DCU_INT_STATUS_P2FIFOLO BIT(8) 73109eee2fSJianwei Wang #define DCU_INT_STATUS_P2FIFOHI BIT(9) 74109eee2fSJianwei Wang #define DCU_INT_STATUS_PROGEND BIT(10) 75109eee2fSJianwei Wang #define DCU_INT_STATUS_IPMERROR BIT(11) 76109eee2fSJianwei Wang #define DCU_INT_STATUS_LYRTRANS BIT(12) 77109eee2fSJianwei Wang #define DCU_INT_STATUS_DMATRANS BIT(14) 78109eee2fSJianwei Wang #define DCU_INT_STATUS_P3FIFOLO BIT(16) 79109eee2fSJianwei Wang #define DCU_INT_STATUS_P3FIFOHI BIT(17) 80109eee2fSJianwei Wang #define DCU_INT_STATUS_P4FIFOLO BIT(18) 81109eee2fSJianwei Wang #define DCU_INT_STATUS_P4FIFOHI BIT(19) 82109eee2fSJianwei Wang #define DCU_INT_STATUS_P1EMPTY BIT(26) 83109eee2fSJianwei Wang #define DCU_INT_STATUS_P2EMPTY BIT(27) 84109eee2fSJianwei Wang #define DCU_INT_STATUS_P3EMPTY BIT(28) 85109eee2fSJianwei Wang #define DCU_INT_STATUS_P4EMPTY BIT(29) 86109eee2fSJianwei Wang 87109eee2fSJianwei Wang #define DCU_INT_MASK 0x0030 88109eee2fSJianwei Wang #define DCU_INT_MASK_VSYNC BIT(0) 89109eee2fSJianwei Wang #define DCU_INT_MASK_UNDRUN BIT(1) 90109eee2fSJianwei Wang #define DCU_INT_MASK_LSBFVS BIT(2) 91109eee2fSJianwei Wang #define DCU_INT_MASK_VBLANK BIT(3) 92109eee2fSJianwei Wang #define DCU_INT_MASK_CRCREADY BIT(4) 93109eee2fSJianwei Wang #define DCU_INT_MASK_CRCOVERFLOW BIT(5) 94109eee2fSJianwei Wang #define DCU_INT_MASK_P1FIFOLO BIT(6) 95109eee2fSJianwei Wang #define DCU_INT_MASK_P1FIFOHI BIT(7) 96109eee2fSJianwei Wang #define DCU_INT_MASK_P2FIFOLO BIT(8) 97109eee2fSJianwei Wang #define DCU_INT_MASK_P2FIFOHI BIT(9) 98109eee2fSJianwei Wang #define DCU_INT_MASK_PROGEND BIT(10) 99109eee2fSJianwei Wang #define DCU_INT_MASK_IPMERROR BIT(11) 100109eee2fSJianwei Wang #define DCU_INT_MASK_LYRTRANS BIT(12) 101109eee2fSJianwei Wang #define DCU_INT_MASK_DMATRANS BIT(14) 102109eee2fSJianwei Wang #define DCU_INT_MASK_P3FIFOLO BIT(16) 103109eee2fSJianwei Wang #define DCU_INT_MASK_P3FIFOHI BIT(17) 104109eee2fSJianwei Wang #define DCU_INT_MASK_P4FIFOLO BIT(18) 105109eee2fSJianwei Wang #define DCU_INT_MASK_P4FIFOHI BIT(19) 106109eee2fSJianwei Wang #define DCU_INT_MASK_P1EMPTY BIT(26) 107109eee2fSJianwei Wang #define DCU_INT_MASK_P2EMPTY BIT(27) 108109eee2fSJianwei Wang #define DCU_INT_MASK_P3EMPTY BIT(28) 109109eee2fSJianwei Wang #define DCU_INT_MASK_P4EMPTY BIT(29) 110109eee2fSJianwei Wang 111109eee2fSJianwei Wang #define DCU_DIV_RATIO 0x0054 112109eee2fSJianwei Wang 113109eee2fSJianwei Wang #define DCU_UPDATE_MODE 0x00cc 114109eee2fSJianwei Wang #define DCU_UPDATE_MODE_MODE BIT(31) 115109eee2fSJianwei Wang #define DCU_UPDATE_MODE_READREG BIT(30) 116109eee2fSJianwei Wang 117109eee2fSJianwei Wang #define DCU_DCFB_MAX 0x300 118109eee2fSJianwei Wang 119109eee2fSJianwei Wang #define DCU_CTRLDESCLN(layer, reg) (0x200 + (reg - 1) * 4 + (layer) * 0x40) 120109eee2fSJianwei Wang 121109eee2fSJianwei Wang #define DCU_LAYER_HEIGHT(x) ((x) << 16) 122109eee2fSJianwei Wang #define DCU_LAYER_WIDTH(x) (x) 123109eee2fSJianwei Wang 124109eee2fSJianwei Wang #define DCU_LAYER_POSY(x) ((x) << 16) 125109eee2fSJianwei Wang #define DCU_LAYER_POSX(x) (x) 126109eee2fSJianwei Wang 127109eee2fSJianwei Wang #define DCU_LAYER_EN BIT(31) 128109eee2fSJianwei Wang #define DCU_LAYER_TILE_EN BIT(30) 129109eee2fSJianwei Wang #define DCU_LAYER_DATA_SEL_CLUT BIT(29) 130109eee2fSJianwei Wang #define DCU_LAYER_SAFETY_EN BIT(28) 131109eee2fSJianwei Wang #define DCU_LAYER_TRANS(x) ((x) << 20) 132109eee2fSJianwei Wang #define DCU_LAYER_BPP(x) ((x) << 16) 133109eee2fSJianwei Wang #define DCU_LAYER_RLE_EN BIT(15) 134109eee2fSJianwei Wang #define DCU_LAYER_LUOFFS(x) ((x) << 4) 135109eee2fSJianwei Wang #define DCU_LAYER_BB_ON BIT(2) 13669855819SStefan Agner #define DCU_LAYER_AB_NONE 0 13769855819SStefan Agner #define DCU_LAYER_AB_CHROMA_KEYING 1 13869855819SStefan Agner #define DCU_LAYER_AB_WHOLE_FRAME 2 139109eee2fSJianwei Wang 140109eee2fSJianwei Wang #define DCU_LAYER_CKMAX_R(x) ((x) << 16) 141109eee2fSJianwei Wang #define DCU_LAYER_CKMAX_G(x) ((x) << 8) 142109eee2fSJianwei Wang #define DCU_LAYER_CKMAX_B(x) (x) 143109eee2fSJianwei Wang 144109eee2fSJianwei Wang #define DCU_LAYER_CKMIN_R(x) ((x) << 16) 145109eee2fSJianwei Wang #define DCU_LAYER_CKMIN_G(x) ((x) << 8) 146109eee2fSJianwei Wang #define DCU_LAYER_CKMIN_B(x) (x) 147109eee2fSJianwei Wang 148109eee2fSJianwei Wang #define DCU_LAYER_TILE_VER(x) ((x) << 16) 149109eee2fSJianwei Wang #define DCU_LAYER_TILE_HOR(x) (x) 150109eee2fSJianwei Wang 151109eee2fSJianwei Wang #define DCU_LAYER_FG_FCOLOR(x) (x) 152109eee2fSJianwei Wang 153109eee2fSJianwei Wang #define DCU_LAYER_BG_BCOLOR(x) (x) 154109eee2fSJianwei Wang 155109eee2fSJianwei Wang #define DCU_LAYER_POST_SKIP(x) ((x) << 16) 156109eee2fSJianwei Wang #define DCU_LAYER_PRE_SKIP(x) (x) 157109eee2fSJianwei Wang 158109eee2fSJianwei Wang #define FSL_DCU_RGB565 4 159109eee2fSJianwei Wang #define FSL_DCU_RGB888 5 160109eee2fSJianwei Wang #define FSL_DCU_ARGB8888 6 161109eee2fSJianwei Wang #define FSL_DCU_ARGB1555 11 162109eee2fSJianwei Wang #define FSL_DCU_ARGB4444 12 163109eee2fSJianwei Wang #define FSL_DCU_YUV422 14 164109eee2fSJianwei Wang 165109eee2fSJianwei Wang #define VF610_LAYER_REG_NUM 9 166109eee2fSJianwei Wang #define LS1021A_LAYER_REG_NUM 10 167109eee2fSJianwei Wang 168109eee2fSJianwei Wang struct clk; 169109eee2fSJianwei Wang struct device; 170109eee2fSJianwei Wang struct drm_device; 171109eee2fSJianwei Wang 172109eee2fSJianwei Wang struct fsl_dcu_soc_data { 173109eee2fSJianwei Wang const char *name; 174109eee2fSJianwei Wang /*total layer number*/ 175109eee2fSJianwei Wang unsigned int total_layer; 176109eee2fSJianwei Wang /*max layer number DCU supported*/ 177109eee2fSJianwei Wang unsigned int max_layer; 178109eee2fSJianwei Wang }; 179109eee2fSJianwei Wang 180109eee2fSJianwei Wang struct fsl_dcu_drm_device { 181109eee2fSJianwei Wang struct device *dev; 182109eee2fSJianwei Wang struct device_node *np; 183109eee2fSJianwei Wang struct regmap *regmap; 184109eee2fSJianwei Wang int irq; 185109eee2fSJianwei Wang struct clk *clk; 186f93500f4SStefan Agner struct clk *pix_clk; 187109eee2fSJianwei Wang /*protects hardware register*/ 188109eee2fSJianwei Wang spinlock_t irq_lock; 189109eee2fSJianwei Wang struct drm_device *drm; 190109eee2fSJianwei Wang struct drm_fbdev_cma *fbdev; 191109eee2fSJianwei Wang struct drm_crtc crtc; 192109eee2fSJianwei Wang struct drm_encoder encoder; 193109eee2fSJianwei Wang struct fsl_dcu_drm_connector connector; 194109eee2fSJianwei Wang const struct fsl_dcu_soc_data *soc; 195109eee2fSJianwei Wang }; 196109eee2fSJianwei Wang 197109eee2fSJianwei Wang void fsl_dcu_fbdev_init(struct drm_device *dev); 198109eee2fSJianwei Wang int fsl_dcu_drm_modeset_init(struct fsl_dcu_drm_device *fsl_dev); 199109eee2fSJianwei Wang 200109eee2fSJianwei Wang #endif /* __FSL_DCU_DRM_DRV_H__ */ 201