1 /* 2 * Copyright 2015 Freescale Semiconductor, Inc. 3 * 4 * Freescale DCU drm device driver 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/regmap.h> 14 15 #include <drm/drmP.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 21 #include "fsl_dcu_drm_crtc.h" 22 #include "fsl_dcu_drm_drv.h" 23 #include "fsl_dcu_drm_plane.h" 24 25 static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, 26 struct drm_crtc_state *old_crtc_state) 27 { 28 struct drm_device *dev = crtc->dev; 29 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 30 struct drm_pending_vblank_event *event = crtc->state->event; 31 32 regmap_write(fsl_dev->regmap, 33 DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG); 34 35 if (event) { 36 crtc->state->event = NULL; 37 38 spin_lock_irq(&crtc->dev->event_lock); 39 if (drm_crtc_vblank_get(crtc) == 0) 40 drm_crtc_arm_vblank_event(crtc, event); 41 else 42 drm_crtc_send_vblank_event(crtc, event); 43 spin_unlock_irq(&crtc->dev->event_lock); 44 } 45 } 46 47 static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc, 48 struct drm_crtc_state *old_crtc_state) 49 { 50 struct drm_device *dev = crtc->dev; 51 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 52 53 /* always disable planes on the CRTC */ 54 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true); 55 56 drm_crtc_vblank_off(crtc); 57 58 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, 59 DCU_MODE_DCU_MODE_MASK, 60 DCU_MODE_DCU_MODE(DCU_MODE_OFF)); 61 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 62 DCU_UPDATE_MODE_READREG); 63 clk_disable_unprepare(fsl_dev->pix_clk); 64 } 65 66 static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc) 67 { 68 struct drm_device *dev = crtc->dev; 69 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 70 71 clk_prepare_enable(fsl_dev->pix_clk); 72 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE, 73 DCU_MODE_DCU_MODE_MASK, 74 DCU_MODE_DCU_MODE(DCU_MODE_NORMAL)); 75 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, 76 DCU_UPDATE_MODE_READREG); 77 78 drm_crtc_vblank_on(crtc); 79 } 80 81 static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 82 { 83 struct drm_device *dev = crtc->dev; 84 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; 85 struct drm_connector *con = &fsl_dev->connector.base; 86 struct drm_display_mode *mode = &crtc->state->mode; 87 unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0; 88 89 index = drm_crtc_index(crtc); 90 clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000); 91 92 /* Configure timings: */ 93 hbp = mode->htotal - mode->hsync_end; 94 hfp = mode->hsync_start - mode->hdisplay; 95 hsw = mode->hsync_end - mode->hsync_start; 96 vbp = mode->vtotal - mode->vsync_end; 97 vfp = mode->vsync_start - mode->vdisplay; 98 vsw = mode->vsync_end - mode->vsync_start; 99 100 /* INV_PXCK as default (most display sample data on rising edge) */ 101 if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_POSEDGE)) 102 pol |= DCU_SYN_POL_INV_PXCK; 103 104 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 105 pol |= DCU_SYN_POL_INV_HS_LOW; 106 107 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 108 pol |= DCU_SYN_POL_INV_VS_LOW; 109 110 regmap_write(fsl_dev->regmap, DCU_HSYN_PARA, 111 DCU_HSYN_PARA_BP(hbp) | 112 DCU_HSYN_PARA_PW(hsw) | 113 DCU_HSYN_PARA_FP(hfp)); 114 regmap_write(fsl_dev->regmap, DCU_VSYN_PARA, 115 DCU_VSYN_PARA_BP(vbp) | 116 DCU_VSYN_PARA_PW(vsw) | 117 DCU_VSYN_PARA_FP(vfp)); 118 regmap_write(fsl_dev->regmap, DCU_DISP_SIZE, 119 DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) | 120 DCU_DISP_SIZE_DELTA_X(mode->hdisplay)); 121 regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol); 122 regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) | 123 DCU_BGND_G(0) | DCU_BGND_B(0)); 124 regmap_write(fsl_dev->regmap, DCU_DCU_MODE, 125 DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN); 126 regmap_write(fsl_dev->regmap, DCU_THRESHOLD, 127 DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | 128 DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | 129 DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); 130 return; 131 } 132 133 static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = { 134 .atomic_disable = fsl_dcu_drm_crtc_atomic_disable, 135 .atomic_flush = fsl_dcu_drm_crtc_atomic_flush, 136 .enable = fsl_dcu_drm_crtc_enable, 137 .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb, 138 }; 139 140 static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = { 141 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 142 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 143 .destroy = drm_crtc_cleanup, 144 .page_flip = drm_atomic_helper_page_flip, 145 .reset = drm_atomic_helper_crtc_reset, 146 .set_config = drm_atomic_helper_set_config, 147 }; 148 149 int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev) 150 { 151 struct drm_plane *primary; 152 struct drm_crtc *crtc = &fsl_dev->crtc; 153 int ret; 154 155 fsl_dcu_drm_init_planes(fsl_dev->drm); 156 157 primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm); 158 if (!primary) 159 return -ENOMEM; 160 161 ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL, 162 &fsl_dcu_drm_crtc_funcs, NULL); 163 if (ret) { 164 primary->funcs->destroy(primary); 165 return ret; 166 } 167 168 drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs); 169 170 return 0; 171 } 172