1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d8408326SSeung-Woo Kim /* 3d8408326SSeung-Woo Kim * 4d8408326SSeung-Woo Kim * Cloned from drivers/media/video/s5p-tv/regs-mixer.h 5d8408326SSeung-Woo Kim * 6d8408326SSeung-Woo Kim * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 7d8408326SSeung-Woo Kim * http://www.samsung.com/ 8d8408326SSeung-Woo Kim * 9d8408326SSeung-Woo Kim * Mixer register header file for Samsung Mixer driver 10d8408326SSeung-Woo Kim */ 11d8408326SSeung-Woo Kim #ifndef SAMSUNG_REGS_MIXER_H 12d8408326SSeung-Woo Kim #define SAMSUNG_REGS_MIXER_H 13d8408326SSeung-Woo Kim 14d8408326SSeung-Woo Kim /* 15d8408326SSeung-Woo Kim * Register part 16d8408326SSeung-Woo Kim */ 17d8408326SSeung-Woo Kim #define MXR_STATUS 0x0000 18d8408326SSeung-Woo Kim #define MXR_CFG 0x0004 19d8408326SSeung-Woo Kim #define MXR_INT_EN 0x0008 20d8408326SSeung-Woo Kim #define MXR_INT_STATUS 0x000C 21d8408326SSeung-Woo Kim #define MXR_LAYER_CFG 0x0010 22d8408326SSeung-Woo Kim #define MXR_VIDEO_CFG 0x0014 23d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_CFG 0x0020 24d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_BASE 0x0024 25d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_SPAN 0x0028 26d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_SXY 0x002C 27d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_WH 0x0030 28d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_DXY 0x0034 29d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_BLANK 0x0038 30d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_CFG 0x0040 31d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_BASE 0x0044 32d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_SPAN 0x0048 33d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_SXY 0x004C 34d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_WH 0x0050 35d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_DXY 0x0054 36d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_BLANK 0x0058 37d8408326SSeung-Woo Kim #define MXR_BG_CFG 0x0060 38d8408326SSeung-Woo Kim #define MXR_BG_COLOR0 0x0064 39d8408326SSeung-Woo Kim #define MXR_BG_COLOR1 0x0068 40d8408326SSeung-Woo Kim #define MXR_BG_COLOR2 0x006C 41d8408326SSeung-Woo Kim #define MXR_CM_COEFF_Y 0x0080 42d8408326SSeung-Woo Kim #define MXR_CM_COEFF_CB 0x0084 43d8408326SSeung-Woo Kim #define MXR_CM_COEFF_CR 0x0088 44def5e095SRahul Sharma #define MXR_MO 0x0304 45def5e095SRahul Sharma #define MXR_RESOLUTION 0x0310 46def5e095SRahul Sharma 472eced8e9SAndrzej Hajda #define MXR_CFG_S 0x2004 48d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_BASE_S 0x2024 49d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_BASE_S 0x2044 50d8408326SSeung-Woo Kim 51d8408326SSeung-Woo Kim /* for parametrized access to layer registers */ 52d8408326SSeung-Woo Kim #define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20) 53d8408326SSeung-Woo Kim #define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20) 54d8408326SSeung-Woo Kim #define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20) 55d8408326SSeung-Woo Kim #define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20) 56d8408326SSeung-Woo Kim #define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20) 57d8408326SSeung-Woo Kim #define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20) 58d8408326SSeung-Woo Kim #define MXR_GRAPHIC_BLANK(i) (0x0038 + (i) * 0x20) 59d8408326SSeung-Woo Kim #define MXR_GRAPHIC_BASE_S(i) (0x2024 + (i) * 0x20) 60d8408326SSeung-Woo Kim 61d8408326SSeung-Woo Kim /* 62d8408326SSeung-Woo Kim * Bit definition part 63d8408326SSeung-Woo Kim */ 64d8408326SSeung-Woo Kim 65d8408326SSeung-Woo Kim /* generates mask for range of bits */ 66d8408326SSeung-Woo Kim #define MXR_MASK(high_bit, low_bit) \ 67d8408326SSeung-Woo Kim (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) 68d8408326SSeung-Woo Kim 69d8408326SSeung-Woo Kim #define MXR_MASK_VAL(val, high_bit, low_bit) \ 70d8408326SSeung-Woo Kim (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) 71d8408326SSeung-Woo Kim 72d8408326SSeung-Woo Kim /* bits for MXR_STATUS */ 73aaf8b49eSRahul Sharma #define MXR_STATUS_SOFT_RESET (1 << 8) 74d8408326SSeung-Woo Kim #define MXR_STATUS_16_BURST (1 << 7) 75d8408326SSeung-Woo Kim #define MXR_STATUS_BURST_MASK (1 << 7) 76d8408326SSeung-Woo Kim #define MXR_STATUS_BIG_ENDIAN (1 << 3) 77d8408326SSeung-Woo Kim #define MXR_STATUS_ENDIAN_MASK (1 << 3) 78d8408326SSeung-Woo Kim #define MXR_STATUS_SYNC_ENABLE (1 << 2) 79381be025SRahul Sharma #define MXR_STATUS_REG_IDLE (1 << 1) 80d8408326SSeung-Woo Kim #define MXR_STATUS_REG_RUN (1 << 0) 81d8408326SSeung-Woo Kim 82d8408326SSeung-Woo Kim /* bits for MXR_CFG */ 83aaf8b49eSRahul Sharma #define MXR_CFG_LAYER_UPDATE (1 << 31) 84aaf8b49eSRahul Sharma #define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29) 8513e810f1SChristoph Manszewski #define MXR_CFG_QUANT_RANGE_FULL (0 << 9) 8613e810f1SChristoph Manszewski #define MXR_CFG_QUANT_RANGE_LIMITED (1 << 9) 8713e810f1SChristoph Manszewski #define MXR_CFG_RGB601 (0 << 10) 8813e810f1SChristoph Manszewski #define MXR_CFG_RGB709 (1 << 10) 8913e810f1SChristoph Manszewski 90d8408326SSeung-Woo Kim #define MXR_CFG_RGB_FMT_MASK 0x600 91d8408326SSeung-Woo Kim #define MXR_CFG_OUT_YUV444 (0 << 8) 92d8408326SSeung-Woo Kim #define MXR_CFG_OUT_RGB888 (1 << 8) 93d8408326SSeung-Woo Kim #define MXR_CFG_OUT_MASK (1 << 8) 94d8408326SSeung-Woo Kim #define MXR_CFG_DST_SDO (0 << 7) 95d8408326SSeung-Woo Kim #define MXR_CFG_DST_HDMI (1 << 7) 96d8408326SSeung-Woo Kim #define MXR_CFG_DST_MASK (1 << 7) 97d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_HD_720 (0 << 6) 98d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_HD_1080 (1 << 6) 99d8408326SSeung-Woo Kim #define MXR_CFG_GRP1_ENABLE (1 << 5) 100d8408326SSeung-Woo Kim #define MXR_CFG_GRP0_ENABLE (1 << 4) 101d8408326SSeung-Woo Kim #define MXR_CFG_VP_ENABLE (1 << 3) 102d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_INTERLACE (0 << 2) 1031e6d459dSTobias Jakobi #define MXR_CFG_SCAN_PROGRESSIVE (1 << 2) 104d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_NTSC (0 << 1) 105d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_PAL (1 << 1) 106d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_SD (0 << 0) 107d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_HD (1 << 0) 108d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_MASK 0x47 109d8408326SSeung-Woo Kim 1106ac99a32SChristoph Manszewski /* bits for MXR_VIDEO_CFG */ 1116ac99a32SChristoph Manszewski #define MXR_VID_CFG_BLEND_EN (1 << 16) 1126ac99a32SChristoph Manszewski 113d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_CFG */ 114d8408326SSeung-Woo Kim #define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) 115d8408326SSeung-Woo Kim #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) 116d8408326SSeung-Woo Kim #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) 117d8408326SSeung-Woo Kim #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) 1186ac99a32SChristoph Manszewski #define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20) | 0xff) 119d8408326SSeung-Woo Kim #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) 120d8408326SSeung-Woo Kim #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) 121d8408326SSeung-Woo Kim #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) 122d8408326SSeung-Woo Kim 123d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_WH */ 124d8408326SSeung-Woo Kim #define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28) 125d8408326SSeung-Woo Kim #define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12) 126d8408326SSeung-Woo Kim #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) 127d8408326SSeung-Woo Kim #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) 128d8408326SSeung-Woo Kim 129def5e095SRahul Sharma /* bits for MXR_RESOLUTION */ 130def5e095SRahul Sharma #define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16) 131def5e095SRahul Sharma #define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0) 132def5e095SRahul Sharma 133d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_SXY */ 134d8408326SSeung-Woo Kim #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) 135d8408326SSeung-Woo Kim #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) 136d8408326SSeung-Woo Kim 137d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_DXY */ 138d8408326SSeung-Woo Kim #define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16) 139d8408326SSeung-Woo Kim #define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0) 140d8408326SSeung-Woo Kim 141d8408326SSeung-Woo Kim /* bits for MXR_INT_EN */ 142d8408326SSeung-Woo Kim #define MXR_INT_EN_VSYNC (1 << 11) 143d8408326SSeung-Woo Kim #define MXR_INT_EN_ALL (0x0f << 8) 144d8408326SSeung-Woo Kim 1452a6e4cd5STobias Jakobi /* bits for MXR_INT_STATUS */ 146d8408326SSeung-Woo Kim #define MXR_INT_CLEAR_VSYNC (1 << 11) 147d8408326SSeung-Woo Kim #define MXR_INT_STATUS_VSYNC (1 << 0) 148d8408326SSeung-Woo Kim 1492a6e4cd5STobias Jakobi /* bits for MXR_LAYER_CFG */ 150d8408326SSeung-Woo Kim #define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) 151a2cb911eSMarek Szyprowski #define MXR_LAYER_CFG_GRP1_MASK MXR_LAYER_CFG_GRP1_VAL(~0) 152d8408326SSeung-Woo Kim #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) 153a2cb911eSMarek Szyprowski #define MXR_LAYER_CFG_GRP0_MASK MXR_LAYER_CFG_GRP0_VAL(~0) 154d8408326SSeung-Woo Kim #define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) 155a2cb911eSMarek Szyprowski #define MXR_LAYER_CFG_VP_MASK MXR_LAYER_CFG_VP_VAL(~0) 156d8408326SSeung-Woo Kim 1572a6e4cd5STobias Jakobi /* bits for MXR_CM_COEFF_Y */ 1582a6e4cd5STobias Jakobi #define MXR_CM_COEFF_RGB_FULL (1 << 30) 1592a6e4cd5STobias Jakobi 160d8408326SSeung-Woo Kim #endif /* SAMSUNG_REGS_MIXER_H */ 161d8408326SSeung-Woo Kim 162