1d8408326SSeung-Woo Kim /* 2d8408326SSeung-Woo Kim * 3d8408326SSeung-Woo Kim * Cloned from drivers/media/video/s5p-tv/regs-mixer.h 4d8408326SSeung-Woo Kim * 5d8408326SSeung-Woo Kim * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 6d8408326SSeung-Woo Kim * http://www.samsung.com/ 7d8408326SSeung-Woo Kim * 8d8408326SSeung-Woo Kim * Mixer register header file for Samsung Mixer driver 9d8408326SSeung-Woo Kim * 10d8408326SSeung-Woo Kim * This program is free software; you can redistribute it and/or modify 11d8408326SSeung-Woo Kim * it under the terms of the GNU General Public License version 2 as 12d8408326SSeung-Woo Kim * published by the Free Software Foundation. 13d8408326SSeung-Woo Kim */ 14d8408326SSeung-Woo Kim #ifndef SAMSUNG_REGS_MIXER_H 15d8408326SSeung-Woo Kim #define SAMSUNG_REGS_MIXER_H 16d8408326SSeung-Woo Kim 17d8408326SSeung-Woo Kim /* 18d8408326SSeung-Woo Kim * Register part 19d8408326SSeung-Woo Kim */ 20d8408326SSeung-Woo Kim #define MXR_STATUS 0x0000 21d8408326SSeung-Woo Kim #define MXR_CFG 0x0004 22d8408326SSeung-Woo Kim #define MXR_INT_EN 0x0008 23d8408326SSeung-Woo Kim #define MXR_INT_STATUS 0x000C 24d8408326SSeung-Woo Kim #define MXR_LAYER_CFG 0x0010 25d8408326SSeung-Woo Kim #define MXR_VIDEO_CFG 0x0014 26d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_CFG 0x0020 27d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_BASE 0x0024 28d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_SPAN 0x0028 29d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_SXY 0x002C 30d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_WH 0x0030 31d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_DXY 0x0034 32d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_BLANK 0x0038 33d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_CFG 0x0040 34d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_BASE 0x0044 35d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_SPAN 0x0048 36d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_SXY 0x004C 37d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_WH 0x0050 38d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_DXY 0x0054 39d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_BLANK 0x0058 40d8408326SSeung-Woo Kim #define MXR_BG_CFG 0x0060 41d8408326SSeung-Woo Kim #define MXR_BG_COLOR0 0x0064 42d8408326SSeung-Woo Kim #define MXR_BG_COLOR1 0x0068 43d8408326SSeung-Woo Kim #define MXR_BG_COLOR2 0x006C 44d8408326SSeung-Woo Kim #define MXR_CM_COEFF_Y 0x0080 45d8408326SSeung-Woo Kim #define MXR_CM_COEFF_CB 0x0084 46d8408326SSeung-Woo Kim #define MXR_CM_COEFF_CR 0x0088 47def5e095SRahul Sharma #define MXR_MO 0x0304 48def5e095SRahul Sharma #define MXR_RESOLUTION 0x0310 49def5e095SRahul Sharma 50d8408326SSeung-Woo Kim #define MXR_GRAPHIC0_BASE_S 0x2024 51d8408326SSeung-Woo Kim #define MXR_GRAPHIC1_BASE_S 0x2044 52d8408326SSeung-Woo Kim 53d8408326SSeung-Woo Kim /* for parametrized access to layer registers */ 54d8408326SSeung-Woo Kim #define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20) 55d8408326SSeung-Woo Kim #define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20) 56d8408326SSeung-Woo Kim #define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20) 57d8408326SSeung-Woo Kim #define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20) 58d8408326SSeung-Woo Kim #define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20) 59d8408326SSeung-Woo Kim #define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20) 60d8408326SSeung-Woo Kim #define MXR_GRAPHIC_BLANK(i) (0x0038 + (i) * 0x20) 61d8408326SSeung-Woo Kim #define MXR_GRAPHIC_BASE_S(i) (0x2024 + (i) * 0x20) 62d8408326SSeung-Woo Kim 63d8408326SSeung-Woo Kim /* 64d8408326SSeung-Woo Kim * Bit definition part 65d8408326SSeung-Woo Kim */ 66d8408326SSeung-Woo Kim 67d8408326SSeung-Woo Kim /* generates mask for range of bits */ 68d8408326SSeung-Woo Kim #define MXR_MASK(high_bit, low_bit) \ 69d8408326SSeung-Woo Kim (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) 70d8408326SSeung-Woo Kim 71d8408326SSeung-Woo Kim #define MXR_MASK_VAL(val, high_bit, low_bit) \ 72d8408326SSeung-Woo Kim (((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) 73d8408326SSeung-Woo Kim 74d8408326SSeung-Woo Kim /* bits for MXR_STATUS */ 75aaf8b49eSRahul Sharma #define MXR_STATUS_SOFT_RESET (1 << 8) 76d8408326SSeung-Woo Kim #define MXR_STATUS_16_BURST (1 << 7) 77d8408326SSeung-Woo Kim #define MXR_STATUS_BURST_MASK (1 << 7) 78d8408326SSeung-Woo Kim #define MXR_STATUS_BIG_ENDIAN (1 << 3) 79d8408326SSeung-Woo Kim #define MXR_STATUS_ENDIAN_MASK (1 << 3) 80d8408326SSeung-Woo Kim #define MXR_STATUS_SYNC_ENABLE (1 << 2) 81381be025SRahul Sharma #define MXR_STATUS_REG_IDLE (1 << 1) 82d8408326SSeung-Woo Kim #define MXR_STATUS_REG_RUN (1 << 0) 83d8408326SSeung-Woo Kim 84d8408326SSeung-Woo Kim /* bits for MXR_CFG */ 85aaf8b49eSRahul Sharma #define MXR_CFG_LAYER_UPDATE (1 << 31) 86aaf8b49eSRahul Sharma #define MXR_CFG_LAYER_UPDATE_COUNT_MASK (3 << 29) 87d8408326SSeung-Woo Kim #define MXR_CFG_RGB601_0_255 (0 << 9) 88d8408326SSeung-Woo Kim #define MXR_CFG_RGB601_16_235 (1 << 9) 89d8408326SSeung-Woo Kim #define MXR_CFG_RGB709_0_255 (2 << 9) 90d8408326SSeung-Woo Kim #define MXR_CFG_RGB709_16_235 (3 << 9) 91d8408326SSeung-Woo Kim #define MXR_CFG_RGB_FMT_MASK 0x600 92d8408326SSeung-Woo Kim #define MXR_CFG_OUT_YUV444 (0 << 8) 93d8408326SSeung-Woo Kim #define MXR_CFG_OUT_RGB888 (1 << 8) 94d8408326SSeung-Woo Kim #define MXR_CFG_OUT_MASK (1 << 8) 95d8408326SSeung-Woo Kim #define MXR_CFG_DST_SDO (0 << 7) 96d8408326SSeung-Woo Kim #define MXR_CFG_DST_HDMI (1 << 7) 97d8408326SSeung-Woo Kim #define MXR_CFG_DST_MASK (1 << 7) 98d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_HD_720 (0 << 6) 99d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_HD_1080 (1 << 6) 100d8408326SSeung-Woo Kim #define MXR_CFG_GRP1_ENABLE (1 << 5) 101d8408326SSeung-Woo Kim #define MXR_CFG_GRP0_ENABLE (1 << 4) 102d8408326SSeung-Woo Kim #define MXR_CFG_VP_ENABLE (1 << 3) 103d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_INTERLACE (0 << 2) 1041e6d459dSTobias Jakobi #define MXR_CFG_SCAN_PROGRESSIVE (1 << 2) 105d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_NTSC (0 << 1) 106d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_PAL (1 << 1) 107d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_SD (0 << 0) 108d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_HD (1 << 0) 109d8408326SSeung-Woo Kim #define MXR_CFG_SCAN_MASK 0x47 110d8408326SSeung-Woo Kim 111d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_CFG */ 112d8408326SSeung-Woo Kim #define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) 113d8408326SSeung-Woo Kim #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) 114d8408326SSeung-Woo Kim #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) 115d8408326SSeung-Woo Kim #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) 116d8408326SSeung-Woo Kim #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) 117d8408326SSeung-Woo Kim #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) 118d8408326SSeung-Woo Kim #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) 119d8408326SSeung-Woo Kim 120d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_WH */ 121d8408326SSeung-Woo Kim #define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28) 122d8408326SSeung-Woo Kim #define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12) 123d8408326SSeung-Woo Kim #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) 124d8408326SSeung-Woo Kim #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) 125d8408326SSeung-Woo Kim 126def5e095SRahul Sharma /* bits for MXR_RESOLUTION */ 127def5e095SRahul Sharma #define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16) 128def5e095SRahul Sharma #define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0) 129def5e095SRahul Sharma 130d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_SXY */ 131d8408326SSeung-Woo Kim #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) 132d8408326SSeung-Woo Kim #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) 133d8408326SSeung-Woo Kim 134d8408326SSeung-Woo Kim /* bits for MXR_GRAPHICn_DXY */ 135d8408326SSeung-Woo Kim #define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16) 136d8408326SSeung-Woo Kim #define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0) 137d8408326SSeung-Woo Kim 138d8408326SSeung-Woo Kim /* bits for MXR_INT_EN */ 139d8408326SSeung-Woo Kim #define MXR_INT_EN_VSYNC (1 << 11) 140d8408326SSeung-Woo Kim #define MXR_INT_EN_ALL (0x0f << 8) 141d8408326SSeung-Woo Kim 142d8408326SSeung-Woo Kim /* bit for MXR_INT_STATUS */ 143d8408326SSeung-Woo Kim #define MXR_INT_CLEAR_VSYNC (1 << 11) 144d8408326SSeung-Woo Kim #define MXR_INT_STATUS_VSYNC (1 << 0) 145d8408326SSeung-Woo Kim 146d8408326SSeung-Woo Kim /* bit for MXR_LAYER_CFG */ 147d8408326SSeung-Woo Kim #define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) 148d8408326SSeung-Woo Kim #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) 149d8408326SSeung-Woo Kim #define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) 150d8408326SSeung-Woo Kim 151d8408326SSeung-Woo Kim #endif /* SAMSUNG_REGS_MIXER_H */ 152d8408326SSeung-Woo Kim 153