1 /* 2 * 3 * Cloned from drivers/media/video/s5p-tv/regs-hdmi.h 4 * 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com/ 7 * 8 * HDMI register header file for Samsung TVOUT driver 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #ifndef SAMSUNG_REGS_HDMI_H 16 #define SAMSUNG_REGS_HDMI_H 17 18 /* 19 * Register part 20 */ 21 22 /* HDMI Version 1.3 & Common */ 23 #define HDMI_CTRL_BASE(x) ((x) + 0x00000000) 24 #define HDMI_CORE_BASE(x) ((x) + 0x00010000) 25 #define HDMI_I2S_BASE(x) ((x) + 0x00040000) 26 #define HDMI_TG_BASE(x) ((x) + 0x00050000) 27 28 /* Control registers */ 29 #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) 30 #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) 31 #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) 32 #define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) 33 #define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018) 34 #define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C) 35 #define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) 36 37 /* Core registers */ 38 #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) 39 #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) 40 #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) 41 #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) 42 #define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014) 43 #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) 44 #define HDMI_HPD HDMI_CORE_BASE(0x0030) 45 #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) 46 #define HDMI_ENC_EN HDMI_CORE_BASE(0x0044) 47 #define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) 48 #define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) 49 #define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) 50 #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) 51 #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) 52 #define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0) 53 #define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4) 54 #define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8) 55 #define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) 56 #define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) 57 #define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) 58 #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) 59 #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) 60 #define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) 61 #define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) 62 #define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) 63 #define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) 64 #define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) 65 #define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) 66 #define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) 67 #define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) 68 #define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) 69 #define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) 70 #define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) 71 #define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) 72 #define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) 73 #define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) 74 #define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) 75 #define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) 76 #define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300) 77 #define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) 78 #define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0) 79 #define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) 80 #define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8) 81 #define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360) 82 #define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400) 83 84 /* Timing generator registers */ 85 #define HDMI_TG_CMD HDMI_TG_BASE(0x0000) 86 #define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018) 87 #define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C) 88 #define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020) 89 #define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024) 90 #define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028) 91 #define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C) 92 #define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030) 93 #define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034) 94 #define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038) 95 #define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C) 96 #define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040) 97 #define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044) 98 #define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048) 99 #define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C) 100 #define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050) 101 #define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054) 102 #define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058) 103 #define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C) 104 #define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060) 105 #define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064) 106 #define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078) 107 #define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C) 108 #define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080) 109 #define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084) 110 #define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088) 111 #define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C) 112 #define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090) 113 #define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094) 114 115 /* 116 * Bit definition part 117 */ 118 119 /* HDMI_INTC_CON */ 120 #define HDMI_INTC_EN_GLOBAL (1 << 6) 121 #define HDMI_INTC_EN_HPD_PLUG (1 << 3) 122 #define HDMI_INTC_EN_HPD_UNPLUG (1 << 2) 123 124 /* HDMI_INTC_FLAG */ 125 #define HDMI_INTC_FLAG_HPD_PLUG (1 << 3) 126 #define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2) 127 128 /* HDMI_PHY_RSTOUT */ 129 #define HDMI_PHY_SW_RSTOUT (1 << 0) 130 131 /* HDMI_CORE_RSTOUT */ 132 #define HDMI_CORE_SW_RSTOUT (1 << 0) 133 134 /* HDMI_CON_0 */ 135 #define HDMI_BLUE_SCR_EN (1 << 5) 136 #define HDMI_ASP_EN (1 << 2) 137 #define HDMI_ASP_DIS (0 << 2) 138 #define HDMI_ASP_MASK (1 << 2) 139 #define HDMI_EN (1 << 0) 140 141 /* HDMI_CON_2 */ 142 #define HDMI_VID_PREAMBLE_DIS (1 << 5) 143 #define HDMI_GUARD_BAND_DIS (1 << 1) 144 145 /* HDMI_PHY_STATUS */ 146 #define HDMI_PHY_STATUS_READY (1 << 0) 147 148 /* HDMI_MODE_SEL */ 149 #define HDMI_MODE_HDMI_EN (1 << 1) 150 #define HDMI_MODE_DVI_EN (1 << 0) 151 #define HDMI_MODE_MASK (3 << 0) 152 153 /* HDMI_TG_CMD */ 154 #define HDMI_TG_EN (1 << 0) 155 #define HDMI_FIELD_EN (1 << 1) 156 157 158 /* HDMI Version 1.4 */ 159 /* Control registers */ 160 /* #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) */ 161 /* #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) */ 162 #define HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008) 163 /* #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) */ 164 #define HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010) 165 #define HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014) 166 #define HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020) 167 #define HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024) 168 #define HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028) 169 #define HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030) 170 #define HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040) 171 #define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044) 172 #define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050) 173 #define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070) 174 #define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0074) 175 #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078) 176 #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C) 177 #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080) 178 179 /* PHY Control bit definition */ 180 181 /* HDMI_PHY_CON_0 */ 182 #define HDMI_PHY_POWER_OFF_EN (1 << 0) 183 184 /* Video related registers */ 185 #define HDMI_YMAX HDMI_CORE_BASE(0x0060) 186 #define HDMI_YMIN HDMI_CORE_BASE(0x0064) 187 #define HDMI_CMAX HDMI_CORE_BASE(0x0068) 188 #define HDMI_CMIN HDMI_CORE_BASE(0x006C) 189 190 #define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0) 191 #define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4) 192 #define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8) 193 #define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC) 194 195 #define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0) 196 #define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4) 197 #define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8) 198 #define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC) 199 200 #define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0) 201 202 #define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110) 203 #define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114) 204 #define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118) 205 #define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C) 206 207 #define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120) 208 #define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124) 209 #define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128) 210 #define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C) 211 212 #define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130) 213 #define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134) 214 #define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138) 215 #define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C) 216 217 #define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140) 218 #define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144) 219 #define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148) 220 #define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C) 221 222 #define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150) 223 #define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154) 224 #define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158) 225 #define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C) 226 227 #define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160) 228 #define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164) 229 #define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168) 230 #define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C) 231 #define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170) 232 #define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174) 233 #define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178) 234 #define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C) 235 236 #define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180) 237 #define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184) 238 #define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188) 239 #define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C) 240 #define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190) 241 #define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194) 242 #define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198) 243 #define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C) 244 245 #define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0) 246 #define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4) 247 #define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8) 248 #define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC) 249 #define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0) 250 #define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4) 251 #define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8) 252 #define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC) 253 254 #define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0) 255 #define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4) 256 #define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8) 257 #define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC) 258 #define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0) 259 #define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4) 260 #define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8) 261 #define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC) 262 #define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0) 263 #define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4) 264 #define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8) 265 #define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC) 266 267 #define HDMI_GCP_CON HDMI_CORE_BASE(0x0200) 268 #define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210) 269 #define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214) 270 #define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218) 271 272 /* Audio related registers */ 273 #define HDMI_ASP_CON HDMI_CORE_BASE(0x0300) 274 #define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304) 275 #define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310) 276 #define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314) 277 #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318) 278 #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C) 279 280 #define HDMI_ACR_CON HDMI_CORE_BASE(0x0400) 281 #define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410) 282 #define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414) 283 #define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418) 284 #define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420) 285 #define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424) 286 #define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428) 287 #define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430) 288 #define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434) 289 #define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438) 290 291 /* Packet related registers */ 292 #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500) 293 #define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514) 294 #define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n)) 295 296 #define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600) 297 #define HDMI_ISRC1_HEADER1 HDMI_CORE_BASE(0x0614) 298 #define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n)) 299 #define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n)) 300 301 #define HDMI_AVI_CON HDMI_CORE_BASE(0x0700) 302 #define HDMI_AVI_HEADER0 HDMI_CORE_BASE(0x0710) 303 #define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714) 304 #define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718) 305 #define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C) 306 #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1)) 307 308 #define HDMI_AUI_CON HDMI_CORE_BASE(0x0800) 309 #define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810) 310 #define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814) 311 #define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818) 312 #define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C) 313 #define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1)) 314 315 #define HDMI_MPG_CON HDMI_CORE_BASE(0x0900) 316 #define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C) 317 #define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n)) 318 319 #define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00) 320 #define HDMI_SPD_HEADER0 HDMI_CORE_BASE(0x0A10) 321 #define HDMI_SPD_HEADER1 HDMI_CORE_BASE(0x0A14) 322 #define HDMI_SPD_HEADER2 HDMI_CORE_BASE(0x0A18) 323 #define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n)) 324 325 #define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00) 326 #define HDMI_GAMUT_HEADER0 HDMI_CORE_BASE(0x0B10) 327 #define HDMI_GAMUT_HEADER1 HDMI_CORE_BASE(0x0B14) 328 #define HDMI_GAMUT_HEADER2 HDMI_CORE_BASE(0x0B18) 329 #define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n)) 330 331 #define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00) 332 #define HDMI_VSI_HEADER0 HDMI_CORE_BASE(0x0C10) 333 #define HDMI_VSI_HEADER1 HDMI_CORE_BASE(0x0C14) 334 #define HDMI_VSI_HEADER2 HDMI_CORE_BASE(0x0C18) 335 #define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n)) 336 337 #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00) 338 #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04) 339 340 #define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48) 341 #define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58) 342 #define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C) 343 #define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60) 344 #define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64) 345 346 /* AVI bit definition */ 347 #define HDMI_AVI_CON_DO_NOT_TRANSMIT (0 << 1) 348 #define HDMI_AVI_CON_EVERY_VSYNC (1 << 1) 349 350 #define AVI_ACTIVE_FORMAT_VALID (1 << 4) 351 #define AVI_UNDERSCANNED_DISPLAY_VALID (1 << 1) 352 353 /* AUI bit definition */ 354 #define HDMI_AUI_CON_NO_TRAN (0 << 0) 355 356 /* VSI bit definition */ 357 #define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0) 358 359 /* HDCP related registers */ 360 #define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n)) 361 #define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n)) 362 363 #define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064) 364 #define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070) 365 #define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080) 366 #define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084) 367 #define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090) 368 #define HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n)) 369 #define HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n)) 370 #define HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n)) 371 372 #define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100) 373 #define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110) 374 #define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114) 375 #define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140) 376 #define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144) 377 #define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180) 378 #define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190) 379 #define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0) 380 #define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0) 381 #define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0) 382 #define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4) 383 #define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0) 384 385 #define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500) 386 #define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504) 387 #define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508) 388 #define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C) 389 #define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510) 390 #define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514) 391 #define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518) 392 393 #define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520) 394 #define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524) 395 #define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528) 396 #define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C) 397 #define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530) 398 #define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534) 399 400 /* HDMI I2S register */ 401 #define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000) 402 #define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004) 403 #define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008) 404 #define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c) 405 #define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010) 406 #define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014) 407 #define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018) 408 #define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c) 409 #define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020) 410 #define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024) 411 #define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028) 412 #define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c) 413 #define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030) 414 #define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034) 415 #define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038) 416 #define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c) 417 #define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040) 418 #define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044) 419 #define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048) 420 #define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c) 421 #define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054) 422 #define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058) 423 424 /* I2S bit definition */ 425 426 /* I2S_CLK_CON */ 427 #define HDMI_I2S_CLK_DIS (0) 428 #define HDMI_I2S_CLK_EN (1) 429 430 /* I2S_CON_1 */ 431 #define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1) 432 #define HDMI_I2S_SCLK_RISING_EDGE (1 << 1) 433 #define HDMI_I2S_L_CH_LOW_POL (0) 434 #define HDMI_I2S_L_CH_HIGH_POL (1) 435 436 /* I2S_CON_2 */ 437 #define HDMI_I2S_MSB_FIRST_MODE (0 << 6) 438 #define HDMI_I2S_LSB_FIRST_MODE (1 << 6) 439 #define HDMI_I2S_BIT_CH_32FS (0 << 4) 440 #define HDMI_I2S_BIT_CH_48FS (1 << 4) 441 #define HDMI_I2S_BIT_CH_RESERVED (2 << 4) 442 #define HDMI_I2S_SDATA_16BIT (1 << 2) 443 #define HDMI_I2S_SDATA_20BIT (2 << 2) 444 #define HDMI_I2S_SDATA_24BIT (3 << 2) 445 #define HDMI_I2S_BASIC_FORMAT (0) 446 #define HDMI_I2S_L_JUST_FORMAT (2) 447 #define HDMI_I2S_R_JUST_FORMAT (3) 448 #define HDMI_I2S_CON_2_CLR (~(0xFF)) 449 #define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4) 450 #define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2) 451 452 /* I2S_PIN_SEL_0 */ 453 #define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4) 454 #define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7) 455 456 /* I2S_PIN_SEL_1 */ 457 #define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4) 458 #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7) 459 460 /* I2S_PIN_SEL_2 */ 461 #define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4) 462 #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7) 463 464 /* I2S_PIN_SEL_3 */ 465 #define HDMI_I2S_SEL_DSD(x) ((x) & 0x7) 466 467 /* I2S_DSD_CON */ 468 #define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1) 469 #define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1) 470 #define HDMI_I2S_DSD_ENABLE (1) 471 #define HDMI_I2S_DSD_DISABLE (0) 472 473 /* I2S_MUX_CON */ 474 #define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5) 475 #define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5) 476 #define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5) 477 #define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5) 478 #define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5) 479 #define HDMI_I2S_IN_DISABLE (1 << 4) 480 #define HDMI_I2S_IN_ENABLE (0 << 4) 481 #define HDMI_I2S_AUD_SPDIF (0 << 2) 482 #define HDMI_I2S_AUD_I2S (1 << 2) 483 #define HDMI_I2S_AUD_DSD (2 << 2) 484 #define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1) 485 #define HDMI_I2S_CUV_I2S_ENABLE (1 << 1) 486 #define HDMI_I2S_MUX_DISABLE (0) 487 #define HDMI_I2S_MUX_ENABLE (1) 488 #define HDMI_I2S_MUX_CON_CLR (~(0xFF)) 489 490 /* I2S_CH_ST_CON */ 491 #define HDMI_I2S_CH_STATUS_RELOAD (1) 492 #define HDMI_I2S_CH_ST_CON_CLR (~(1)) 493 494 /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */ 495 #define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6) 496 #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3) 497 #define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3) 498 #define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3) 499 #define HDMI_I2S_COPYRIGHT (0 << 2) 500 #define HDMI_I2S_NO_COPYRIGHT (1 << 2) 501 #define HDMI_I2S_LINEAR_PCM (0 << 1) 502 #define HDMI_I2S_NO_LINEAR_PCM (1 << 1) 503 #define HDMI_I2S_CONSUMER_FORMAT (0) 504 #define HDMI_I2S_PROF_FORMAT (1) 505 #define HDMI_I2S_CH_ST_0_CLR (~(0xFF)) 506 507 /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */ 508 #define HDMI_I2S_CD_PLAYER (0x00) 509 #define HDMI_I2S_DAT_PLAYER (0x03) 510 #define HDMI_I2S_DCC_PLAYER (0x43) 511 #define HDMI_I2S_MINI_DISC_PLAYER (0x49) 512 513 /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */ 514 #define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4) 515 #define HDMI_I2S_SOURCE_NUM_MASK (0xF) 516 #define HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4) 517 #define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF)) 518 519 /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */ 520 #define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4) 521 #define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4) 522 #define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4) 523 #define HDMI_I2S_SMP_FREQ_44_1 (0x0) 524 #define HDMI_I2S_SMP_FREQ_48 (0x2) 525 #define HDMI_I2S_SMP_FREQ_32 (0x3) 526 #define HDMI_I2S_SMP_FREQ_96 (0xA) 527 #define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF)) 528 529 /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */ 530 #define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4) 531 #define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4) 532 #define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4) 533 #define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4) 534 #define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1) 535 #define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1) 536 #define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1) 537 #define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1) 538 #define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1) 539 #define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1) 540 #define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1) 541 #define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1) 542 #define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1) 543 #define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1) 544 #define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1) 545 #define HDMI_I2S_WORD_LEN_MAX_24BITS (1) 546 #define HDMI_I2S_WORD_LEN_MAX_20BITS (0) 547 548 /* I2S_MUX_CH */ 549 #define HDMI_I2S_CH3_R_EN (1 << 7) 550 #define HDMI_I2S_CH3_L_EN (1 << 6) 551 #define HDMI_I2S_CH3_EN (3 << 6) 552 #define HDMI_I2S_CH2_R_EN (1 << 5) 553 #define HDMI_I2S_CH2_L_EN (1 << 4) 554 #define HDMI_I2S_CH2_EN (3 << 4) 555 #define HDMI_I2S_CH1_R_EN (1 << 3) 556 #define HDMI_I2S_CH1_L_EN (1 << 2) 557 #define HDMI_I2S_CH1_EN (3 << 2) 558 #define HDMI_I2S_CH0_R_EN (1 << 1) 559 #define HDMI_I2S_CH0_L_EN (1) 560 #define HDMI_I2S_CH0_EN (3) 561 #define HDMI_I2S_CH_ALL_EN (0xFF) 562 #define HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN) 563 564 /* I2S_MUX_CUV */ 565 #define HDMI_I2S_CUV_R_EN (1 << 1) 566 #define HDMI_I2S_CUV_L_EN (1) 567 #define HDMI_I2S_CUV_RL_EN (0x03) 568 569 /* I2S_CUV_L_R */ 570 #define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4) 571 #define HDMI_I2S_CUV_L_DATA_MASK (0x7) 572 573 /* Timing generator registers */ 574 /* TG configure/status registers */ 575 #define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068) 576 #define HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c) 577 #define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070) 578 #define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074) 579 #define HDMI_TG_3D HDMI_TG_BASE(0x00F0) 580 581 /* HDMI PHY Registers Offsets*/ 582 #define HDMIPHY_POWER (0x74 >> 2) 583 #define HDMIPHY_MODE_SET_DONE (0x7c >> 2) 584 585 /* HDMI PHY Values */ 586 #define HDMI_PHY_POWER_ON 0x80 587 #define HDMI_PHY_POWER_OFF 0xff 588 589 /* HDMI PHY Values */ 590 #define HDMI_PHY_DISABLE_MODE_SET 0x80 591 #define HDMI_PHY_ENABLE_MODE_SET 0x00 592 593 /* PMU Registers for PHY */ 594 #define PMU_HDMI_PHY_CONTROL 0x700 595 #define PMU_HDMI_PHY_ENABLE_BIT BIT(0) 596 597 #endif /* SAMSUNG_REGS_HDMI_H */ 598