1 /* 2 * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 * Authors: 4 * Seung-Woo Kim <sw0312.kim@samsung.com> 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * 8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include <drm/drmP.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_atomic_helper.h> 21 22 #include "regs-hdmi.h" 23 24 #include <linux/kernel.h> 25 #include <linux/wait.h> 26 #include <linux/i2c.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/irq.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/clk.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/io.h> 36 #include <linux/of_address.h> 37 #include <linux/of_device.h> 38 #include <linux/of_graph.h> 39 #include <linux/hdmi.h> 40 #include <linux/component.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/regmap.h> 43 44 #include <drm/exynos_drm.h> 45 46 #include "exynos_drm_drv.h" 47 #include "exynos_drm_crtc.h" 48 49 #define HOTPLUG_DEBOUNCE_MS 1100 50 51 enum hdmi_type { 52 HDMI_TYPE13, 53 HDMI_TYPE14, 54 HDMI_TYPE_COUNT 55 }; 56 57 #define HDMI_MAPPED_BASE 0xffff0000 58 59 enum hdmi_mapped_regs { 60 HDMI_PHY_STATUS = HDMI_MAPPED_BASE, 61 HDMI_PHY_RSTOUT, 62 HDMI_ACR_CON, 63 HDMI_ACR_MCTS0, 64 HDMI_ACR_CTS0, 65 HDMI_ACR_N0 66 }; 67 68 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = { 69 { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 }, 70 { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT }, 71 { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON }, 72 { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 }, 73 { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 }, 74 { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 }, 75 }; 76 77 static const char * const supply[] = { 78 "vdd", 79 "vdd_osc", 80 "vdd_pll", 81 }; 82 83 struct hdmiphy_config { 84 int pixel_clock; 85 u8 conf[32]; 86 }; 87 88 struct hdmiphy_configs { 89 int count; 90 const struct hdmiphy_config *data; 91 }; 92 93 struct string_array_spec { 94 int count; 95 const char * const *data; 96 }; 97 98 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a } 99 100 struct hdmi_driver_data { 101 unsigned int type; 102 unsigned int is_apb_phy:1; 103 unsigned int has_sysreg:1; 104 struct hdmiphy_configs phy_confs; 105 struct string_array_spec clk_gates; 106 /* 107 * Array of triplets (p_off, p_on, clock), where p_off and p_on are 108 * required parents of clock when HDMI-PHY is respectively off or on. 109 */ 110 struct string_array_spec clk_muxes; 111 }; 112 113 struct hdmi_context { 114 struct drm_encoder encoder; 115 struct device *dev; 116 struct drm_device *drm_dev; 117 struct drm_connector connector; 118 bool powered; 119 bool dvi_mode; 120 struct delayed_work hotplug_work; 121 struct drm_display_mode current_mode; 122 const struct hdmi_driver_data *drv_data; 123 124 void __iomem *regs; 125 void __iomem *regs_hdmiphy; 126 struct i2c_client *hdmiphy_port; 127 struct i2c_adapter *ddc_adpt; 128 struct gpio_desc *hpd_gpio; 129 int irq; 130 struct regmap *pmureg; 131 struct regmap *sysreg; 132 struct clk **clk_gates; 133 struct clk **clk_muxes; 134 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; 135 struct regulator *reg_hdmi_en; 136 struct exynos_drm_clk phy_clk; 137 struct drm_bridge *bridge; 138 }; 139 140 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) 141 { 142 return container_of(e, struct hdmi_context, encoder); 143 } 144 145 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c) 146 { 147 return container_of(c, struct hdmi_context, connector); 148 } 149 150 static const struct hdmiphy_config hdmiphy_v13_configs[] = { 151 { 152 .pixel_clock = 27000000, 153 .conf = { 154 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 155 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 156 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 157 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 158 }, 159 }, 160 { 161 .pixel_clock = 27027000, 162 .conf = { 163 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 164 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 165 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 166 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 167 }, 168 }, 169 { 170 .pixel_clock = 74176000, 171 .conf = { 172 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 173 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 174 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 175 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80, 176 }, 177 }, 178 { 179 .pixel_clock = 74250000, 180 .conf = { 181 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 182 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 183 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, 184 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80, 185 }, 186 }, 187 { 188 .pixel_clock = 148500000, 189 .conf = { 190 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 191 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 192 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, 193 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80, 194 }, 195 }, 196 }; 197 198 static const struct hdmiphy_config hdmiphy_v14_configs[] = { 199 { 200 .pixel_clock = 25200000, 201 .conf = { 202 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08, 203 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 204 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 205 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 206 }, 207 }, 208 { 209 .pixel_clock = 27000000, 210 .conf = { 211 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20, 212 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, 213 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 214 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 215 }, 216 }, 217 { 218 .pixel_clock = 27027000, 219 .conf = { 220 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, 221 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 222 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 223 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 224 }, 225 }, 226 { 227 .pixel_clock = 36000000, 228 .conf = { 229 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08, 230 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 231 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 232 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 233 }, 234 }, 235 { 236 .pixel_clock = 40000000, 237 .conf = { 238 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08, 239 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 240 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 241 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 242 }, 243 }, 244 { 245 .pixel_clock = 65000000, 246 .conf = { 247 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08, 248 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, 249 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 250 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 251 }, 252 }, 253 { 254 .pixel_clock = 71000000, 255 .conf = { 256 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08, 257 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 258 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 259 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 260 }, 261 }, 262 { 263 .pixel_clock = 73250000, 264 .conf = { 265 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08, 266 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 267 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 268 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 269 }, 270 }, 271 { 272 .pixel_clock = 74176000, 273 .conf = { 274 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, 275 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 276 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 277 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 278 }, 279 }, 280 { 281 .pixel_clock = 74250000, 282 .conf = { 283 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, 284 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 285 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 286 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 287 }, 288 }, 289 { 290 .pixel_clock = 83500000, 291 .conf = { 292 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08, 293 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 294 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 295 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 296 }, 297 }, 298 { 299 .pixel_clock = 106500000, 300 .conf = { 301 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, 302 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 303 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 304 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 305 }, 306 }, 307 { 308 .pixel_clock = 108000000, 309 .conf = { 310 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08, 311 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 312 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 313 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 314 }, 315 }, 316 { 317 .pixel_clock = 115500000, 318 .conf = { 319 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08, 320 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, 321 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 322 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 323 }, 324 }, 325 { 326 .pixel_clock = 119000000, 327 .conf = { 328 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08, 329 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 330 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 331 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 332 }, 333 }, 334 { 335 .pixel_clock = 146250000, 336 .conf = { 337 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, 338 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 339 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 340 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 341 }, 342 }, 343 { 344 .pixel_clock = 148500000, 345 .conf = { 346 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, 347 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 348 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 349 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 350 }, 351 }, 352 }; 353 354 static const struct hdmiphy_config hdmiphy_5420_configs[] = { 355 { 356 .pixel_clock = 25200000, 357 .conf = { 358 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8, 359 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 360 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66, 361 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 362 }, 363 }, 364 { 365 .pixel_clock = 27000000, 366 .conf = { 367 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0, 368 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 369 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 370 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 371 }, 372 }, 373 { 374 .pixel_clock = 27027000, 375 .conf = { 376 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8, 377 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 378 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 379 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 380 }, 381 }, 382 { 383 .pixel_clock = 36000000, 384 .conf = { 385 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8, 386 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 387 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 388 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 389 }, 390 }, 391 { 392 .pixel_clock = 40000000, 393 .conf = { 394 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8, 395 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 396 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 397 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 398 }, 399 }, 400 { 401 .pixel_clock = 65000000, 402 .conf = { 403 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8, 404 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 405 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 406 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 407 }, 408 }, 409 { 410 .pixel_clock = 71000000, 411 .conf = { 412 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8, 413 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 414 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 415 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 416 }, 417 }, 418 { 419 .pixel_clock = 73250000, 420 .conf = { 421 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8, 422 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 423 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 424 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 425 }, 426 }, 427 { 428 .pixel_clock = 74176000, 429 .conf = { 430 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, 431 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 432 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 433 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 434 }, 435 }, 436 { 437 .pixel_clock = 74250000, 438 .conf = { 439 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08, 440 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 441 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 442 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 443 }, 444 }, 445 { 446 .pixel_clock = 83500000, 447 .conf = { 448 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8, 449 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 450 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 451 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 452 }, 453 }, 454 { 455 .pixel_clock = 88750000, 456 .conf = { 457 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8, 458 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 459 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 460 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 461 }, 462 }, 463 { 464 .pixel_clock = 106500000, 465 .conf = { 466 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8, 467 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 468 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 469 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 470 }, 471 }, 472 { 473 .pixel_clock = 108000000, 474 .conf = { 475 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, 476 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 477 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 478 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 479 }, 480 }, 481 { 482 .pixel_clock = 115500000, 483 .conf = { 484 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8, 485 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 486 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 487 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 488 }, 489 }, 490 { 491 .pixel_clock = 146250000, 492 .conf = { 493 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8, 494 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 495 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 496 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 497 }, 498 }, 499 { 500 .pixel_clock = 148500000, 501 .conf = { 502 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08, 503 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 504 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 505 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80, 506 }, 507 }, 508 }; 509 510 static const struct hdmiphy_config hdmiphy_5433_configs[] = { 511 { 512 .pixel_clock = 27000000, 513 .conf = { 514 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02, 515 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 516 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 517 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 518 }, 519 }, 520 { 521 .pixel_clock = 27027000, 522 .conf = { 523 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3, 524 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 525 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 526 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 527 }, 528 }, 529 { 530 .pixel_clock = 40000000, 531 .conf = { 532 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02, 533 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 534 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 535 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 536 }, 537 }, 538 { 539 .pixel_clock = 50000000, 540 .conf = { 541 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3, 542 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 543 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 544 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 545 }, 546 }, 547 { 548 .pixel_clock = 65000000, 549 .conf = { 550 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6, 551 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 552 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 553 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 554 }, 555 }, 556 { 557 .pixel_clock = 74176000, 558 .conf = { 559 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42, 560 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 561 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 562 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 563 }, 564 }, 565 { 566 .pixel_clock = 74250000, 567 .conf = { 568 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2, 569 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 570 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 571 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 572 }, 573 }, 574 { 575 .pixel_clock = 108000000, 576 .conf = { 577 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02, 578 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 579 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 580 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 581 }, 582 }, 583 { 584 .pixel_clock = 148500000, 585 .conf = { 586 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1, 587 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5, 588 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30, 589 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, 590 }, 591 }, 592 { 593 .pixel_clock = 297000000, 594 .conf = { 595 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2, 596 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 597 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 598 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 599 }, 600 }, 601 }; 602 603 static const char * const hdmi_clk_gates4[] = { 604 "hdmi", "sclk_hdmi" 605 }; 606 607 static const char * const hdmi_clk_muxes4[] = { 608 "sclk_pixel", "sclk_hdmiphy", "mout_hdmi" 609 }; 610 611 static const char * const hdmi_clk_gates5433[] = { 612 "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk" 613 }; 614 615 static const char * const hdmi_clk_muxes5433[] = { 616 "oscclk", "tmds_clko", "tmds_clko_user", 617 "oscclk", "pixel_clko", "pixel_clko_user" 618 }; 619 620 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = { 621 .type = HDMI_TYPE13, 622 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs), 623 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 624 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 625 }; 626 627 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = { 628 .type = HDMI_TYPE14, 629 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs), 630 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 631 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 632 }; 633 634 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = { 635 .type = HDMI_TYPE14, 636 .is_apb_phy = 1, 637 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs), 638 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 639 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 640 }; 641 642 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = { 643 .type = HDMI_TYPE14, 644 .is_apb_phy = 1, 645 .has_sysreg = 1, 646 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs), 647 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433), 648 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433), 649 }; 650 651 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id) 652 { 653 if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE) 654 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type]; 655 return reg_id; 656 } 657 658 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id) 659 { 660 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id)); 661 } 662 663 static inline void hdmi_reg_writeb(struct hdmi_context *hdata, 664 u32 reg_id, u8 value) 665 { 666 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id)); 667 } 668 669 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, 670 int bytes, u32 val) 671 { 672 reg_id = hdmi_map_reg(hdata, reg_id); 673 674 while (--bytes >= 0) { 675 writel(val & 0xff, hdata->regs + reg_id); 676 val >>= 8; 677 reg_id += 4; 678 } 679 } 680 681 static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id, 682 u8 *buf, int size) 683 { 684 for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4) 685 writel(*buf++, hdata->regs + reg_id); 686 } 687 688 static inline void hdmi_reg_writemask(struct hdmi_context *hdata, 689 u32 reg_id, u32 value, u32 mask) 690 { 691 u32 old; 692 693 reg_id = hdmi_map_reg(hdata, reg_id); 694 old = readl(hdata->regs + reg_id); 695 value = (value & mask) | (old & ~mask); 696 writel(value, hdata->regs + reg_id); 697 } 698 699 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, 700 u32 reg_offset, const u8 *buf, u32 len) 701 { 702 if ((reg_offset + len) > 32) 703 return -EINVAL; 704 705 if (hdata->hdmiphy_port) { 706 int ret; 707 708 ret = i2c_master_send(hdata->hdmiphy_port, buf, len); 709 if (ret == len) 710 return 0; 711 return ret; 712 } else { 713 int i; 714 for (i = 0; i < len; i++) 715 writel(buf[i], hdata->regs_hdmiphy + 716 ((reg_offset + i)<<2)); 717 return 0; 718 } 719 } 720 721 static int hdmi_clk_enable_gates(struct hdmi_context *hdata) 722 { 723 int i, ret; 724 725 for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) { 726 ret = clk_prepare_enable(hdata->clk_gates[i]); 727 if (!ret) 728 continue; 729 730 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n", 731 hdata->drv_data->clk_gates.data[i], ret); 732 while (i--) 733 clk_disable_unprepare(hdata->clk_gates[i]); 734 return ret; 735 } 736 737 return 0; 738 } 739 740 static void hdmi_clk_disable_gates(struct hdmi_context *hdata) 741 { 742 int i = hdata->drv_data->clk_gates.count; 743 744 while (i--) 745 clk_disable_unprepare(hdata->clk_gates[i]); 746 } 747 748 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy) 749 { 750 struct device *dev = hdata->dev; 751 int ret = 0; 752 int i; 753 754 for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) { 755 struct clk **c = &hdata->clk_muxes[i]; 756 757 ret = clk_set_parent(c[2], c[to_phy]); 758 if (!ret) 759 continue; 760 761 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n", 762 hdata->drv_data->clk_muxes.data[i + 2], 763 hdata->drv_data->clk_muxes.data[i + to_phy], ret); 764 } 765 766 return ret; 767 } 768 769 static void hdmi_reg_infoframes(struct hdmi_context *hdata) 770 { 771 union hdmi_infoframe frm; 772 u8 buf[25]; 773 int ret; 774 775 if (hdata->dvi_mode) { 776 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 777 HDMI_AVI_CON_DO_NOT_TRANSMIT); 778 hdmi_reg_writeb(hdata, HDMI_VSI_CON, 779 HDMI_VSI_CON_DO_NOT_TRANSMIT); 780 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN); 781 return; 782 } 783 784 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 785 &hdata->current_mode); 786 if (!ret) 787 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); 788 if (ret > 0) { 789 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC); 790 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret); 791 } else { 792 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); 793 } 794 795 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, 796 &hdata->current_mode); 797 if (!ret) 798 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, 799 sizeof(buf)); 800 if (ret > 0) { 801 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC); 802 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3); 803 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3); 804 } 805 806 ret = hdmi_audio_infoframe_init(&frm.audio); 807 if (!ret) { 808 frm.audio.channels = 2; 809 ret = hdmi_audio_infoframe_pack(&frm.audio, buf, sizeof(buf)); 810 } 811 if (ret > 0) { 812 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); 813 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, ret); 814 } 815 } 816 817 static enum drm_connector_status hdmi_detect(struct drm_connector *connector, 818 bool force) 819 { 820 struct hdmi_context *hdata = connector_to_hdmi(connector); 821 822 if (gpiod_get_value(hdata->hpd_gpio)) 823 return connector_status_connected; 824 825 return connector_status_disconnected; 826 } 827 828 static void hdmi_connector_destroy(struct drm_connector *connector) 829 { 830 drm_connector_unregister(connector); 831 drm_connector_cleanup(connector); 832 } 833 834 static const struct drm_connector_funcs hdmi_connector_funcs = { 835 .dpms = drm_atomic_helper_connector_dpms, 836 .fill_modes = drm_helper_probe_single_connector_modes, 837 .detect = hdmi_detect, 838 .destroy = hdmi_connector_destroy, 839 .reset = drm_atomic_helper_connector_reset, 840 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 841 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 842 }; 843 844 static int hdmi_get_modes(struct drm_connector *connector) 845 { 846 struct hdmi_context *hdata = connector_to_hdmi(connector); 847 struct edid *edid; 848 int ret; 849 850 if (!hdata->ddc_adpt) 851 return -ENODEV; 852 853 edid = drm_get_edid(connector, hdata->ddc_adpt); 854 if (!edid) 855 return -ENODEV; 856 857 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); 858 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n", 859 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"), 860 edid->width_cm, edid->height_cm); 861 862 drm_mode_connector_update_edid_property(connector, edid); 863 864 ret = drm_add_edid_modes(connector, edid); 865 866 kfree(edid); 867 868 return ret; 869 } 870 871 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) 872 { 873 const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs; 874 int i; 875 876 for (i = 0; i < confs->count; i++) 877 if (confs->data[i].pixel_clock == pixel_clock) 878 return i; 879 880 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock); 881 return -EINVAL; 882 } 883 884 static int hdmi_mode_valid(struct drm_connector *connector, 885 struct drm_display_mode *mode) 886 { 887 struct hdmi_context *hdata = connector_to_hdmi(connector); 888 int ret; 889 890 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 891 mode->hdisplay, mode->vdisplay, mode->vrefresh, 892 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true : 893 false, mode->clock * 1000); 894 895 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000); 896 if (ret < 0) 897 return MODE_BAD; 898 899 return MODE_OK; 900 } 901 902 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { 903 .get_modes = hdmi_get_modes, 904 .mode_valid = hdmi_mode_valid, 905 }; 906 907 static int hdmi_create_connector(struct drm_encoder *encoder) 908 { 909 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 910 struct drm_connector *connector = &hdata->connector; 911 int ret; 912 913 connector->interlace_allowed = true; 914 connector->polled = DRM_CONNECTOR_POLL_HPD; 915 916 ret = drm_connector_init(hdata->drm_dev, connector, 917 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); 918 if (ret) { 919 DRM_ERROR("Failed to initialize connector with drm\n"); 920 return ret; 921 } 922 923 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); 924 drm_connector_register(connector); 925 drm_mode_connector_attach_encoder(connector, encoder); 926 927 if (hdata->bridge) { 928 encoder->bridge = hdata->bridge; 929 hdata->bridge->encoder = encoder; 930 ret = drm_bridge_attach(encoder, hdata->bridge, NULL); 931 if (ret) 932 DRM_ERROR("Failed to attach bridge\n"); 933 } 934 935 return ret; 936 } 937 938 static bool hdmi_mode_fixup(struct drm_encoder *encoder, 939 const struct drm_display_mode *mode, 940 struct drm_display_mode *adjusted_mode) 941 { 942 struct drm_device *dev = encoder->dev; 943 struct drm_connector *connector; 944 struct drm_display_mode *m; 945 int mode_ok; 946 947 drm_mode_set_crtcinfo(adjusted_mode, 0); 948 949 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 950 if (connector->encoder == encoder) 951 break; 952 } 953 954 if (connector->encoder != encoder) 955 return true; 956 957 mode_ok = hdmi_mode_valid(connector, adjusted_mode); 958 959 if (mode_ok == MODE_OK) 960 return true; 961 962 /* 963 * Find the most suitable mode and copy it to adjusted_mode. 964 */ 965 list_for_each_entry(m, &connector->modes, head) { 966 mode_ok = hdmi_mode_valid(connector, m); 967 968 if (mode_ok == MODE_OK) { 969 DRM_INFO("desired mode doesn't exist so\n"); 970 DRM_INFO("use the most suitable mode among modes.\n"); 971 972 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n", 973 m->hdisplay, m->vdisplay, m->vrefresh); 974 975 drm_mode_copy(adjusted_mode, m); 976 break; 977 } 978 } 979 980 return true; 981 } 982 983 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq) 984 { 985 u32 n, cts; 986 987 cts = (freq % 9) ? 27000 : 30000; 988 n = 128 * freq / (27000000 / cts); 989 990 hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n); 991 hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts); 992 hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts); 993 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); 994 } 995 996 static void hdmi_audio_init(struct hdmi_context *hdata) 997 { 998 u32 sample_rate, bits_per_sample; 999 u32 data_num, bit_ch, sample_frq; 1000 u32 val; 1001 1002 sample_rate = 44100; 1003 bits_per_sample = 16; 1004 1005 switch (bits_per_sample) { 1006 case 20: 1007 data_num = 2; 1008 bit_ch = 1; 1009 break; 1010 case 24: 1011 data_num = 3; 1012 bit_ch = 1; 1013 break; 1014 default: 1015 data_num = 1; 1016 bit_ch = 0; 1017 break; 1018 } 1019 1020 hdmi_reg_acr(hdata, sample_rate); 1021 1022 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE 1023 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE 1024 | HDMI_I2S_MUX_ENABLE); 1025 1026 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN 1027 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); 1028 1029 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); 1030 1031 sample_frq = (sample_rate == 44100) ? 0 : 1032 (sample_rate == 48000) ? 2 : 1033 (sample_rate == 32000) ? 3 : 1034 (sample_rate == 96000) ? 0xa : 0x0; 1035 1036 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); 1037 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); 1038 1039 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; 1040 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); 1041 1042 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */ 1043 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5) 1044 | HDMI_I2S_SEL_LRCK(6)); 1045 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1) 1046 | HDMI_I2S_SEL_SDATA2(4)); 1047 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1) 1048 | HDMI_I2S_SEL_SDATA2(2)); 1049 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0)); 1050 1051 /* I2S_CON_1 & 2 */ 1052 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE 1053 | HDMI_I2S_L_CH_LOW_POL); 1054 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE 1055 | HDMI_I2S_SET_BIT_CH(bit_ch) 1056 | HDMI_I2S_SET_SDATA_BIT(data_num) 1057 | HDMI_I2S_BASIC_FORMAT); 1058 1059 /* Configure register related to CUV information */ 1060 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0 1061 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH 1062 | HDMI_I2S_COPYRIGHT 1063 | HDMI_I2S_LINEAR_PCM 1064 | HDMI_I2S_CONSUMER_FORMAT); 1065 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER); 1066 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0)); 1067 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2 1068 | HDMI_I2S_SET_SMP_FREQ(sample_frq)); 1069 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4, 1070 HDMI_I2S_ORG_SMP_FREQ_44_1 1071 | HDMI_I2S_WORD_LEN_MAX24_24BITS 1072 | HDMI_I2S_WORD_LEN_MAX_24BITS); 1073 1074 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); 1075 } 1076 1077 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff) 1078 { 1079 if (hdata->dvi_mode) 1080 return; 1081 1082 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0); 1083 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ? 1084 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); 1085 } 1086 1087 static void hdmi_start(struct hdmi_context *hdata, bool start) 1088 { 1089 u32 val = start ? HDMI_TG_EN : 0; 1090 1091 if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE) 1092 val |= HDMI_FIELD_EN; 1093 1094 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); 1095 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN); 1096 } 1097 1098 static void hdmi_conf_init(struct hdmi_context *hdata) 1099 { 1100 /* disable HPD interrupts from HDMI IP block, use GPIO instead */ 1101 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL | 1102 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); 1103 1104 /* choose HDMI mode */ 1105 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1106 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); 1107 /* apply video pre-amble and guard band in HDMI mode only */ 1108 hdmi_reg_writeb(hdata, HDMI_CON_2, 0); 1109 /* disable bluescreen */ 1110 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); 1111 1112 if (hdata->dvi_mode) { 1113 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1114 HDMI_MODE_DVI_EN, HDMI_MODE_MASK); 1115 hdmi_reg_writeb(hdata, HDMI_CON_2, 1116 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS); 1117 } 1118 1119 if (hdata->drv_data->type == HDMI_TYPE13) { 1120 /* choose bluescreen (fecal) color */ 1121 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12); 1122 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34); 1123 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56); 1124 1125 /* enable AVI packet every vsync, fixes purple line problem */ 1126 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02); 1127 /* force RGB, look to CEA-861-D, table 7 for more detail */ 1128 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5); 1129 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5); 1130 1131 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02); 1132 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); 1133 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); 1134 } else { 1135 hdmi_reg_infoframes(hdata); 1136 1137 /* enable AVI packet every vsync, fixes purple line problem */ 1138 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5); 1139 } 1140 } 1141 1142 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata) 1143 { 1144 int tries; 1145 1146 for (tries = 0; tries < 10; ++tries) { 1147 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); 1148 1149 if (val & HDMI_PHY_STATUS_READY) { 1150 DRM_DEBUG_KMS("PLL stabilized after %d tries\n", tries); 1151 return; 1152 } 1153 usleep_range(10, 20); 1154 } 1155 1156 DRM_ERROR("PLL could not reach steady state\n"); 1157 } 1158 1159 static void hdmi_v13_mode_apply(struct hdmi_context *hdata) 1160 { 1161 struct drm_display_mode *m = &hdata->current_mode; 1162 unsigned int val; 1163 1164 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1165 hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3, 1166 (m->htotal << 12) | m->vtotal); 1167 1168 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 1169 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val); 1170 1171 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; 1172 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val); 1173 1174 val = (m->hsync_start - m->hdisplay - 2); 1175 val |= ((m->hsync_end - m->hdisplay - 2) << 10); 1176 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20; 1177 hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val); 1178 1179 /* 1180 * Quirk requirement for exynos HDMI IP design, 1181 * 2 pixels less than the actual calculation for hsync_start 1182 * and end. 1183 */ 1184 1185 /* Following values & calculations differ for different type of modes */ 1186 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1187 val = ((m->vsync_end - m->vdisplay) / 2); 1188 val |= ((m->vsync_start - m->vdisplay) / 2) << 12; 1189 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1190 1191 val = m->vtotal / 2; 1192 val |= ((m->vtotal - m->vdisplay) / 2) << 11; 1193 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1194 1195 val = (m->vtotal + 1196 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2; 1197 val |= m->vtotal << 11; 1198 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val); 1199 1200 val = ((m->vtotal / 2) + 7); 1201 val |= ((m->vtotal / 2) + 2) << 12; 1202 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val); 1203 1204 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1205 val |= ((m->htotal / 2) + 1206 (m->hsync_start - m->hdisplay)) << 12; 1207 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val); 1208 1209 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1210 (m->vtotal - m->vdisplay) / 2); 1211 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1212 1213 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249); 1214 } else { 1215 val = m->vtotal; 1216 val |= (m->vtotal - m->vdisplay) << 11; 1217 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1218 1219 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0); 1220 1221 val = (m->vsync_end - m->vdisplay); 1222 val |= ((m->vsync_start - m->vdisplay) << 12); 1223 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1224 1225 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001); 1226 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001); 1227 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1228 m->vtotal - m->vdisplay); 1229 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1230 } 1231 1232 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1233 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); 1234 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); 1235 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1236 } 1237 1238 static void hdmi_v14_mode_apply(struct hdmi_context *hdata) 1239 { 1240 struct drm_display_mode *m = &hdata->current_mode; 1241 1242 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1243 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); 1244 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal); 1245 hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1, 1246 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0); 1247 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, 1248 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0); 1249 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, 1250 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); 1251 1252 /* 1253 * Quirk requirement for exynos 5 HDMI IP design, 1254 * 2 pixels less than the actual calculation for hsync_start 1255 * and end. 1256 */ 1257 1258 /* Following values & calculations differ for different type of modes */ 1259 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1260 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1261 (m->vsync_end - m->vdisplay) / 2); 1262 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1263 (m->vsync_start - m->vdisplay) / 2); 1264 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2); 1265 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1266 (m->vtotal - m->vdisplay) / 2); 1267 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 1268 m->vtotal - m->vdisplay / 2); 1269 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal); 1270 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 1271 (m->vtotal / 2) + 7); 1272 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 1273 (m->vtotal / 2) + 2); 1274 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 1275 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1276 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 1277 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1278 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1279 (m->vtotal - m->vdisplay) / 2); 1280 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1281 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 1282 m->vtotal - m->vdisplay / 2); 1283 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 1284 (m->vtotal / 2) + 1); 1285 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 1286 (m->vtotal / 2) + 1); 1287 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 1288 (m->vtotal / 2) + 1); 1289 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0); 1290 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0); 1291 } else { 1292 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1293 m->vsync_end - m->vdisplay); 1294 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1295 m->vsync_start - m->vdisplay); 1296 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal); 1297 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1298 m->vtotal - m->vdisplay); 1299 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff); 1300 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff); 1301 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff); 1302 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff); 1303 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff); 1304 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff); 1305 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1306 m->vtotal - m->vdisplay); 1307 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1308 } 1309 1310 hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2, 1311 m->hsync_start - m->hdisplay - 2); 1312 hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2, 1313 m->hsync_end - m->hdisplay - 2); 1314 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff); 1315 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff); 1316 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff); 1317 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff); 1318 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff); 1319 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff); 1320 hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff); 1321 hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff); 1322 hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff); 1323 hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff); 1324 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff); 1325 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff); 1326 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff); 1327 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff); 1328 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff); 1329 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff); 1330 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff); 1331 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff); 1332 1333 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1334 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); 1335 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); 1336 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1337 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1338 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1); 1339 } 1340 1341 static void hdmi_mode_apply(struct hdmi_context *hdata) 1342 { 1343 if (hdata->drv_data->type == HDMI_TYPE13) 1344 hdmi_v13_mode_apply(hdata); 1345 else 1346 hdmi_v14_mode_apply(hdata); 1347 1348 hdmi_start(hdata, true); 1349 } 1350 1351 static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1352 { 1353 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1); 1354 usleep_range(10000, 12000); 1355 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1); 1356 usleep_range(10000, 12000); 1357 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); 1358 usleep_range(10000, 12000); 1359 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); 1360 usleep_range(10000, 12000); 1361 } 1362 1363 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable) 1364 { 1365 u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET; 1366 1367 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1368 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE); 1369 } 1370 1371 static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1372 { 1373 int ret; 1374 const u8 *phy_conf; 1375 1376 ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000); 1377 if (ret < 0) { 1378 DRM_ERROR("failed to find hdmiphy conf\n"); 1379 return; 1380 } 1381 phy_conf = hdata->drv_data->phy_confs.data[ret].conf; 1382 1383 hdmi_clk_set_parents(hdata, false); 1384 1385 hdmiphy_conf_reset(hdata); 1386 1387 hdmiphy_enable_mode_set(hdata, true); 1388 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32); 1389 if (ret) { 1390 DRM_ERROR("failed to configure hdmiphy\n"); 1391 return; 1392 } 1393 hdmiphy_enable_mode_set(hdata, false); 1394 hdmi_clk_set_parents(hdata, true); 1395 usleep_range(10000, 12000); 1396 hdmiphy_wait_for_pll(hdata); 1397 } 1398 1399 static void hdmi_conf_apply(struct hdmi_context *hdata) 1400 { 1401 hdmi_start(hdata, false); 1402 hdmi_conf_init(hdata); 1403 hdmi_audio_init(hdata); 1404 hdmi_mode_apply(hdata); 1405 hdmi_audio_control(hdata, true); 1406 } 1407 1408 static void hdmi_mode_set(struct drm_encoder *encoder, 1409 struct drm_display_mode *mode, 1410 struct drm_display_mode *adjusted_mode) 1411 { 1412 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1413 struct drm_display_mode *m = adjusted_mode; 1414 1415 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n", 1416 m->hdisplay, m->vdisplay, 1417 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1418 "INTERLACED" : "PROGRESSIVE"); 1419 1420 drm_mode_copy(&hdata->current_mode, m); 1421 } 1422 1423 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) 1424 { 1425 if (!hdata->sysreg) 1426 return; 1427 1428 regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY, 1429 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); 1430 } 1431 1432 static void hdmiphy_enable(struct hdmi_context *hdata) 1433 { 1434 if (hdata->powered) 1435 return; 1436 1437 pm_runtime_get_sync(hdata->dev); 1438 1439 if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk)) 1440 DRM_DEBUG_KMS("failed to enable regulator bulk\n"); 1441 1442 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1443 PMU_HDMI_PHY_ENABLE_BIT, 1); 1444 1445 hdmi_set_refclk(hdata, true); 1446 1447 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN); 1448 1449 hdmiphy_conf_apply(hdata); 1450 1451 hdata->powered = true; 1452 } 1453 1454 static void hdmiphy_disable(struct hdmi_context *hdata) 1455 { 1456 if (!hdata->powered) 1457 return; 1458 1459 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); 1460 1461 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); 1462 1463 hdmi_set_refclk(hdata, false); 1464 1465 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1466 PMU_HDMI_PHY_ENABLE_BIT, 0); 1467 1468 regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); 1469 1470 pm_runtime_put_sync(hdata->dev); 1471 1472 hdata->powered = false; 1473 } 1474 1475 static void hdmi_enable(struct drm_encoder *encoder) 1476 { 1477 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1478 1479 hdmiphy_enable(hdata); 1480 hdmi_conf_apply(hdata); 1481 } 1482 1483 static void hdmi_disable(struct drm_encoder *encoder) 1484 { 1485 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1486 struct drm_crtc *crtc = encoder->crtc; 1487 const struct drm_crtc_helper_funcs *funcs = NULL; 1488 1489 if (!hdata->powered) 1490 return; 1491 1492 /* 1493 * The SFRs of VP and Mixer are updated by Vertical Sync of 1494 * Timing generator which is a part of HDMI so the sequence 1495 * to disable TV Subsystem should be as following, 1496 * VP -> Mixer -> HDMI 1497 * 1498 * Below codes will try to disable Mixer and VP(if used) 1499 * prior to disabling HDMI. 1500 */ 1501 if (crtc) 1502 funcs = crtc->helper_private; 1503 if (funcs && funcs->disable) 1504 (*funcs->disable)(crtc); 1505 1506 cancel_delayed_work(&hdata->hotplug_work); 1507 1508 hdmiphy_disable(hdata); 1509 } 1510 1511 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { 1512 .mode_fixup = hdmi_mode_fixup, 1513 .mode_set = hdmi_mode_set, 1514 .enable = hdmi_enable, 1515 .disable = hdmi_disable, 1516 }; 1517 1518 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = { 1519 .destroy = drm_encoder_cleanup, 1520 }; 1521 1522 static void hdmi_hotplug_work_func(struct work_struct *work) 1523 { 1524 struct hdmi_context *hdata; 1525 1526 hdata = container_of(work, struct hdmi_context, hotplug_work.work); 1527 1528 if (hdata->drm_dev) 1529 drm_helper_hpd_irq_event(hdata->drm_dev); 1530 } 1531 1532 static irqreturn_t hdmi_irq_thread(int irq, void *arg) 1533 { 1534 struct hdmi_context *hdata = arg; 1535 1536 mod_delayed_work(system_wq, &hdata->hotplug_work, 1537 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); 1538 1539 return IRQ_HANDLED; 1540 } 1541 1542 static int hdmi_clks_get(struct hdmi_context *hdata, 1543 const struct string_array_spec *names, 1544 struct clk **clks) 1545 { 1546 struct device *dev = hdata->dev; 1547 int i; 1548 1549 for (i = 0; i < names->count; ++i) { 1550 struct clk *clk = devm_clk_get(dev, names->data[i]); 1551 1552 if (IS_ERR(clk)) { 1553 int ret = PTR_ERR(clk); 1554 1555 dev_err(dev, "Cannot get clock %s, %d\n", 1556 names->data[i], ret); 1557 1558 return ret; 1559 } 1560 1561 clks[i] = clk; 1562 } 1563 1564 return 0; 1565 } 1566 1567 static int hdmi_clk_init(struct hdmi_context *hdata) 1568 { 1569 const struct hdmi_driver_data *drv_data = hdata->drv_data; 1570 int count = drv_data->clk_gates.count + drv_data->clk_muxes.count; 1571 struct device *dev = hdata->dev; 1572 struct clk **clks; 1573 int ret; 1574 1575 if (!count) 1576 return 0; 1577 1578 clks = devm_kzalloc(dev, sizeof(*clks) * count, GFP_KERNEL); 1579 if (!clks) 1580 return -ENOMEM; 1581 1582 hdata->clk_gates = clks; 1583 hdata->clk_muxes = clks + drv_data->clk_gates.count; 1584 1585 ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates); 1586 if (ret) 1587 return ret; 1588 1589 return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes); 1590 } 1591 1592 1593 static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable) 1594 { 1595 struct hdmi_context *hdata = container_of(clk, struct hdmi_context, 1596 phy_clk); 1597 1598 if (enable) 1599 hdmiphy_enable(hdata); 1600 else 1601 hdmiphy_disable(hdata); 1602 } 1603 1604 static int hdmi_bridge_init(struct hdmi_context *hdata) 1605 { 1606 struct device *dev = hdata->dev; 1607 struct device_node *ep, *np; 1608 1609 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1); 1610 if (!ep) 1611 return 0; 1612 1613 np = of_graph_get_remote_port_parent(ep); 1614 of_node_put(ep); 1615 if (!np) { 1616 DRM_ERROR("failed to get remote port parent"); 1617 return -EINVAL; 1618 } 1619 1620 hdata->bridge = of_drm_find_bridge(np); 1621 of_node_put(np); 1622 1623 if (!hdata->bridge) 1624 return -EPROBE_DEFER; 1625 1626 return 0; 1627 } 1628 1629 static int hdmi_resources_init(struct hdmi_context *hdata) 1630 { 1631 struct device *dev = hdata->dev; 1632 int i, ret; 1633 1634 DRM_DEBUG_KMS("HDMI resource init\n"); 1635 1636 hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); 1637 if (IS_ERR(hdata->hpd_gpio)) { 1638 DRM_ERROR("cannot get hpd gpio property\n"); 1639 return PTR_ERR(hdata->hpd_gpio); 1640 } 1641 1642 hdata->irq = gpiod_to_irq(hdata->hpd_gpio); 1643 if (hdata->irq < 0) { 1644 DRM_ERROR("failed to get GPIO irq\n"); 1645 return hdata->irq; 1646 } 1647 1648 ret = hdmi_clk_init(hdata); 1649 if (ret) 1650 return ret; 1651 1652 ret = hdmi_clk_set_parents(hdata, false); 1653 if (ret) 1654 return ret; 1655 1656 for (i = 0; i < ARRAY_SIZE(supply); ++i) 1657 hdata->regul_bulk[i].supply = supply[i]; 1658 1659 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk); 1660 if (ret) { 1661 if (ret != -EPROBE_DEFER) 1662 DRM_ERROR("failed to get regulators\n"); 1663 return ret; 1664 } 1665 1666 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en"); 1667 1668 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) { 1669 if (IS_ERR(hdata->reg_hdmi_en)) 1670 return PTR_ERR(hdata->reg_hdmi_en); 1671 1672 ret = regulator_enable(hdata->reg_hdmi_en); 1673 if (ret) { 1674 DRM_ERROR("failed to enable hdmi-en regulator\n"); 1675 return ret; 1676 } 1677 } 1678 1679 return hdmi_bridge_init(hdata); 1680 } 1681 1682 static struct of_device_id hdmi_match_types[] = { 1683 { 1684 .compatible = "samsung,exynos4210-hdmi", 1685 .data = &exynos4210_hdmi_driver_data, 1686 }, { 1687 .compatible = "samsung,exynos4212-hdmi", 1688 .data = &exynos4212_hdmi_driver_data, 1689 }, { 1690 .compatible = "samsung,exynos5420-hdmi", 1691 .data = &exynos5420_hdmi_driver_data, 1692 }, { 1693 .compatible = "samsung,exynos5433-hdmi", 1694 .data = &exynos5433_hdmi_driver_data, 1695 }, { 1696 /* end node */ 1697 } 1698 }; 1699 MODULE_DEVICE_TABLE (of, hdmi_match_types); 1700 1701 static int hdmi_bind(struct device *dev, struct device *master, void *data) 1702 { 1703 struct drm_device *drm_dev = data; 1704 struct hdmi_context *hdata = dev_get_drvdata(dev); 1705 struct drm_encoder *encoder = &hdata->encoder; 1706 int ret, pipe; 1707 1708 hdata->drm_dev = drm_dev; 1709 1710 pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev, 1711 EXYNOS_DISPLAY_TYPE_HDMI); 1712 if (pipe < 0) 1713 return pipe; 1714 1715 hdata->phy_clk.enable = hdmiphy_clk_enable; 1716 1717 exynos_drm_crtc_from_pipe(drm_dev, pipe)->pipe_clk = &hdata->phy_clk; 1718 1719 encoder->possible_crtcs = 1 << pipe; 1720 1721 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 1722 1723 drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs, 1724 DRM_MODE_ENCODER_TMDS, NULL); 1725 1726 drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs); 1727 1728 ret = hdmi_create_connector(encoder); 1729 if (ret) { 1730 DRM_ERROR("failed to create connector ret = %d\n", ret); 1731 drm_encoder_cleanup(encoder); 1732 return ret; 1733 } 1734 1735 return 0; 1736 } 1737 1738 static void hdmi_unbind(struct device *dev, struct device *master, void *data) 1739 { 1740 } 1741 1742 static const struct component_ops hdmi_component_ops = { 1743 .bind = hdmi_bind, 1744 .unbind = hdmi_unbind, 1745 }; 1746 1747 static int hdmi_get_ddc_adapter(struct hdmi_context *hdata) 1748 { 1749 const char *compatible_str = "samsung,exynos4210-hdmiddc"; 1750 struct device_node *np; 1751 struct i2c_adapter *adpt; 1752 1753 np = of_find_compatible_node(NULL, NULL, compatible_str); 1754 if (np) 1755 np = of_get_next_parent(np); 1756 else 1757 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0); 1758 1759 if (!np) { 1760 DRM_ERROR("Failed to find ddc node in device tree\n"); 1761 return -ENODEV; 1762 } 1763 1764 adpt = of_find_i2c_adapter_by_node(np); 1765 of_node_put(np); 1766 1767 if (!adpt) { 1768 DRM_INFO("Failed to get ddc i2c adapter by node\n"); 1769 return -EPROBE_DEFER; 1770 } 1771 1772 hdata->ddc_adpt = adpt; 1773 1774 return 0; 1775 } 1776 1777 static int hdmi_get_phy_io(struct hdmi_context *hdata) 1778 { 1779 const char *compatible_str = "samsung,exynos4212-hdmiphy"; 1780 struct device_node *np; 1781 int ret = 0; 1782 1783 np = of_find_compatible_node(NULL, NULL, compatible_str); 1784 if (!np) { 1785 np = of_parse_phandle(hdata->dev->of_node, "phy", 0); 1786 if (!np) { 1787 DRM_ERROR("Failed to find hdmiphy node in device tree\n"); 1788 return -ENODEV; 1789 } 1790 } 1791 1792 if (hdata->drv_data->is_apb_phy) { 1793 hdata->regs_hdmiphy = of_iomap(np, 0); 1794 if (!hdata->regs_hdmiphy) { 1795 DRM_ERROR("failed to ioremap hdmi phy\n"); 1796 ret = -ENOMEM; 1797 goto out; 1798 } 1799 } else { 1800 hdata->hdmiphy_port = of_find_i2c_device_by_node(np); 1801 if (!hdata->hdmiphy_port) { 1802 DRM_INFO("Failed to get hdmi phy i2c client\n"); 1803 ret = -EPROBE_DEFER; 1804 goto out; 1805 } 1806 } 1807 1808 out: 1809 of_node_put(np); 1810 return ret; 1811 } 1812 1813 static int hdmi_probe(struct platform_device *pdev) 1814 { 1815 struct device *dev = &pdev->dev; 1816 struct hdmi_context *hdata; 1817 struct resource *res; 1818 int ret; 1819 1820 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL); 1821 if (!hdata) 1822 return -ENOMEM; 1823 1824 hdata->drv_data = of_device_get_match_data(dev); 1825 1826 platform_set_drvdata(pdev, hdata); 1827 1828 hdata->dev = dev; 1829 1830 ret = hdmi_resources_init(hdata); 1831 if (ret) { 1832 if (ret != -EPROBE_DEFER) 1833 DRM_ERROR("hdmi_resources_init failed\n"); 1834 return ret; 1835 } 1836 1837 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1838 hdata->regs = devm_ioremap_resource(dev, res); 1839 if (IS_ERR(hdata->regs)) { 1840 ret = PTR_ERR(hdata->regs); 1841 return ret; 1842 } 1843 1844 ret = hdmi_get_ddc_adapter(hdata); 1845 if (ret) 1846 return ret; 1847 1848 ret = hdmi_get_phy_io(hdata); 1849 if (ret) 1850 goto err_ddc; 1851 1852 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func); 1853 1854 ret = devm_request_threaded_irq(dev, hdata->irq, NULL, 1855 hdmi_irq_thread, IRQF_TRIGGER_RISING | 1856 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1857 "hdmi", hdata); 1858 if (ret) { 1859 DRM_ERROR("failed to register hdmi interrupt\n"); 1860 goto err_hdmiphy; 1861 } 1862 1863 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 1864 "samsung,syscon-phandle"); 1865 if (IS_ERR(hdata->pmureg)) { 1866 DRM_ERROR("syscon regmap lookup failed.\n"); 1867 ret = -EPROBE_DEFER; 1868 goto err_hdmiphy; 1869 } 1870 1871 if (hdata->drv_data->has_sysreg) { 1872 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1873 "samsung,sysreg-phandle"); 1874 if (IS_ERR(hdata->sysreg)) { 1875 DRM_ERROR("sysreg regmap lookup failed.\n"); 1876 ret = -EPROBE_DEFER; 1877 goto err_hdmiphy; 1878 } 1879 } 1880 1881 pm_runtime_enable(dev); 1882 1883 ret = component_add(&pdev->dev, &hdmi_component_ops); 1884 if (ret) 1885 goto err_disable_pm_runtime; 1886 1887 return ret; 1888 1889 err_disable_pm_runtime: 1890 pm_runtime_disable(dev); 1891 1892 err_hdmiphy: 1893 if (hdata->hdmiphy_port) 1894 put_device(&hdata->hdmiphy_port->dev); 1895 if (hdata->regs_hdmiphy) 1896 iounmap(hdata->regs_hdmiphy); 1897 err_ddc: 1898 put_device(&hdata->ddc_adpt->dev); 1899 1900 return ret; 1901 } 1902 1903 static int hdmi_remove(struct platform_device *pdev) 1904 { 1905 struct hdmi_context *hdata = platform_get_drvdata(pdev); 1906 1907 cancel_delayed_work_sync(&hdata->hotplug_work); 1908 1909 component_del(&pdev->dev, &hdmi_component_ops); 1910 1911 pm_runtime_disable(&pdev->dev); 1912 1913 if (!IS_ERR(hdata->reg_hdmi_en)) 1914 regulator_disable(hdata->reg_hdmi_en); 1915 1916 if (hdata->hdmiphy_port) 1917 put_device(&hdata->hdmiphy_port->dev); 1918 1919 if (hdata->regs_hdmiphy) 1920 iounmap(hdata->regs_hdmiphy); 1921 1922 put_device(&hdata->ddc_adpt->dev); 1923 1924 return 0; 1925 } 1926 1927 #ifdef CONFIG_PM 1928 static int exynos_hdmi_suspend(struct device *dev) 1929 { 1930 struct hdmi_context *hdata = dev_get_drvdata(dev); 1931 1932 hdmi_clk_disable_gates(hdata); 1933 1934 return 0; 1935 } 1936 1937 static int exynos_hdmi_resume(struct device *dev) 1938 { 1939 struct hdmi_context *hdata = dev_get_drvdata(dev); 1940 int ret; 1941 1942 ret = hdmi_clk_enable_gates(hdata); 1943 if (ret < 0) 1944 return ret; 1945 1946 return 0; 1947 } 1948 #endif 1949 1950 static const struct dev_pm_ops exynos_hdmi_pm_ops = { 1951 SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL) 1952 }; 1953 1954 struct platform_driver hdmi_driver = { 1955 .probe = hdmi_probe, 1956 .remove = hdmi_remove, 1957 .driver = { 1958 .name = "exynos-hdmi", 1959 .owner = THIS_MODULE, 1960 .pm = &exynos_hdmi_pm_ops, 1961 .of_match_table = hdmi_match_types, 1962 }, 1963 }; 1964