1 /* 2 * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 * Authors: 4 * Seung-Woo Kim <sw0312.kim@samsung.com> 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * 8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include <drm/drmP.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_atomic_helper.h> 21 22 #include "regs-hdmi.h" 23 24 #include <linux/kernel.h> 25 #include <linux/wait.h> 26 #include <linux/i2c.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/irq.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/clk.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/io.h> 36 #include <linux/of_address.h> 37 #include <linux/of_device.h> 38 #include <linux/of_graph.h> 39 #include <linux/hdmi.h> 40 #include <linux/component.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/regmap.h> 43 #include <sound/hdmi-codec.h> 44 #include <drm/exynos_drm.h> 45 46 #include <media/cec-notifier.h> 47 48 #include "exynos_drm_crtc.h" 49 50 #define HOTPLUG_DEBOUNCE_MS 1100 51 52 enum hdmi_type { 53 HDMI_TYPE13, 54 HDMI_TYPE14, 55 HDMI_TYPE_COUNT 56 }; 57 58 #define HDMI_MAPPED_BASE 0xffff0000 59 60 enum hdmi_mapped_regs { 61 HDMI_PHY_STATUS = HDMI_MAPPED_BASE, 62 HDMI_PHY_RSTOUT, 63 HDMI_ACR_CON, 64 HDMI_ACR_MCTS0, 65 HDMI_ACR_CTS0, 66 HDMI_ACR_N0 67 }; 68 69 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = { 70 { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 }, 71 { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT }, 72 { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON }, 73 { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 }, 74 { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 }, 75 { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 }, 76 }; 77 78 static const char * const supply[] = { 79 "vdd", 80 "vdd_osc", 81 "vdd_pll", 82 }; 83 84 struct hdmiphy_config { 85 int pixel_clock; 86 u8 conf[32]; 87 }; 88 89 struct hdmiphy_configs { 90 int count; 91 const struct hdmiphy_config *data; 92 }; 93 94 struct string_array_spec { 95 int count; 96 const char * const *data; 97 }; 98 99 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a } 100 101 struct hdmi_driver_data { 102 unsigned int type; 103 unsigned int is_apb_phy:1; 104 unsigned int has_sysreg:1; 105 struct hdmiphy_configs phy_confs; 106 struct string_array_spec clk_gates; 107 /* 108 * Array of triplets (p_off, p_on, clock), where p_off and p_on are 109 * required parents of clock when HDMI-PHY is respectively off or on. 110 */ 111 struct string_array_spec clk_muxes; 112 }; 113 114 struct hdmi_audio { 115 struct platform_device *pdev; 116 struct hdmi_audio_infoframe infoframe; 117 struct hdmi_codec_params params; 118 bool mute; 119 }; 120 121 struct hdmi_context { 122 struct drm_encoder encoder; 123 struct device *dev; 124 struct drm_device *drm_dev; 125 struct drm_connector connector; 126 bool dvi_mode; 127 struct delayed_work hotplug_work; 128 struct cec_notifier *notifier; 129 const struct hdmi_driver_data *drv_data; 130 131 void __iomem *regs; 132 void __iomem *regs_hdmiphy; 133 struct i2c_client *hdmiphy_port; 134 struct i2c_adapter *ddc_adpt; 135 struct gpio_desc *hpd_gpio; 136 int irq; 137 struct regmap *pmureg; 138 struct regmap *sysreg; 139 struct clk **clk_gates; 140 struct clk **clk_muxes; 141 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; 142 struct regulator *reg_hdmi_en; 143 struct exynos_drm_clk phy_clk; 144 struct drm_bridge *bridge; 145 146 /* mutex protecting subsequent fields below */ 147 struct mutex mutex; 148 struct hdmi_audio audio; 149 bool powered; 150 }; 151 152 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) 153 { 154 return container_of(e, struct hdmi_context, encoder); 155 } 156 157 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c) 158 { 159 return container_of(c, struct hdmi_context, connector); 160 } 161 162 static const struct hdmiphy_config hdmiphy_v13_configs[] = { 163 { 164 .pixel_clock = 27000000, 165 .conf = { 166 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 167 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 168 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 169 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 170 }, 171 }, 172 { 173 .pixel_clock = 27027000, 174 .conf = { 175 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 176 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 177 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 178 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 179 }, 180 }, 181 { 182 .pixel_clock = 74176000, 183 .conf = { 184 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 185 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 186 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 187 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80, 188 }, 189 }, 190 { 191 .pixel_clock = 74250000, 192 .conf = { 193 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 194 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 195 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, 196 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80, 197 }, 198 }, 199 { 200 .pixel_clock = 148500000, 201 .conf = { 202 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 203 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 204 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, 205 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80, 206 }, 207 }, 208 }; 209 210 static const struct hdmiphy_config hdmiphy_v14_configs[] = { 211 { 212 .pixel_clock = 25200000, 213 .conf = { 214 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08, 215 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 216 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 217 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 218 }, 219 }, 220 { 221 .pixel_clock = 27000000, 222 .conf = { 223 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20, 224 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, 225 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 226 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 227 }, 228 }, 229 { 230 .pixel_clock = 27027000, 231 .conf = { 232 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, 233 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 234 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 235 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 236 }, 237 }, 238 { 239 .pixel_clock = 36000000, 240 .conf = { 241 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08, 242 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 243 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 244 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 245 }, 246 }, 247 { 248 .pixel_clock = 40000000, 249 .conf = { 250 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08, 251 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 252 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 253 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 254 }, 255 }, 256 { 257 .pixel_clock = 65000000, 258 .conf = { 259 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08, 260 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, 261 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 262 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 263 }, 264 }, 265 { 266 .pixel_clock = 71000000, 267 .conf = { 268 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08, 269 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 270 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 271 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 272 }, 273 }, 274 { 275 .pixel_clock = 73250000, 276 .conf = { 277 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08, 278 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 279 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 280 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 281 }, 282 }, 283 { 284 .pixel_clock = 74176000, 285 .conf = { 286 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, 287 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 288 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 289 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 290 }, 291 }, 292 { 293 .pixel_clock = 74250000, 294 .conf = { 295 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, 296 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 297 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 298 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 299 }, 300 }, 301 { 302 .pixel_clock = 83500000, 303 .conf = { 304 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08, 305 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 306 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 307 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 308 }, 309 }, 310 { 311 .pixel_clock = 85500000, 312 .conf = { 313 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08, 314 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80, 315 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 316 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 317 }, 318 }, 319 { 320 .pixel_clock = 106500000, 321 .conf = { 322 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, 323 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 324 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 325 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 326 }, 327 }, 328 { 329 .pixel_clock = 108000000, 330 .conf = { 331 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08, 332 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 333 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 334 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 335 }, 336 }, 337 { 338 .pixel_clock = 115500000, 339 .conf = { 340 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08, 341 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, 342 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 343 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 344 }, 345 }, 346 { 347 .pixel_clock = 119000000, 348 .conf = { 349 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08, 350 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 351 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 352 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 353 }, 354 }, 355 { 356 .pixel_clock = 146250000, 357 .conf = { 358 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, 359 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 360 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 361 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 362 }, 363 }, 364 { 365 .pixel_clock = 148500000, 366 .conf = { 367 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, 368 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 369 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 370 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 371 }, 372 }, 373 }; 374 375 static const struct hdmiphy_config hdmiphy_5420_configs[] = { 376 { 377 .pixel_clock = 25200000, 378 .conf = { 379 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8, 380 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 381 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66, 382 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 383 }, 384 }, 385 { 386 .pixel_clock = 27000000, 387 .conf = { 388 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0, 389 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 390 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 391 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 392 }, 393 }, 394 { 395 .pixel_clock = 27027000, 396 .conf = { 397 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8, 398 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 399 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 400 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 401 }, 402 }, 403 { 404 .pixel_clock = 36000000, 405 .conf = { 406 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8, 407 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 408 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 409 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 410 }, 411 }, 412 { 413 .pixel_clock = 40000000, 414 .conf = { 415 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8, 416 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 417 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 418 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 419 }, 420 }, 421 { 422 .pixel_clock = 65000000, 423 .conf = { 424 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8, 425 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 426 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 427 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 428 }, 429 }, 430 { 431 .pixel_clock = 71000000, 432 .conf = { 433 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8, 434 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 435 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 436 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 437 }, 438 }, 439 { 440 .pixel_clock = 73250000, 441 .conf = { 442 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8, 443 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 444 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 445 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 446 }, 447 }, 448 { 449 .pixel_clock = 74176000, 450 .conf = { 451 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, 452 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 453 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 454 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 455 }, 456 }, 457 { 458 .pixel_clock = 74250000, 459 .conf = { 460 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08, 461 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 462 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 463 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 464 }, 465 }, 466 { 467 .pixel_clock = 83500000, 468 .conf = { 469 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8, 470 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 471 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 472 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 473 }, 474 }, 475 { 476 .pixel_clock = 88750000, 477 .conf = { 478 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8, 479 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 480 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 481 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 482 }, 483 }, 484 { 485 .pixel_clock = 106500000, 486 .conf = { 487 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8, 488 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 489 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 490 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 491 }, 492 }, 493 { 494 .pixel_clock = 108000000, 495 .conf = { 496 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, 497 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 498 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 499 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 500 }, 501 }, 502 { 503 .pixel_clock = 115500000, 504 .conf = { 505 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8, 506 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 507 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 508 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 509 }, 510 }, 511 { 512 .pixel_clock = 146250000, 513 .conf = { 514 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8, 515 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 516 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 517 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 518 }, 519 }, 520 { 521 .pixel_clock = 148500000, 522 .conf = { 523 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08, 524 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 525 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 526 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80, 527 }, 528 }, 529 }; 530 531 static const struct hdmiphy_config hdmiphy_5433_configs[] = { 532 { 533 .pixel_clock = 27000000, 534 .conf = { 535 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02, 536 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 537 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 538 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 539 }, 540 }, 541 { 542 .pixel_clock = 27027000, 543 .conf = { 544 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3, 545 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 546 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 547 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 548 }, 549 }, 550 { 551 .pixel_clock = 40000000, 552 .conf = { 553 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02, 554 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 555 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 556 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 557 }, 558 }, 559 { 560 .pixel_clock = 50000000, 561 .conf = { 562 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3, 563 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 564 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 565 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 566 }, 567 }, 568 { 569 .pixel_clock = 65000000, 570 .conf = { 571 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6, 572 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 573 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 574 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 575 }, 576 }, 577 { 578 .pixel_clock = 74176000, 579 .conf = { 580 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42, 581 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 582 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 583 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 584 }, 585 }, 586 { 587 .pixel_clock = 74250000, 588 .conf = { 589 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2, 590 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 591 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 592 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 593 }, 594 }, 595 { 596 .pixel_clock = 108000000, 597 .conf = { 598 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02, 599 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 600 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 601 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 602 }, 603 }, 604 { 605 .pixel_clock = 148500000, 606 .conf = { 607 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1, 608 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5, 609 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30, 610 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, 611 }, 612 }, 613 { 614 .pixel_clock = 297000000, 615 .conf = { 616 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2, 617 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 618 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 619 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 620 }, 621 }, 622 }; 623 624 static const char * const hdmi_clk_gates4[] = { 625 "hdmi", "sclk_hdmi" 626 }; 627 628 static const char * const hdmi_clk_muxes4[] = { 629 "sclk_pixel", "sclk_hdmiphy", "mout_hdmi" 630 }; 631 632 static const char * const hdmi_clk_gates5433[] = { 633 "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk" 634 }; 635 636 static const char * const hdmi_clk_muxes5433[] = { 637 "oscclk", "tmds_clko", "tmds_clko_user", 638 "oscclk", "pixel_clko", "pixel_clko_user" 639 }; 640 641 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = { 642 .type = HDMI_TYPE13, 643 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs), 644 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 645 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 646 }; 647 648 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = { 649 .type = HDMI_TYPE14, 650 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs), 651 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 652 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 653 }; 654 655 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = { 656 .type = HDMI_TYPE14, 657 .is_apb_phy = 1, 658 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs), 659 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 660 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 661 }; 662 663 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = { 664 .type = HDMI_TYPE14, 665 .is_apb_phy = 1, 666 .has_sysreg = 1, 667 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs), 668 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433), 669 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433), 670 }; 671 672 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id) 673 { 674 if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE) 675 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type]; 676 return reg_id; 677 } 678 679 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id) 680 { 681 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id)); 682 } 683 684 static inline void hdmi_reg_writeb(struct hdmi_context *hdata, 685 u32 reg_id, u8 value) 686 { 687 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id)); 688 } 689 690 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, 691 int bytes, u32 val) 692 { 693 reg_id = hdmi_map_reg(hdata, reg_id); 694 695 while (--bytes >= 0) { 696 writel(val & 0xff, hdata->regs + reg_id); 697 val >>= 8; 698 reg_id += 4; 699 } 700 } 701 702 static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id, 703 u8 *buf, int size) 704 { 705 for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4) 706 writel(*buf++, hdata->regs + reg_id); 707 } 708 709 static inline void hdmi_reg_writemask(struct hdmi_context *hdata, 710 u32 reg_id, u32 value, u32 mask) 711 { 712 u32 old; 713 714 reg_id = hdmi_map_reg(hdata, reg_id); 715 old = readl(hdata->regs + reg_id); 716 value = (value & mask) | (old & ~mask); 717 writel(value, hdata->regs + reg_id); 718 } 719 720 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, 721 u32 reg_offset, const u8 *buf, u32 len) 722 { 723 if ((reg_offset + len) > 32) 724 return -EINVAL; 725 726 if (hdata->hdmiphy_port) { 727 int ret; 728 729 ret = i2c_master_send(hdata->hdmiphy_port, buf, len); 730 if (ret == len) 731 return 0; 732 return ret; 733 } else { 734 int i; 735 for (i = 0; i < len; i++) 736 writel(buf[i], hdata->regs_hdmiphy + 737 ((reg_offset + i)<<2)); 738 return 0; 739 } 740 } 741 742 static int hdmi_clk_enable_gates(struct hdmi_context *hdata) 743 { 744 int i, ret; 745 746 for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) { 747 ret = clk_prepare_enable(hdata->clk_gates[i]); 748 if (!ret) 749 continue; 750 751 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n", 752 hdata->drv_data->clk_gates.data[i], ret); 753 while (i--) 754 clk_disable_unprepare(hdata->clk_gates[i]); 755 return ret; 756 } 757 758 return 0; 759 } 760 761 static void hdmi_clk_disable_gates(struct hdmi_context *hdata) 762 { 763 int i = hdata->drv_data->clk_gates.count; 764 765 while (i--) 766 clk_disable_unprepare(hdata->clk_gates[i]); 767 } 768 769 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy) 770 { 771 struct device *dev = hdata->dev; 772 int ret = 0; 773 int i; 774 775 for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) { 776 struct clk **c = &hdata->clk_muxes[i]; 777 778 ret = clk_set_parent(c[2], c[to_phy]); 779 if (!ret) 780 continue; 781 782 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n", 783 hdata->drv_data->clk_muxes.data[i + 2], 784 hdata->drv_data->clk_muxes.data[i + to_phy], ret); 785 } 786 787 return ret; 788 } 789 790 static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata) 791 { 792 struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe; 793 u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; 794 int len; 795 796 len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf)); 797 if (len < 0) 798 return len; 799 800 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); 801 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len); 802 803 return 0; 804 } 805 806 static void hdmi_reg_infoframes(struct hdmi_context *hdata) 807 { 808 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 809 union hdmi_infoframe frm; 810 u8 buf[25]; 811 int ret; 812 813 if (hdata->dvi_mode) { 814 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 815 HDMI_AVI_CON_DO_NOT_TRANSMIT); 816 hdmi_reg_writeb(hdata, HDMI_VSI_CON, 817 HDMI_VSI_CON_DO_NOT_TRANSMIT); 818 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN); 819 return; 820 } 821 822 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, m, false); 823 if (!ret) 824 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); 825 if (ret > 0) { 826 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC); 827 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret); 828 } else { 829 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); 830 } 831 832 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, m); 833 if (!ret) 834 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, 835 sizeof(buf)); 836 if (ret > 0) { 837 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC); 838 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3); 839 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3); 840 } 841 842 hdmi_audio_infoframe_apply(hdata); 843 } 844 845 static enum drm_connector_status hdmi_detect(struct drm_connector *connector, 846 bool force) 847 { 848 struct hdmi_context *hdata = connector_to_hdmi(connector); 849 850 if (gpiod_get_value(hdata->hpd_gpio)) 851 return connector_status_connected; 852 853 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); 854 return connector_status_disconnected; 855 } 856 857 static void hdmi_connector_destroy(struct drm_connector *connector) 858 { 859 drm_connector_unregister(connector); 860 drm_connector_cleanup(connector); 861 } 862 863 static const struct drm_connector_funcs hdmi_connector_funcs = { 864 .fill_modes = drm_helper_probe_single_connector_modes, 865 .detect = hdmi_detect, 866 .destroy = hdmi_connector_destroy, 867 .reset = drm_atomic_helper_connector_reset, 868 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 869 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 870 }; 871 872 static int hdmi_get_modes(struct drm_connector *connector) 873 { 874 struct hdmi_context *hdata = connector_to_hdmi(connector); 875 struct edid *edid; 876 int ret; 877 878 if (!hdata->ddc_adpt) 879 return -ENODEV; 880 881 edid = drm_get_edid(connector, hdata->ddc_adpt); 882 if (!edid) 883 return -ENODEV; 884 885 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); 886 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n", 887 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"), 888 edid->width_cm, edid->height_cm); 889 890 drm_mode_connector_update_edid_property(connector, edid); 891 cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid); 892 893 ret = drm_add_edid_modes(connector, edid); 894 895 kfree(edid); 896 897 return ret; 898 } 899 900 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) 901 { 902 const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs; 903 int i; 904 905 for (i = 0; i < confs->count; i++) 906 if (confs->data[i].pixel_clock == pixel_clock) 907 return i; 908 909 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock); 910 return -EINVAL; 911 } 912 913 static int hdmi_mode_valid(struct drm_connector *connector, 914 struct drm_display_mode *mode) 915 { 916 struct hdmi_context *hdata = connector_to_hdmi(connector); 917 int ret; 918 919 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 920 mode->hdisplay, mode->vdisplay, mode->vrefresh, 921 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true : 922 false, mode->clock * 1000); 923 924 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000); 925 if (ret < 0) 926 return MODE_BAD; 927 928 return MODE_OK; 929 } 930 931 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { 932 .get_modes = hdmi_get_modes, 933 .mode_valid = hdmi_mode_valid, 934 }; 935 936 static int hdmi_create_connector(struct drm_encoder *encoder) 937 { 938 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 939 struct drm_connector *connector = &hdata->connector; 940 int ret; 941 942 connector->interlace_allowed = true; 943 connector->polled = DRM_CONNECTOR_POLL_HPD; 944 945 ret = drm_connector_init(hdata->drm_dev, connector, 946 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); 947 if (ret) { 948 DRM_ERROR("Failed to initialize connector with drm\n"); 949 return ret; 950 } 951 952 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); 953 drm_mode_connector_attach_encoder(connector, encoder); 954 955 if (hdata->bridge) { 956 encoder->bridge = hdata->bridge; 957 hdata->bridge->encoder = encoder; 958 ret = drm_bridge_attach(encoder, hdata->bridge, NULL); 959 if (ret) 960 DRM_ERROR("Failed to attach bridge\n"); 961 } 962 963 return ret; 964 } 965 966 static bool hdmi_mode_fixup(struct drm_encoder *encoder, 967 const struct drm_display_mode *mode, 968 struct drm_display_mode *adjusted_mode) 969 { 970 struct drm_device *dev = encoder->dev; 971 struct drm_connector *connector; 972 struct drm_display_mode *m; 973 struct drm_connector_list_iter conn_iter; 974 int mode_ok; 975 976 drm_mode_set_crtcinfo(adjusted_mode, 0); 977 978 drm_connector_list_iter_begin(dev, &conn_iter); 979 drm_for_each_connector_iter(connector, &conn_iter) { 980 if (connector->encoder == encoder) 981 break; 982 } 983 if (connector) 984 drm_connector_get(connector); 985 drm_connector_list_iter_end(&conn_iter); 986 987 if (!connector) 988 return true; 989 990 mode_ok = hdmi_mode_valid(connector, adjusted_mode); 991 992 if (mode_ok == MODE_OK) 993 goto cleanup; 994 995 /* 996 * Find the most suitable mode and copy it to adjusted_mode. 997 */ 998 list_for_each_entry(m, &connector->modes, head) { 999 mode_ok = hdmi_mode_valid(connector, m); 1000 1001 if (mode_ok == MODE_OK) { 1002 DRM_INFO("desired mode doesn't exist so\n"); 1003 DRM_INFO("use the most suitable mode among modes.\n"); 1004 1005 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n", 1006 m->hdisplay, m->vdisplay, m->vrefresh); 1007 1008 drm_mode_copy(adjusted_mode, m); 1009 break; 1010 } 1011 } 1012 1013 cleanup: 1014 drm_connector_put(connector); 1015 1016 return true; 1017 } 1018 1019 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq) 1020 { 1021 u32 n, cts; 1022 1023 cts = (freq % 9) ? 27000 : 30000; 1024 n = 128 * freq / (27000000 / cts); 1025 1026 hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n); 1027 hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts); 1028 hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts); 1029 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); 1030 } 1031 1032 static void hdmi_audio_config(struct hdmi_context *hdata) 1033 { 1034 u32 bit_ch = 1; 1035 u32 data_num, val; 1036 int i; 1037 1038 switch (hdata->audio.params.sample_width) { 1039 case 20: 1040 data_num = 2; 1041 break; 1042 case 24: 1043 data_num = 3; 1044 break; 1045 default: 1046 data_num = 1; 1047 bit_ch = 0; 1048 break; 1049 } 1050 1051 hdmi_reg_acr(hdata, hdata->audio.params.sample_rate); 1052 1053 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE 1054 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE 1055 | HDMI_I2S_MUX_ENABLE); 1056 1057 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN 1058 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); 1059 1060 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); 1061 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); 1062 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); 1063 1064 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; 1065 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); 1066 1067 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */ 1068 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5) 1069 | HDMI_I2S_SEL_LRCK(6)); 1070 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1) 1071 | HDMI_I2S_SEL_SDATA2(4)); 1072 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1) 1073 | HDMI_I2S_SEL_SDATA2(2)); 1074 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0)); 1075 1076 /* I2S_CON_1 & 2 */ 1077 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE 1078 | HDMI_I2S_L_CH_LOW_POL); 1079 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE 1080 | HDMI_I2S_SET_BIT_CH(bit_ch) 1081 | HDMI_I2S_SET_SDATA_BIT(data_num) 1082 | HDMI_I2S_BASIC_FORMAT); 1083 1084 /* Configuration of the audio channel status registers */ 1085 for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++) 1086 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i), 1087 hdata->audio.params.iec.status[i]); 1088 1089 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); 1090 } 1091 1092 static void hdmi_audio_control(struct hdmi_context *hdata) 1093 { 1094 bool enable = !hdata->audio.mute; 1095 1096 if (hdata->dvi_mode) 1097 return; 1098 1099 hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ? 1100 HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN); 1101 hdmi_reg_writemask(hdata, HDMI_CON_0, enable ? 1102 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); 1103 } 1104 1105 static void hdmi_start(struct hdmi_context *hdata, bool start) 1106 { 1107 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1108 u32 val = start ? HDMI_TG_EN : 0; 1109 1110 if (m->flags & DRM_MODE_FLAG_INTERLACE) 1111 val |= HDMI_FIELD_EN; 1112 1113 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); 1114 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN); 1115 } 1116 1117 static void hdmi_conf_init(struct hdmi_context *hdata) 1118 { 1119 /* disable HPD interrupts from HDMI IP block, use GPIO instead */ 1120 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL | 1121 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); 1122 1123 /* choose HDMI mode */ 1124 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1125 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); 1126 /* apply video pre-amble and guard band in HDMI mode only */ 1127 hdmi_reg_writeb(hdata, HDMI_CON_2, 0); 1128 /* disable bluescreen */ 1129 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); 1130 1131 if (hdata->dvi_mode) { 1132 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1133 HDMI_MODE_DVI_EN, HDMI_MODE_MASK); 1134 hdmi_reg_writeb(hdata, HDMI_CON_2, 1135 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS); 1136 } 1137 1138 if (hdata->drv_data->type == HDMI_TYPE13) { 1139 /* choose bluescreen (fecal) color */ 1140 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12); 1141 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34); 1142 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56); 1143 1144 /* enable AVI packet every vsync, fixes purple line problem */ 1145 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02); 1146 /* force RGB, look to CEA-861-D, table 7 for more detail */ 1147 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5); 1148 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5); 1149 1150 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02); 1151 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); 1152 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); 1153 } else { 1154 hdmi_reg_infoframes(hdata); 1155 1156 /* enable AVI packet every vsync, fixes purple line problem */ 1157 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5); 1158 } 1159 } 1160 1161 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata) 1162 { 1163 int tries; 1164 1165 for (tries = 0; tries < 10; ++tries) { 1166 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); 1167 1168 if (val & HDMI_PHY_STATUS_READY) { 1169 DRM_DEBUG_KMS("PLL stabilized after %d tries\n", tries); 1170 return; 1171 } 1172 usleep_range(10, 20); 1173 } 1174 1175 DRM_ERROR("PLL could not reach steady state\n"); 1176 } 1177 1178 static void hdmi_v13_mode_apply(struct hdmi_context *hdata) 1179 { 1180 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1181 unsigned int val; 1182 1183 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1184 hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3, 1185 (m->htotal << 12) | m->vtotal); 1186 1187 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 1188 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val); 1189 1190 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; 1191 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val); 1192 1193 val = (m->hsync_start - m->hdisplay - 2); 1194 val |= ((m->hsync_end - m->hdisplay - 2) << 10); 1195 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20; 1196 hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val); 1197 1198 /* 1199 * Quirk requirement for exynos HDMI IP design, 1200 * 2 pixels less than the actual calculation for hsync_start 1201 * and end. 1202 */ 1203 1204 /* Following values & calculations differ for different type of modes */ 1205 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1206 val = ((m->vsync_end - m->vdisplay) / 2); 1207 val |= ((m->vsync_start - m->vdisplay) / 2) << 12; 1208 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1209 1210 val = m->vtotal / 2; 1211 val |= ((m->vtotal - m->vdisplay) / 2) << 11; 1212 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1213 1214 val = (m->vtotal + 1215 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2; 1216 val |= m->vtotal << 11; 1217 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val); 1218 1219 val = ((m->vtotal / 2) + 7); 1220 val |= ((m->vtotal / 2) + 2) << 12; 1221 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val); 1222 1223 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1224 val |= ((m->htotal / 2) + 1225 (m->hsync_start - m->hdisplay)) << 12; 1226 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val); 1227 1228 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1229 (m->vtotal - m->vdisplay) / 2); 1230 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1231 1232 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249); 1233 } else { 1234 val = m->vtotal; 1235 val |= (m->vtotal - m->vdisplay) << 11; 1236 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1237 1238 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0); 1239 1240 val = (m->vsync_end - m->vdisplay); 1241 val |= ((m->vsync_start - m->vdisplay) << 12); 1242 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1243 1244 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001); 1245 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001); 1246 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1247 m->vtotal - m->vdisplay); 1248 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1249 } 1250 1251 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1252 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); 1253 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); 1254 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1255 } 1256 1257 static void hdmi_v14_mode_apply(struct hdmi_context *hdata) 1258 { 1259 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1260 struct drm_display_mode *am = 1261 &hdata->encoder.crtc->state->adjusted_mode; 1262 int hquirk = 0; 1263 1264 /* 1265 * In case video mode coming from CRTC differs from requested one HDMI 1266 * sometimes is able to almost properly perform conversion - only 1267 * first line is distorted. 1268 */ 1269 if ((m->vdisplay != am->vdisplay) && 1270 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366)) 1271 hquirk = 258; 1272 1273 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1274 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); 1275 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal); 1276 hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1, 1277 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0); 1278 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, 1279 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0); 1280 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, 1281 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); 1282 1283 /* 1284 * Quirk requirement for exynos 5 HDMI IP design, 1285 * 2 pixels less than the actual calculation for hsync_start 1286 * and end. 1287 */ 1288 1289 /* Following values & calculations differ for different type of modes */ 1290 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1291 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1292 (m->vsync_end - m->vdisplay) / 2); 1293 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1294 (m->vsync_start - m->vdisplay) / 2); 1295 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2); 1296 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1297 (m->vtotal - m->vdisplay) / 2); 1298 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 1299 m->vtotal - m->vdisplay / 2); 1300 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal); 1301 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 1302 (m->vtotal / 2) + 7); 1303 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 1304 (m->vtotal / 2) + 2); 1305 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 1306 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1307 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 1308 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1309 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1310 (m->vtotal - m->vdisplay) / 2); 1311 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1312 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 1313 m->vtotal - m->vdisplay / 2); 1314 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 1315 (m->vtotal / 2) + 1); 1316 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 1317 (m->vtotal / 2) + 1); 1318 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 1319 (m->vtotal / 2) + 1); 1320 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0); 1321 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0); 1322 } else { 1323 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1324 m->vsync_end - m->vdisplay); 1325 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1326 m->vsync_start - m->vdisplay); 1327 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal); 1328 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1329 m->vtotal - m->vdisplay); 1330 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff); 1331 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff); 1332 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff); 1333 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff); 1334 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff); 1335 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff); 1336 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1337 m->vtotal - m->vdisplay); 1338 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1339 } 1340 1341 hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2, 1342 m->hsync_start - m->hdisplay - 2); 1343 hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2, 1344 m->hsync_end - m->hdisplay - 2); 1345 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff); 1346 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff); 1347 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff); 1348 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff); 1349 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff); 1350 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff); 1351 hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff); 1352 hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff); 1353 hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff); 1354 hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff); 1355 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff); 1356 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff); 1357 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff); 1358 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff); 1359 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff); 1360 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff); 1361 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff); 1362 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff); 1363 1364 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1365 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, 1366 m->htotal - m->hdisplay - hquirk); 1367 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk); 1368 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1369 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1370 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1); 1371 } 1372 1373 static void hdmi_mode_apply(struct hdmi_context *hdata) 1374 { 1375 if (hdata->drv_data->type == HDMI_TYPE13) 1376 hdmi_v13_mode_apply(hdata); 1377 else 1378 hdmi_v14_mode_apply(hdata); 1379 1380 hdmi_start(hdata, true); 1381 } 1382 1383 static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1384 { 1385 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1); 1386 usleep_range(10000, 12000); 1387 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1); 1388 usleep_range(10000, 12000); 1389 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); 1390 usleep_range(10000, 12000); 1391 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); 1392 usleep_range(10000, 12000); 1393 } 1394 1395 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable) 1396 { 1397 u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET; 1398 1399 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1400 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE); 1401 } 1402 1403 static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1404 { 1405 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1406 int ret; 1407 const u8 *phy_conf; 1408 1409 ret = hdmi_find_phy_conf(hdata, m->clock * 1000); 1410 if (ret < 0) { 1411 DRM_ERROR("failed to find hdmiphy conf\n"); 1412 return; 1413 } 1414 phy_conf = hdata->drv_data->phy_confs.data[ret].conf; 1415 1416 hdmi_clk_set_parents(hdata, false); 1417 1418 hdmiphy_conf_reset(hdata); 1419 1420 hdmiphy_enable_mode_set(hdata, true); 1421 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32); 1422 if (ret) { 1423 DRM_ERROR("failed to configure hdmiphy\n"); 1424 return; 1425 } 1426 hdmiphy_enable_mode_set(hdata, false); 1427 hdmi_clk_set_parents(hdata, true); 1428 usleep_range(10000, 12000); 1429 hdmiphy_wait_for_pll(hdata); 1430 } 1431 1432 /* Should be called with hdata->mutex mutex held */ 1433 static void hdmi_conf_apply(struct hdmi_context *hdata) 1434 { 1435 hdmi_start(hdata, false); 1436 hdmi_conf_init(hdata); 1437 hdmi_audio_config(hdata); 1438 hdmi_mode_apply(hdata); 1439 hdmi_audio_control(hdata); 1440 } 1441 1442 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) 1443 { 1444 if (!hdata->sysreg) 1445 return; 1446 1447 regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY, 1448 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); 1449 } 1450 1451 /* Should be called with hdata->mutex mutex held. */ 1452 static void hdmiphy_enable(struct hdmi_context *hdata) 1453 { 1454 if (hdata->powered) 1455 return; 1456 1457 pm_runtime_get_sync(hdata->dev); 1458 1459 if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk)) 1460 DRM_DEBUG_KMS("failed to enable regulator bulk\n"); 1461 1462 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1463 PMU_HDMI_PHY_ENABLE_BIT, 1); 1464 1465 hdmi_set_refclk(hdata, true); 1466 1467 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN); 1468 1469 hdmiphy_conf_apply(hdata); 1470 1471 hdata->powered = true; 1472 } 1473 1474 /* Should be called with hdata->mutex mutex held. */ 1475 static void hdmiphy_disable(struct hdmi_context *hdata) 1476 { 1477 if (!hdata->powered) 1478 return; 1479 1480 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); 1481 1482 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); 1483 1484 hdmi_set_refclk(hdata, false); 1485 1486 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1487 PMU_HDMI_PHY_ENABLE_BIT, 0); 1488 1489 regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); 1490 1491 pm_runtime_put_sync(hdata->dev); 1492 1493 hdata->powered = false; 1494 } 1495 1496 static void hdmi_enable(struct drm_encoder *encoder) 1497 { 1498 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1499 1500 mutex_lock(&hdata->mutex); 1501 1502 hdmiphy_enable(hdata); 1503 hdmi_conf_apply(hdata); 1504 1505 mutex_unlock(&hdata->mutex); 1506 } 1507 1508 static void hdmi_disable(struct drm_encoder *encoder) 1509 { 1510 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1511 1512 mutex_lock(&hdata->mutex); 1513 1514 if (hdata->powered) { 1515 /* 1516 * The SFRs of VP and Mixer are updated by Vertical Sync of 1517 * Timing generator which is a part of HDMI so the sequence 1518 * to disable TV Subsystem should be as following, 1519 * VP -> Mixer -> HDMI 1520 * 1521 * To achieve such sequence HDMI is disabled together with 1522 * HDMI PHY, via pipe clock callback. 1523 */ 1524 mutex_unlock(&hdata->mutex); 1525 cancel_delayed_work(&hdata->hotplug_work); 1526 cec_notifier_set_phys_addr(hdata->notifier, 1527 CEC_PHYS_ADDR_INVALID); 1528 return; 1529 } 1530 1531 mutex_unlock(&hdata->mutex); 1532 } 1533 1534 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { 1535 .mode_fixup = hdmi_mode_fixup, 1536 .enable = hdmi_enable, 1537 .disable = hdmi_disable, 1538 }; 1539 1540 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = { 1541 .destroy = drm_encoder_cleanup, 1542 }; 1543 1544 static void hdmi_audio_shutdown(struct device *dev, void *data) 1545 { 1546 struct hdmi_context *hdata = dev_get_drvdata(dev); 1547 1548 mutex_lock(&hdata->mutex); 1549 1550 hdata->audio.mute = true; 1551 1552 if (hdata->powered) 1553 hdmi_audio_control(hdata); 1554 1555 mutex_unlock(&hdata->mutex); 1556 } 1557 1558 static int hdmi_audio_hw_params(struct device *dev, void *data, 1559 struct hdmi_codec_daifmt *daifmt, 1560 struct hdmi_codec_params *params) 1561 { 1562 struct hdmi_context *hdata = dev_get_drvdata(dev); 1563 1564 if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv || 1565 daifmt->frame_clk_inv || daifmt->bit_clk_master || 1566 daifmt->frame_clk_master) { 1567 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1568 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1569 daifmt->bit_clk_master, 1570 daifmt->frame_clk_master); 1571 return -EINVAL; 1572 } 1573 1574 mutex_lock(&hdata->mutex); 1575 1576 hdata->audio.params = *params; 1577 1578 if (hdata->powered) { 1579 hdmi_audio_config(hdata); 1580 hdmi_audio_infoframe_apply(hdata); 1581 } 1582 1583 mutex_unlock(&hdata->mutex); 1584 1585 return 0; 1586 } 1587 1588 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool mute) 1589 { 1590 struct hdmi_context *hdata = dev_get_drvdata(dev); 1591 1592 mutex_lock(&hdata->mutex); 1593 1594 hdata->audio.mute = mute; 1595 1596 if (hdata->powered) 1597 hdmi_audio_control(hdata); 1598 1599 mutex_unlock(&hdata->mutex); 1600 1601 return 0; 1602 } 1603 1604 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, 1605 size_t len) 1606 { 1607 struct hdmi_context *hdata = dev_get_drvdata(dev); 1608 struct drm_connector *connector = &hdata->connector; 1609 1610 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1611 1612 return 0; 1613 } 1614 1615 static const struct hdmi_codec_ops audio_codec_ops = { 1616 .hw_params = hdmi_audio_hw_params, 1617 .audio_shutdown = hdmi_audio_shutdown, 1618 .digital_mute = hdmi_audio_digital_mute, 1619 .get_eld = hdmi_audio_get_eld, 1620 }; 1621 1622 static int hdmi_register_audio_device(struct hdmi_context *hdata) 1623 { 1624 struct hdmi_codec_pdata codec_data = { 1625 .ops = &audio_codec_ops, 1626 .max_i2s_channels = 6, 1627 .i2s = 1, 1628 }; 1629 1630 hdata->audio.pdev = platform_device_register_data( 1631 hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1632 &codec_data, sizeof(codec_data)); 1633 1634 return PTR_ERR_OR_ZERO(hdata->audio.pdev); 1635 } 1636 1637 static void hdmi_hotplug_work_func(struct work_struct *work) 1638 { 1639 struct hdmi_context *hdata; 1640 1641 hdata = container_of(work, struct hdmi_context, hotplug_work.work); 1642 1643 if (hdata->drm_dev) 1644 drm_helper_hpd_irq_event(hdata->drm_dev); 1645 } 1646 1647 static irqreturn_t hdmi_irq_thread(int irq, void *arg) 1648 { 1649 struct hdmi_context *hdata = arg; 1650 1651 mod_delayed_work(system_wq, &hdata->hotplug_work, 1652 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); 1653 1654 return IRQ_HANDLED; 1655 } 1656 1657 static int hdmi_clks_get(struct hdmi_context *hdata, 1658 const struct string_array_spec *names, 1659 struct clk **clks) 1660 { 1661 struct device *dev = hdata->dev; 1662 int i; 1663 1664 for (i = 0; i < names->count; ++i) { 1665 struct clk *clk = devm_clk_get(dev, names->data[i]); 1666 1667 if (IS_ERR(clk)) { 1668 int ret = PTR_ERR(clk); 1669 1670 dev_err(dev, "Cannot get clock %s, %d\n", 1671 names->data[i], ret); 1672 1673 return ret; 1674 } 1675 1676 clks[i] = clk; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static int hdmi_clk_init(struct hdmi_context *hdata) 1683 { 1684 const struct hdmi_driver_data *drv_data = hdata->drv_data; 1685 int count = drv_data->clk_gates.count + drv_data->clk_muxes.count; 1686 struct device *dev = hdata->dev; 1687 struct clk **clks; 1688 int ret; 1689 1690 if (!count) 1691 return 0; 1692 1693 clks = devm_kzalloc(dev, sizeof(*clks) * count, GFP_KERNEL); 1694 if (!clks) 1695 return -ENOMEM; 1696 1697 hdata->clk_gates = clks; 1698 hdata->clk_muxes = clks + drv_data->clk_gates.count; 1699 1700 ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates); 1701 if (ret) 1702 return ret; 1703 1704 return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes); 1705 } 1706 1707 1708 static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable) 1709 { 1710 struct hdmi_context *hdata = container_of(clk, struct hdmi_context, 1711 phy_clk); 1712 mutex_lock(&hdata->mutex); 1713 1714 if (enable) 1715 hdmiphy_enable(hdata); 1716 else 1717 hdmiphy_disable(hdata); 1718 1719 mutex_unlock(&hdata->mutex); 1720 } 1721 1722 static int hdmi_bridge_init(struct hdmi_context *hdata) 1723 { 1724 struct device *dev = hdata->dev; 1725 struct device_node *ep, *np; 1726 1727 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1); 1728 if (!ep) 1729 return 0; 1730 1731 np = of_graph_get_remote_port_parent(ep); 1732 of_node_put(ep); 1733 if (!np) { 1734 DRM_ERROR("failed to get remote port parent"); 1735 return -EINVAL; 1736 } 1737 1738 hdata->bridge = of_drm_find_bridge(np); 1739 of_node_put(np); 1740 1741 if (!hdata->bridge) 1742 return -EPROBE_DEFER; 1743 1744 return 0; 1745 } 1746 1747 static int hdmi_resources_init(struct hdmi_context *hdata) 1748 { 1749 struct device *dev = hdata->dev; 1750 int i, ret; 1751 1752 DRM_DEBUG_KMS("HDMI resource init\n"); 1753 1754 hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); 1755 if (IS_ERR(hdata->hpd_gpio)) { 1756 DRM_ERROR("cannot get hpd gpio property\n"); 1757 return PTR_ERR(hdata->hpd_gpio); 1758 } 1759 1760 hdata->irq = gpiod_to_irq(hdata->hpd_gpio); 1761 if (hdata->irq < 0) { 1762 DRM_ERROR("failed to get GPIO irq\n"); 1763 return hdata->irq; 1764 } 1765 1766 ret = hdmi_clk_init(hdata); 1767 if (ret) 1768 return ret; 1769 1770 ret = hdmi_clk_set_parents(hdata, false); 1771 if (ret) 1772 return ret; 1773 1774 for (i = 0; i < ARRAY_SIZE(supply); ++i) 1775 hdata->regul_bulk[i].supply = supply[i]; 1776 1777 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk); 1778 if (ret) { 1779 if (ret != -EPROBE_DEFER) 1780 DRM_ERROR("failed to get regulators\n"); 1781 return ret; 1782 } 1783 1784 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en"); 1785 1786 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) { 1787 if (IS_ERR(hdata->reg_hdmi_en)) 1788 return PTR_ERR(hdata->reg_hdmi_en); 1789 1790 ret = regulator_enable(hdata->reg_hdmi_en); 1791 if (ret) { 1792 DRM_ERROR("failed to enable hdmi-en regulator\n"); 1793 return ret; 1794 } 1795 } 1796 1797 return hdmi_bridge_init(hdata); 1798 } 1799 1800 static const struct of_device_id hdmi_match_types[] = { 1801 { 1802 .compatible = "samsung,exynos4210-hdmi", 1803 .data = &exynos4210_hdmi_driver_data, 1804 }, { 1805 .compatible = "samsung,exynos4212-hdmi", 1806 .data = &exynos4212_hdmi_driver_data, 1807 }, { 1808 .compatible = "samsung,exynos5420-hdmi", 1809 .data = &exynos5420_hdmi_driver_data, 1810 }, { 1811 .compatible = "samsung,exynos5433-hdmi", 1812 .data = &exynos5433_hdmi_driver_data, 1813 }, { 1814 /* end node */ 1815 } 1816 }; 1817 MODULE_DEVICE_TABLE (of, hdmi_match_types); 1818 1819 static int hdmi_bind(struct device *dev, struct device *master, void *data) 1820 { 1821 struct drm_device *drm_dev = data; 1822 struct hdmi_context *hdata = dev_get_drvdata(dev); 1823 struct drm_encoder *encoder = &hdata->encoder; 1824 struct exynos_drm_crtc *crtc; 1825 int ret; 1826 1827 hdata->drm_dev = drm_dev; 1828 1829 hdata->phy_clk.enable = hdmiphy_clk_enable; 1830 1831 drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs, 1832 DRM_MODE_ENCODER_TMDS, NULL); 1833 1834 drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs); 1835 1836 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI); 1837 if (ret < 0) 1838 return ret; 1839 1840 crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI); 1841 crtc->pipe_clk = &hdata->phy_clk; 1842 1843 ret = hdmi_create_connector(encoder); 1844 if (ret) { 1845 DRM_ERROR("failed to create connector ret = %d\n", ret); 1846 drm_encoder_cleanup(encoder); 1847 return ret; 1848 } 1849 1850 return 0; 1851 } 1852 1853 static void hdmi_unbind(struct device *dev, struct device *master, void *data) 1854 { 1855 } 1856 1857 static const struct component_ops hdmi_component_ops = { 1858 .bind = hdmi_bind, 1859 .unbind = hdmi_unbind, 1860 }; 1861 1862 static int hdmi_get_ddc_adapter(struct hdmi_context *hdata) 1863 { 1864 const char *compatible_str = "samsung,exynos4210-hdmiddc"; 1865 struct device_node *np; 1866 struct i2c_adapter *adpt; 1867 1868 np = of_find_compatible_node(NULL, NULL, compatible_str); 1869 if (np) 1870 np = of_get_next_parent(np); 1871 else 1872 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0); 1873 1874 if (!np) { 1875 DRM_ERROR("Failed to find ddc node in device tree\n"); 1876 return -ENODEV; 1877 } 1878 1879 adpt = of_find_i2c_adapter_by_node(np); 1880 of_node_put(np); 1881 1882 if (!adpt) { 1883 DRM_INFO("Failed to get ddc i2c adapter by node\n"); 1884 return -EPROBE_DEFER; 1885 } 1886 1887 hdata->ddc_adpt = adpt; 1888 1889 return 0; 1890 } 1891 1892 static int hdmi_get_phy_io(struct hdmi_context *hdata) 1893 { 1894 const char *compatible_str = "samsung,exynos4212-hdmiphy"; 1895 struct device_node *np; 1896 int ret = 0; 1897 1898 np = of_find_compatible_node(NULL, NULL, compatible_str); 1899 if (!np) { 1900 np = of_parse_phandle(hdata->dev->of_node, "phy", 0); 1901 if (!np) { 1902 DRM_ERROR("Failed to find hdmiphy node in device tree\n"); 1903 return -ENODEV; 1904 } 1905 } 1906 1907 if (hdata->drv_data->is_apb_phy) { 1908 hdata->regs_hdmiphy = of_iomap(np, 0); 1909 if (!hdata->regs_hdmiphy) { 1910 DRM_ERROR("failed to ioremap hdmi phy\n"); 1911 ret = -ENOMEM; 1912 goto out; 1913 } 1914 } else { 1915 hdata->hdmiphy_port = of_find_i2c_device_by_node(np); 1916 if (!hdata->hdmiphy_port) { 1917 DRM_INFO("Failed to get hdmi phy i2c client\n"); 1918 ret = -EPROBE_DEFER; 1919 goto out; 1920 } 1921 } 1922 1923 out: 1924 of_node_put(np); 1925 return ret; 1926 } 1927 1928 static int hdmi_probe(struct platform_device *pdev) 1929 { 1930 struct hdmi_audio_infoframe *audio_infoframe; 1931 struct device *dev = &pdev->dev; 1932 struct hdmi_context *hdata; 1933 struct resource *res; 1934 int ret; 1935 1936 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL); 1937 if (!hdata) 1938 return -ENOMEM; 1939 1940 hdata->drv_data = of_device_get_match_data(dev); 1941 1942 platform_set_drvdata(pdev, hdata); 1943 1944 hdata->dev = dev; 1945 1946 mutex_init(&hdata->mutex); 1947 1948 ret = hdmi_resources_init(hdata); 1949 if (ret) { 1950 if (ret != -EPROBE_DEFER) 1951 DRM_ERROR("hdmi_resources_init failed\n"); 1952 return ret; 1953 } 1954 1955 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1956 hdata->regs = devm_ioremap_resource(dev, res); 1957 if (IS_ERR(hdata->regs)) { 1958 ret = PTR_ERR(hdata->regs); 1959 return ret; 1960 } 1961 1962 ret = hdmi_get_ddc_adapter(hdata); 1963 if (ret) 1964 return ret; 1965 1966 ret = hdmi_get_phy_io(hdata); 1967 if (ret) 1968 goto err_ddc; 1969 1970 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func); 1971 1972 ret = devm_request_threaded_irq(dev, hdata->irq, NULL, 1973 hdmi_irq_thread, IRQF_TRIGGER_RISING | 1974 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1975 "hdmi", hdata); 1976 if (ret) { 1977 DRM_ERROR("failed to register hdmi interrupt\n"); 1978 goto err_hdmiphy; 1979 } 1980 1981 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 1982 "samsung,syscon-phandle"); 1983 if (IS_ERR(hdata->pmureg)) { 1984 DRM_ERROR("syscon regmap lookup failed.\n"); 1985 ret = -EPROBE_DEFER; 1986 goto err_hdmiphy; 1987 } 1988 1989 if (hdata->drv_data->has_sysreg) { 1990 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1991 "samsung,sysreg-phandle"); 1992 if (IS_ERR(hdata->sysreg)) { 1993 DRM_ERROR("sysreg regmap lookup failed.\n"); 1994 ret = -EPROBE_DEFER; 1995 goto err_hdmiphy; 1996 } 1997 } 1998 1999 hdata->notifier = cec_notifier_get(&pdev->dev); 2000 if (hdata->notifier == NULL) { 2001 ret = -ENOMEM; 2002 goto err_hdmiphy; 2003 } 2004 2005 pm_runtime_enable(dev); 2006 2007 audio_infoframe = &hdata->audio.infoframe; 2008 hdmi_audio_infoframe_init(audio_infoframe); 2009 audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 2010 audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 2011 audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 2012 audio_infoframe->channels = 2; 2013 2014 ret = hdmi_register_audio_device(hdata); 2015 if (ret) 2016 goto err_notifier_put; 2017 2018 ret = component_add(&pdev->dev, &hdmi_component_ops); 2019 if (ret) 2020 goto err_unregister_audio; 2021 2022 return ret; 2023 2024 err_unregister_audio: 2025 platform_device_unregister(hdata->audio.pdev); 2026 2027 err_notifier_put: 2028 cec_notifier_put(hdata->notifier); 2029 pm_runtime_disable(dev); 2030 2031 err_hdmiphy: 2032 if (hdata->hdmiphy_port) 2033 put_device(&hdata->hdmiphy_port->dev); 2034 if (hdata->regs_hdmiphy) 2035 iounmap(hdata->regs_hdmiphy); 2036 err_ddc: 2037 put_device(&hdata->ddc_adpt->dev); 2038 2039 return ret; 2040 } 2041 2042 static int hdmi_remove(struct platform_device *pdev) 2043 { 2044 struct hdmi_context *hdata = platform_get_drvdata(pdev); 2045 2046 cancel_delayed_work_sync(&hdata->hotplug_work); 2047 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); 2048 2049 component_del(&pdev->dev, &hdmi_component_ops); 2050 platform_device_unregister(hdata->audio.pdev); 2051 2052 cec_notifier_put(hdata->notifier); 2053 pm_runtime_disable(&pdev->dev); 2054 2055 if (!IS_ERR(hdata->reg_hdmi_en)) 2056 regulator_disable(hdata->reg_hdmi_en); 2057 2058 if (hdata->hdmiphy_port) 2059 put_device(&hdata->hdmiphy_port->dev); 2060 2061 if (hdata->regs_hdmiphy) 2062 iounmap(hdata->regs_hdmiphy); 2063 2064 put_device(&hdata->ddc_adpt->dev); 2065 2066 mutex_destroy(&hdata->mutex); 2067 2068 return 0; 2069 } 2070 2071 static int __maybe_unused exynos_hdmi_suspend(struct device *dev) 2072 { 2073 struct hdmi_context *hdata = dev_get_drvdata(dev); 2074 2075 hdmi_clk_disable_gates(hdata); 2076 2077 return 0; 2078 } 2079 2080 static int __maybe_unused exynos_hdmi_resume(struct device *dev) 2081 { 2082 struct hdmi_context *hdata = dev_get_drvdata(dev); 2083 int ret; 2084 2085 ret = hdmi_clk_enable_gates(hdata); 2086 if (ret < 0) 2087 return ret; 2088 2089 return 0; 2090 } 2091 2092 static const struct dev_pm_ops exynos_hdmi_pm_ops = { 2093 SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL) 2094 }; 2095 2096 struct platform_driver hdmi_driver = { 2097 .probe = hdmi_probe, 2098 .remove = hdmi_remove, 2099 .driver = { 2100 .name = "exynos-hdmi", 2101 .owner = THIS_MODULE, 2102 .pm = &exynos_hdmi_pm_ops, 2103 .of_match_table = hdmi_match_types, 2104 }, 2105 }; 2106