1 /* 2 * Copyright (C) 2011 Samsung Electronics Co.Ltd 3 * Authors: 4 * Seung-Woo Kim <sw0312.kim@samsung.com> 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * 8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17 #include <drm/drmP.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_probe_helper.h> 21 22 #include "regs-hdmi.h" 23 24 #include <linux/kernel.h> 25 #include <linux/wait.h> 26 #include <linux/i2c.h> 27 #include <linux/platform_device.h> 28 #include <linux/interrupt.h> 29 #include <linux/irq.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/clk.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/io.h> 36 #include <linux/of_address.h> 37 #include <linux/of_device.h> 38 #include <linux/of_graph.h> 39 #include <linux/hdmi.h> 40 #include <linux/component.h> 41 #include <linux/mfd/syscon.h> 42 #include <linux/regmap.h> 43 #include <sound/hdmi-codec.h> 44 #include <drm/exynos_drm.h> 45 46 #include <media/cec-notifier.h> 47 48 #include "exynos_drm_crtc.h" 49 50 #define HOTPLUG_DEBOUNCE_MS 1100 51 52 enum hdmi_type { 53 HDMI_TYPE13, 54 HDMI_TYPE14, 55 HDMI_TYPE_COUNT 56 }; 57 58 #define HDMI_MAPPED_BASE 0xffff0000 59 60 enum hdmi_mapped_regs { 61 HDMI_PHY_STATUS = HDMI_MAPPED_BASE, 62 HDMI_PHY_RSTOUT, 63 HDMI_ACR_CON, 64 HDMI_ACR_MCTS0, 65 HDMI_ACR_CTS0, 66 HDMI_ACR_N0 67 }; 68 69 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = { 70 { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 }, 71 { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT }, 72 { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON }, 73 { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 }, 74 { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 }, 75 { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 }, 76 }; 77 78 static const char * const supply[] = { 79 "vdd", 80 "vdd_osc", 81 "vdd_pll", 82 }; 83 84 struct hdmiphy_config { 85 int pixel_clock; 86 u8 conf[32]; 87 }; 88 89 struct hdmiphy_configs { 90 int count; 91 const struct hdmiphy_config *data; 92 }; 93 94 struct string_array_spec { 95 int count; 96 const char * const *data; 97 }; 98 99 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a } 100 101 struct hdmi_driver_data { 102 unsigned int type; 103 unsigned int is_apb_phy:1; 104 unsigned int has_sysreg:1; 105 struct hdmiphy_configs phy_confs; 106 struct string_array_spec clk_gates; 107 /* 108 * Array of triplets (p_off, p_on, clock), where p_off and p_on are 109 * required parents of clock when HDMI-PHY is respectively off or on. 110 */ 111 struct string_array_spec clk_muxes; 112 }; 113 114 struct hdmi_audio { 115 struct platform_device *pdev; 116 struct hdmi_audio_infoframe infoframe; 117 struct hdmi_codec_params params; 118 bool mute; 119 }; 120 121 struct hdmi_context { 122 struct drm_encoder encoder; 123 struct device *dev; 124 struct drm_device *drm_dev; 125 struct drm_connector connector; 126 bool dvi_mode; 127 struct delayed_work hotplug_work; 128 struct cec_notifier *notifier; 129 const struct hdmi_driver_data *drv_data; 130 131 void __iomem *regs; 132 void __iomem *regs_hdmiphy; 133 struct i2c_client *hdmiphy_port; 134 struct i2c_adapter *ddc_adpt; 135 struct gpio_desc *hpd_gpio; 136 int irq; 137 struct regmap *pmureg; 138 struct regmap *sysreg; 139 struct clk **clk_gates; 140 struct clk **clk_muxes; 141 struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; 142 struct regulator *reg_hdmi_en; 143 struct exynos_drm_clk phy_clk; 144 struct drm_bridge *bridge; 145 146 /* mutex protecting subsequent fields below */ 147 struct mutex mutex; 148 struct hdmi_audio audio; 149 bool powered; 150 }; 151 152 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) 153 { 154 return container_of(e, struct hdmi_context, encoder); 155 } 156 157 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c) 158 { 159 return container_of(c, struct hdmi_context, connector); 160 } 161 162 static const struct hdmiphy_config hdmiphy_v13_configs[] = { 163 { 164 .pixel_clock = 27000000, 165 .conf = { 166 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 167 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 168 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 169 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 170 }, 171 }, 172 { 173 .pixel_clock = 27027000, 174 .conf = { 175 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 176 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 177 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 178 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, 179 }, 180 }, 181 { 182 .pixel_clock = 74176000, 183 .conf = { 184 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 185 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 186 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, 187 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80, 188 }, 189 }, 190 { 191 .pixel_clock = 74250000, 192 .conf = { 193 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 194 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 195 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, 196 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80, 197 }, 198 }, 199 { 200 .pixel_clock = 148500000, 201 .conf = { 202 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 203 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 204 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, 205 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80, 206 }, 207 }, 208 }; 209 210 static const struct hdmiphy_config hdmiphy_v14_configs[] = { 211 { 212 .pixel_clock = 25200000, 213 .conf = { 214 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08, 215 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80, 216 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 217 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 218 }, 219 }, 220 { 221 .pixel_clock = 27000000, 222 .conf = { 223 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20, 224 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80, 225 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 226 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 227 }, 228 }, 229 { 230 .pixel_clock = 27027000, 231 .conf = { 232 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, 233 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 234 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 235 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 236 }, 237 }, 238 { 239 .pixel_clock = 36000000, 240 .conf = { 241 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08, 242 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 243 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 244 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 245 }, 246 }, 247 { 248 .pixel_clock = 40000000, 249 .conf = { 250 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08, 251 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80, 252 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 253 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 254 }, 255 }, 256 { 257 .pixel_clock = 65000000, 258 .conf = { 259 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08, 260 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80, 261 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 262 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 263 }, 264 }, 265 { 266 .pixel_clock = 71000000, 267 .conf = { 268 0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08, 269 0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80, 270 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 271 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 272 }, 273 }, 274 { 275 .pixel_clock = 73250000, 276 .conf = { 277 0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08, 278 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 279 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 280 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 281 }, 282 }, 283 { 284 .pixel_clock = 74176000, 285 .conf = { 286 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08, 287 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80, 288 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 289 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 290 }, 291 }, 292 { 293 .pixel_clock = 74250000, 294 .conf = { 295 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, 296 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 297 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 298 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 299 }, 300 }, 301 { 302 .pixel_clock = 83500000, 303 .conf = { 304 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08, 305 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80, 306 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 307 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 308 }, 309 }, 310 { 311 .pixel_clock = 85500000, 312 .conf = { 313 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08, 314 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80, 315 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 316 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 317 }, 318 }, 319 { 320 .pixel_clock = 106500000, 321 .conf = { 322 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, 323 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 324 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 325 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 326 }, 327 }, 328 { 329 .pixel_clock = 108000000, 330 .conf = { 331 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08, 332 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 333 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 334 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 335 }, 336 }, 337 { 338 .pixel_clock = 115500000, 339 .conf = { 340 0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08, 341 0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80, 342 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 343 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 344 }, 345 }, 346 { 347 .pixel_clock = 119000000, 348 .conf = { 349 0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08, 350 0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80, 351 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 352 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 353 }, 354 }, 355 { 356 .pixel_clock = 146250000, 357 .conf = { 358 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08, 359 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 360 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 361 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 362 }, 363 }, 364 { 365 .pixel_clock = 148500000, 366 .conf = { 367 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, 368 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 369 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, 370 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 371 }, 372 }, 373 }; 374 375 static const struct hdmiphy_config hdmiphy_5420_configs[] = { 376 { 377 .pixel_clock = 25200000, 378 .conf = { 379 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8, 380 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 381 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66, 382 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 383 }, 384 }, 385 { 386 .pixel_clock = 27000000, 387 .conf = { 388 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0, 389 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 390 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 391 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 392 }, 393 }, 394 { 395 .pixel_clock = 27027000, 396 .conf = { 397 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8, 398 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 399 0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 400 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 401 }, 402 }, 403 { 404 .pixel_clock = 36000000, 405 .conf = { 406 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8, 407 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 408 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 409 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 410 }, 411 }, 412 { 413 .pixel_clock = 40000000, 414 .conf = { 415 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8, 416 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 417 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 418 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 419 }, 420 }, 421 { 422 .pixel_clock = 65000000, 423 .conf = { 424 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8, 425 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 426 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 427 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 428 }, 429 }, 430 { 431 .pixel_clock = 71000000, 432 .conf = { 433 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8, 434 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 435 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 436 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 437 }, 438 }, 439 { 440 .pixel_clock = 73250000, 441 .conf = { 442 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8, 443 0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 444 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 445 0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 446 }, 447 }, 448 { 449 .pixel_clock = 74176000, 450 .conf = { 451 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, 452 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 453 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 454 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 455 }, 456 }, 457 { 458 .pixel_clock = 74250000, 459 .conf = { 460 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08, 461 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 462 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 463 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 464 }, 465 }, 466 { 467 .pixel_clock = 83500000, 468 .conf = { 469 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8, 470 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 471 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 472 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 473 }, 474 }, 475 { 476 .pixel_clock = 88750000, 477 .conf = { 478 0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8, 479 0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 480 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 481 0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, 482 }, 483 }, 484 { 485 .pixel_clock = 106500000, 486 .conf = { 487 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8, 488 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 489 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 490 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 491 }, 492 }, 493 { 494 .pixel_clock = 108000000, 495 .conf = { 496 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, 497 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 498 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 499 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, 500 }, 501 }, 502 { 503 .pixel_clock = 115500000, 504 .conf = { 505 0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8, 506 0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 507 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 508 0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 509 }, 510 }, 511 { 512 .pixel_clock = 146250000, 513 .conf = { 514 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8, 515 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, 516 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66, 517 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, 518 }, 519 }, 520 { 521 .pixel_clock = 148500000, 522 .conf = { 523 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08, 524 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, 525 0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66, 526 0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80, 527 }, 528 }, 529 }; 530 531 static const struct hdmiphy_config hdmiphy_5433_configs[] = { 532 { 533 .pixel_clock = 27000000, 534 .conf = { 535 0x01, 0x51, 0x2d, 0x75, 0x01, 0x00, 0x88, 0x02, 536 0x72, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 537 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 538 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 539 }, 540 }, 541 { 542 .pixel_clock = 27027000, 543 .conf = { 544 0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3, 545 0x71, 0x50, 0x44, 0x8c, 0x27, 0x00, 0x7c, 0xac, 546 0xd6, 0x2b, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 547 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 548 }, 549 }, 550 { 551 .pixel_clock = 40000000, 552 .conf = { 553 0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02, 554 0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 555 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 556 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 557 }, 558 }, 559 { 560 .pixel_clock = 50000000, 561 .conf = { 562 0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3, 563 0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 564 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 565 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 566 }, 567 }, 568 { 569 .pixel_clock = 65000000, 570 .conf = { 571 0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6, 572 0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 573 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 574 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 575 }, 576 }, 577 { 578 .pixel_clock = 74176000, 579 .conf = { 580 0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42, 581 0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 582 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 583 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 584 }, 585 }, 586 { 587 .pixel_clock = 74250000, 588 .conf = { 589 0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2, 590 0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 591 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 592 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 593 }, 594 }, 595 { 596 .pixel_clock = 108000000, 597 .conf = { 598 0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02, 599 0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 600 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 601 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 602 }, 603 }, 604 { 605 .pixel_clock = 148500000, 606 .conf = { 607 0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1, 608 0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5, 609 0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30, 610 0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40, 611 }, 612 }, 613 { 614 .pixel_clock = 297000000, 615 .conf = { 616 0x01, 0x51, 0x3E, 0x05, 0x40, 0xF0, 0x88, 0xC2, 617 0x52, 0x53, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC, 618 0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30, 619 0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40, 620 }, 621 }, 622 }; 623 624 static const char * const hdmi_clk_gates4[] = { 625 "hdmi", "sclk_hdmi" 626 }; 627 628 static const char * const hdmi_clk_muxes4[] = { 629 "sclk_pixel", "sclk_hdmiphy", "mout_hdmi" 630 }; 631 632 static const char * const hdmi_clk_gates5433[] = { 633 "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk" 634 }; 635 636 static const char * const hdmi_clk_muxes5433[] = { 637 "oscclk", "tmds_clko", "tmds_clko_user", 638 "oscclk", "pixel_clko", "pixel_clko_user" 639 }; 640 641 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = { 642 .type = HDMI_TYPE13, 643 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v13_configs), 644 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 645 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 646 }; 647 648 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = { 649 .type = HDMI_TYPE14, 650 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_v14_configs), 651 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 652 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 653 }; 654 655 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = { 656 .type = HDMI_TYPE14, 657 .is_apb_phy = 1, 658 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5420_configs), 659 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates4), 660 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes4), 661 }; 662 663 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = { 664 .type = HDMI_TYPE14, 665 .is_apb_phy = 1, 666 .has_sysreg = 1, 667 .phy_confs = INIT_ARRAY_SPEC(hdmiphy_5433_configs), 668 .clk_gates = INIT_ARRAY_SPEC(hdmi_clk_gates5433), 669 .clk_muxes = INIT_ARRAY_SPEC(hdmi_clk_muxes5433), 670 }; 671 672 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id) 673 { 674 if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE) 675 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type]; 676 return reg_id; 677 } 678 679 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id) 680 { 681 return readl(hdata->regs + hdmi_map_reg(hdata, reg_id)); 682 } 683 684 static inline void hdmi_reg_writeb(struct hdmi_context *hdata, 685 u32 reg_id, u8 value) 686 { 687 writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id)); 688 } 689 690 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, 691 int bytes, u32 val) 692 { 693 reg_id = hdmi_map_reg(hdata, reg_id); 694 695 while (--bytes >= 0) { 696 writel(val & 0xff, hdata->regs + reg_id); 697 val >>= 8; 698 reg_id += 4; 699 } 700 } 701 702 static inline void hdmi_reg_write_buf(struct hdmi_context *hdata, u32 reg_id, 703 u8 *buf, int size) 704 { 705 for (reg_id = hdmi_map_reg(hdata, reg_id); size; --size, reg_id += 4) 706 writel(*buf++, hdata->regs + reg_id); 707 } 708 709 static inline void hdmi_reg_writemask(struct hdmi_context *hdata, 710 u32 reg_id, u32 value, u32 mask) 711 { 712 u32 old; 713 714 reg_id = hdmi_map_reg(hdata, reg_id); 715 old = readl(hdata->regs + reg_id); 716 value = (value & mask) | (old & ~mask); 717 writel(value, hdata->regs + reg_id); 718 } 719 720 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, 721 u32 reg_offset, const u8 *buf, u32 len) 722 { 723 if ((reg_offset + len) > 32) 724 return -EINVAL; 725 726 if (hdata->hdmiphy_port) { 727 int ret; 728 729 ret = i2c_master_send(hdata->hdmiphy_port, buf, len); 730 if (ret == len) 731 return 0; 732 return ret; 733 } else { 734 int i; 735 for (i = 0; i < len; i++) 736 writel(buf[i], hdata->regs_hdmiphy + 737 ((reg_offset + i)<<2)); 738 return 0; 739 } 740 } 741 742 static int hdmi_clk_enable_gates(struct hdmi_context *hdata) 743 { 744 int i, ret; 745 746 for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) { 747 ret = clk_prepare_enable(hdata->clk_gates[i]); 748 if (!ret) 749 continue; 750 751 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n", 752 hdata->drv_data->clk_gates.data[i], ret); 753 while (i--) 754 clk_disable_unprepare(hdata->clk_gates[i]); 755 return ret; 756 } 757 758 return 0; 759 } 760 761 static void hdmi_clk_disable_gates(struct hdmi_context *hdata) 762 { 763 int i = hdata->drv_data->clk_gates.count; 764 765 while (i--) 766 clk_disable_unprepare(hdata->clk_gates[i]); 767 } 768 769 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy) 770 { 771 struct device *dev = hdata->dev; 772 int ret = 0; 773 int i; 774 775 for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) { 776 struct clk **c = &hdata->clk_muxes[i]; 777 778 ret = clk_set_parent(c[2], c[to_phy]); 779 if (!ret) 780 continue; 781 782 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n", 783 hdata->drv_data->clk_muxes.data[i + 2], 784 hdata->drv_data->clk_muxes.data[i + to_phy], ret); 785 } 786 787 return ret; 788 } 789 790 static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata) 791 { 792 struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe; 793 u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; 794 int len; 795 796 len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf)); 797 if (len < 0) 798 return len; 799 800 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); 801 hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len); 802 803 return 0; 804 } 805 806 static void hdmi_reg_infoframes(struct hdmi_context *hdata) 807 { 808 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 809 union hdmi_infoframe frm; 810 u8 buf[25]; 811 int ret; 812 813 if (hdata->dvi_mode) { 814 hdmi_reg_writeb(hdata, HDMI_AVI_CON, 815 HDMI_AVI_CON_DO_NOT_TRANSMIT); 816 hdmi_reg_writeb(hdata, HDMI_VSI_CON, 817 HDMI_VSI_CON_DO_NOT_TRANSMIT); 818 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN); 819 return; 820 } 821 822 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 823 &hdata->connector, m); 824 if (!ret) 825 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); 826 if (ret > 0) { 827 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC); 828 hdmi_reg_write_buf(hdata, HDMI_AVI_HEADER0, buf, ret); 829 } else { 830 DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); 831 } 832 833 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, 834 &hdata->connector, m); 835 if (!ret) 836 ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, 837 sizeof(buf)); 838 if (ret > 0) { 839 hdmi_reg_writeb(hdata, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC); 840 hdmi_reg_write_buf(hdata, HDMI_VSI_HEADER0, buf, 3); 841 hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3); 842 } 843 844 hdmi_audio_infoframe_apply(hdata); 845 } 846 847 static enum drm_connector_status hdmi_detect(struct drm_connector *connector, 848 bool force) 849 { 850 struct hdmi_context *hdata = connector_to_hdmi(connector); 851 852 if (gpiod_get_value(hdata->hpd_gpio)) 853 return connector_status_connected; 854 855 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); 856 return connector_status_disconnected; 857 } 858 859 static void hdmi_connector_destroy(struct drm_connector *connector) 860 { 861 drm_connector_unregister(connector); 862 drm_connector_cleanup(connector); 863 } 864 865 static const struct drm_connector_funcs hdmi_connector_funcs = { 866 .fill_modes = drm_helper_probe_single_connector_modes, 867 .detect = hdmi_detect, 868 .destroy = hdmi_connector_destroy, 869 .reset = drm_atomic_helper_connector_reset, 870 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 871 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 872 }; 873 874 static int hdmi_get_modes(struct drm_connector *connector) 875 { 876 struct hdmi_context *hdata = connector_to_hdmi(connector); 877 struct edid *edid; 878 int ret; 879 880 if (!hdata->ddc_adpt) 881 return -ENODEV; 882 883 edid = drm_get_edid(connector, hdata->ddc_adpt); 884 if (!edid) 885 return -ENODEV; 886 887 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid); 888 DRM_DEV_DEBUG_KMS(hdata->dev, "%s : width[%d] x height[%d]\n", 889 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"), 890 edid->width_cm, edid->height_cm); 891 892 drm_connector_update_edid_property(connector, edid); 893 cec_notifier_set_phys_addr_from_edid(hdata->notifier, edid); 894 895 ret = drm_add_edid_modes(connector, edid); 896 897 kfree(edid); 898 899 return ret; 900 } 901 902 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) 903 { 904 const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs; 905 int i; 906 907 for (i = 0; i < confs->count; i++) 908 if (confs->data[i].pixel_clock == pixel_clock) 909 return i; 910 911 DRM_DEV_DEBUG_KMS(hdata->dev, "Could not find phy config for %d\n", 912 pixel_clock); 913 return -EINVAL; 914 } 915 916 static int hdmi_mode_valid(struct drm_connector *connector, 917 struct drm_display_mode *mode) 918 { 919 struct hdmi_context *hdata = connector_to_hdmi(connector); 920 int ret; 921 922 DRM_DEV_DEBUG_KMS(hdata->dev, 923 "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", 924 mode->hdisplay, mode->vdisplay, mode->vrefresh, 925 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true : 926 false, mode->clock * 1000); 927 928 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000); 929 if (ret < 0) 930 return MODE_BAD; 931 932 return MODE_OK; 933 } 934 935 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { 936 .get_modes = hdmi_get_modes, 937 .mode_valid = hdmi_mode_valid, 938 }; 939 940 static int hdmi_create_connector(struct drm_encoder *encoder) 941 { 942 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 943 struct drm_connector *connector = &hdata->connector; 944 int ret; 945 946 connector->interlace_allowed = true; 947 connector->polled = DRM_CONNECTOR_POLL_HPD; 948 949 ret = drm_connector_init(hdata->drm_dev, connector, 950 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA); 951 if (ret) { 952 DRM_DEV_ERROR(hdata->dev, 953 "Failed to initialize connector with drm\n"); 954 return ret; 955 } 956 957 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); 958 drm_connector_attach_encoder(connector, encoder); 959 960 if (hdata->bridge) { 961 ret = drm_bridge_attach(encoder, hdata->bridge, NULL); 962 if (ret) 963 DRM_DEV_ERROR(hdata->dev, "Failed to attach bridge\n"); 964 } 965 966 return ret; 967 } 968 969 static bool hdmi_mode_fixup(struct drm_encoder *encoder, 970 const struct drm_display_mode *mode, 971 struct drm_display_mode *adjusted_mode) 972 { 973 struct drm_device *dev = encoder->dev; 974 struct drm_connector *connector; 975 struct drm_display_mode *m; 976 struct drm_connector_list_iter conn_iter; 977 int mode_ok; 978 979 drm_mode_set_crtcinfo(adjusted_mode, 0); 980 981 drm_connector_list_iter_begin(dev, &conn_iter); 982 drm_for_each_connector_iter(connector, &conn_iter) { 983 if (connector->encoder == encoder) 984 break; 985 } 986 if (connector) 987 drm_connector_get(connector); 988 drm_connector_list_iter_end(&conn_iter); 989 990 if (!connector) 991 return true; 992 993 mode_ok = hdmi_mode_valid(connector, adjusted_mode); 994 995 if (mode_ok == MODE_OK) 996 goto cleanup; 997 998 /* 999 * Find the most suitable mode and copy it to adjusted_mode. 1000 */ 1001 list_for_each_entry(m, &connector->modes, head) { 1002 mode_ok = hdmi_mode_valid(connector, m); 1003 1004 if (mode_ok == MODE_OK) { 1005 DRM_INFO("desired mode doesn't exist so\n"); 1006 DRM_INFO("use the most suitable mode among modes.\n"); 1007 1008 DRM_DEV_DEBUG_KMS(dev->dev, 1009 "Adjusted Mode: [%d]x[%d] [%d]Hz\n", 1010 m->hdisplay, m->vdisplay, 1011 m->vrefresh); 1012 1013 drm_mode_copy(adjusted_mode, m); 1014 break; 1015 } 1016 } 1017 1018 cleanup: 1019 drm_connector_put(connector); 1020 1021 return true; 1022 } 1023 1024 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq) 1025 { 1026 u32 n, cts; 1027 1028 cts = (freq % 9) ? 27000 : 30000; 1029 n = 128 * freq / (27000000 / cts); 1030 1031 hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n); 1032 hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts); 1033 hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts); 1034 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); 1035 } 1036 1037 static void hdmi_audio_config(struct hdmi_context *hdata) 1038 { 1039 u32 bit_ch = 1; 1040 u32 data_num, val; 1041 int i; 1042 1043 switch (hdata->audio.params.sample_width) { 1044 case 20: 1045 data_num = 2; 1046 break; 1047 case 24: 1048 data_num = 3; 1049 break; 1050 default: 1051 data_num = 1; 1052 bit_ch = 0; 1053 break; 1054 } 1055 1056 hdmi_reg_acr(hdata, hdata->audio.params.sample_rate); 1057 1058 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE 1059 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE 1060 | HDMI_I2S_MUX_ENABLE); 1061 1062 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN 1063 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); 1064 1065 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); 1066 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); 1067 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); 1068 1069 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01; 1070 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val); 1071 1072 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */ 1073 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5) 1074 | HDMI_I2S_SEL_LRCK(6)); 1075 1076 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(3) 1077 | HDMI_I2S_SEL_SDATA0(4)); 1078 1079 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1) 1080 | HDMI_I2S_SEL_SDATA2(2)); 1081 1082 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0)); 1083 1084 /* I2S_CON_1 & 2 */ 1085 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE 1086 | HDMI_I2S_L_CH_LOW_POL); 1087 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE 1088 | HDMI_I2S_SET_BIT_CH(bit_ch) 1089 | HDMI_I2S_SET_SDATA_BIT(data_num) 1090 | HDMI_I2S_BASIC_FORMAT); 1091 1092 /* Configuration of the audio channel status registers */ 1093 for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++) 1094 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i), 1095 hdata->audio.params.iec.status[i]); 1096 1097 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); 1098 } 1099 1100 static void hdmi_audio_control(struct hdmi_context *hdata) 1101 { 1102 bool enable = !hdata->audio.mute; 1103 1104 if (hdata->dvi_mode) 1105 return; 1106 1107 hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ? 1108 HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN); 1109 hdmi_reg_writemask(hdata, HDMI_CON_0, enable ? 1110 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); 1111 } 1112 1113 static void hdmi_start(struct hdmi_context *hdata, bool start) 1114 { 1115 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1116 u32 val = start ? HDMI_TG_EN : 0; 1117 1118 if (m->flags & DRM_MODE_FLAG_INTERLACE) 1119 val |= HDMI_FIELD_EN; 1120 1121 hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); 1122 hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN); 1123 } 1124 1125 static void hdmi_conf_init(struct hdmi_context *hdata) 1126 { 1127 /* disable HPD interrupts from HDMI IP block, use GPIO instead */ 1128 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL | 1129 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG); 1130 1131 /* choose HDMI mode */ 1132 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1133 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK); 1134 /* apply video pre-amble and guard band in HDMI mode only */ 1135 hdmi_reg_writeb(hdata, HDMI_CON_2, 0); 1136 /* disable bluescreen */ 1137 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN); 1138 1139 if (hdata->dvi_mode) { 1140 hdmi_reg_writemask(hdata, HDMI_MODE_SEL, 1141 HDMI_MODE_DVI_EN, HDMI_MODE_MASK); 1142 hdmi_reg_writeb(hdata, HDMI_CON_2, 1143 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS); 1144 } 1145 1146 if (hdata->drv_data->type == HDMI_TYPE13) { 1147 /* choose bluescreen (fecal) color */ 1148 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12); 1149 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34); 1150 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56); 1151 1152 /* enable AVI packet every vsync, fixes purple line problem */ 1153 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02); 1154 /* force RGB, look to CEA-861-D, table 7 for more detail */ 1155 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5); 1156 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5); 1157 1158 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02); 1159 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); 1160 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); 1161 } else { 1162 hdmi_reg_infoframes(hdata); 1163 1164 /* enable AVI packet every vsync, fixes purple line problem */ 1165 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5); 1166 } 1167 } 1168 1169 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata) 1170 { 1171 int tries; 1172 1173 for (tries = 0; tries < 10; ++tries) { 1174 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); 1175 1176 if (val & HDMI_PHY_STATUS_READY) { 1177 DRM_DEV_DEBUG_KMS(hdata->dev, 1178 "PLL stabilized after %d tries\n", 1179 tries); 1180 return; 1181 } 1182 usleep_range(10, 20); 1183 } 1184 1185 DRM_DEV_ERROR(hdata->dev, "PLL could not reach steady state\n"); 1186 } 1187 1188 static void hdmi_v13_mode_apply(struct hdmi_context *hdata) 1189 { 1190 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1191 unsigned int val; 1192 1193 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1194 hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3, 1195 (m->htotal << 12) | m->vtotal); 1196 1197 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 1198 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val); 1199 1200 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0; 1201 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val); 1202 1203 val = (m->hsync_start - m->hdisplay - 2); 1204 val |= ((m->hsync_end - m->hdisplay - 2) << 10); 1205 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20; 1206 hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val); 1207 1208 /* 1209 * Quirk requirement for exynos HDMI IP design, 1210 * 2 pixels less than the actual calculation for hsync_start 1211 * and end. 1212 */ 1213 1214 /* Following values & calculations differ for different type of modes */ 1215 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1216 val = ((m->vsync_end - m->vdisplay) / 2); 1217 val |= ((m->vsync_start - m->vdisplay) / 2) << 12; 1218 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1219 1220 val = m->vtotal / 2; 1221 val |= ((m->vtotal - m->vdisplay) / 2) << 11; 1222 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1223 1224 val = (m->vtotal + 1225 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2; 1226 val |= m->vtotal << 11; 1227 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val); 1228 1229 val = ((m->vtotal / 2) + 7); 1230 val |= ((m->vtotal / 2) + 2) << 12; 1231 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val); 1232 1233 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1234 val |= ((m->htotal / 2) + 1235 (m->hsync_start - m->hdisplay)) << 12; 1236 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val); 1237 1238 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1239 (m->vtotal - m->vdisplay) / 2); 1240 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1241 1242 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249); 1243 } else { 1244 val = m->vtotal; 1245 val |= (m->vtotal - m->vdisplay) << 11; 1246 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val); 1247 1248 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0); 1249 1250 val = (m->vsync_end - m->vdisplay); 1251 val |= ((m->vsync_start - m->vdisplay) << 12); 1252 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val); 1253 1254 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001); 1255 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001); 1256 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1257 m->vtotal - m->vdisplay); 1258 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1259 } 1260 1261 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1262 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); 1263 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); 1264 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1265 } 1266 1267 static void hdmi_v14_mode_apply(struct hdmi_context *hdata) 1268 { 1269 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1270 struct drm_display_mode *am = 1271 &hdata->encoder.crtc->state->adjusted_mode; 1272 int hquirk = 0; 1273 1274 /* 1275 * In case video mode coming from CRTC differs from requested one HDMI 1276 * sometimes is able to almost properly perform conversion - only 1277 * first line is distorted. 1278 */ 1279 if ((m->vdisplay != am->vdisplay) && 1280 (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366)) 1281 hquirk = 258; 1282 1283 hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); 1284 hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); 1285 hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal); 1286 hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1, 1287 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0); 1288 hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, 1289 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0); 1290 hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, 1291 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); 1292 1293 /* 1294 * Quirk requirement for exynos 5 HDMI IP design, 1295 * 2 pixels less than the actual calculation for hsync_start 1296 * and end. 1297 */ 1298 1299 /* Following values & calculations differ for different type of modes */ 1300 if (m->flags & DRM_MODE_FLAG_INTERLACE) { 1301 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1302 (m->vsync_end - m->vdisplay) / 2); 1303 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1304 (m->vsync_start - m->vdisplay) / 2); 1305 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2); 1306 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1307 (m->vtotal - m->vdisplay) / 2); 1308 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 1309 m->vtotal - m->vdisplay / 2); 1310 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal); 1311 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 1312 (m->vtotal / 2) + 7); 1313 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 1314 (m->vtotal / 2) + 2); 1315 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 1316 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1317 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 1318 (m->htotal / 2) + (m->hsync_start - m->hdisplay)); 1319 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1320 (m->vtotal - m->vdisplay) / 2); 1321 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2); 1322 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 1323 m->vtotal - m->vdisplay / 2); 1324 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2, 1325 (m->vtotal / 2) + 1); 1326 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 1327 (m->vtotal / 2) + 1); 1328 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 1329 (m->vtotal / 2) + 1); 1330 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0); 1331 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0); 1332 } else { 1333 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2, 1334 m->vsync_end - m->vdisplay); 1335 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2, 1336 m->vsync_start - m->vdisplay); 1337 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal); 1338 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2, 1339 m->vtotal - m->vdisplay); 1340 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff); 1341 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff); 1342 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff); 1343 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff); 1344 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff); 1345 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff); 1346 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2, 1347 m->vtotal - m->vdisplay); 1348 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay); 1349 } 1350 1351 hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2, 1352 m->hsync_start - m->hdisplay - 2); 1353 hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2, 1354 m->hsync_end - m->hdisplay - 2); 1355 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff); 1356 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff); 1357 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff); 1358 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff); 1359 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff); 1360 hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff); 1361 hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff); 1362 hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff); 1363 hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff); 1364 hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff); 1365 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff); 1366 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff); 1367 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff); 1368 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff); 1369 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff); 1370 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff); 1371 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff); 1372 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff); 1373 1374 hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); 1375 hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, 1376 m->htotal - m->hdisplay - hquirk); 1377 hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk); 1378 hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); 1379 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1380 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1); 1381 } 1382 1383 static void hdmi_mode_apply(struct hdmi_context *hdata) 1384 { 1385 if (hdata->drv_data->type == HDMI_TYPE13) 1386 hdmi_v13_mode_apply(hdata); 1387 else 1388 hdmi_v14_mode_apply(hdata); 1389 1390 hdmi_start(hdata, true); 1391 } 1392 1393 static void hdmiphy_conf_reset(struct hdmi_context *hdata) 1394 { 1395 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, 0, 1); 1396 usleep_range(10000, 12000); 1397 hdmi_reg_writemask(hdata, HDMI_CORE_RSTOUT, ~0, 1); 1398 usleep_range(10000, 12000); 1399 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); 1400 usleep_range(10000, 12000); 1401 hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); 1402 usleep_range(10000, 12000); 1403 } 1404 1405 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable) 1406 { 1407 u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET; 1408 1409 if (hdata->drv_data == &exynos5433_hdmi_driver_data) 1410 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE); 1411 } 1412 1413 static void hdmiphy_conf_apply(struct hdmi_context *hdata) 1414 { 1415 struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; 1416 int ret; 1417 const u8 *phy_conf; 1418 1419 ret = hdmi_find_phy_conf(hdata, m->clock * 1000); 1420 if (ret < 0) { 1421 DRM_DEV_ERROR(hdata->dev, "failed to find hdmiphy conf\n"); 1422 return; 1423 } 1424 phy_conf = hdata->drv_data->phy_confs.data[ret].conf; 1425 1426 hdmi_clk_set_parents(hdata, false); 1427 1428 hdmiphy_conf_reset(hdata); 1429 1430 hdmiphy_enable_mode_set(hdata, true); 1431 ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32); 1432 if (ret) { 1433 DRM_DEV_ERROR(hdata->dev, "failed to configure hdmiphy\n"); 1434 return; 1435 } 1436 hdmiphy_enable_mode_set(hdata, false); 1437 hdmi_clk_set_parents(hdata, true); 1438 usleep_range(10000, 12000); 1439 hdmiphy_wait_for_pll(hdata); 1440 } 1441 1442 /* Should be called with hdata->mutex mutex held */ 1443 static void hdmi_conf_apply(struct hdmi_context *hdata) 1444 { 1445 hdmi_start(hdata, false); 1446 hdmi_conf_init(hdata); 1447 hdmi_audio_config(hdata); 1448 hdmi_mode_apply(hdata); 1449 hdmi_audio_control(hdata); 1450 } 1451 1452 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) 1453 { 1454 if (!hdata->sysreg) 1455 return; 1456 1457 regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY, 1458 SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); 1459 } 1460 1461 /* Should be called with hdata->mutex mutex held. */ 1462 static void hdmiphy_enable(struct hdmi_context *hdata) 1463 { 1464 if (hdata->powered) 1465 return; 1466 1467 pm_runtime_get_sync(hdata->dev); 1468 1469 if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk)) 1470 DRM_DEV_DEBUG_KMS(hdata->dev, 1471 "failed to enable regulator bulk\n"); 1472 1473 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1474 PMU_HDMI_PHY_ENABLE_BIT, 1); 1475 1476 hdmi_set_refclk(hdata, true); 1477 1478 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN); 1479 1480 hdmiphy_conf_apply(hdata); 1481 1482 hdata->powered = true; 1483 } 1484 1485 /* Should be called with hdata->mutex mutex held. */ 1486 static void hdmiphy_disable(struct hdmi_context *hdata) 1487 { 1488 if (!hdata->powered) 1489 return; 1490 1491 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); 1492 1493 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); 1494 1495 hdmi_set_refclk(hdata, false); 1496 1497 regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, 1498 PMU_HDMI_PHY_ENABLE_BIT, 0); 1499 1500 regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); 1501 1502 pm_runtime_put_sync(hdata->dev); 1503 1504 hdata->powered = false; 1505 } 1506 1507 static void hdmi_enable(struct drm_encoder *encoder) 1508 { 1509 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1510 1511 mutex_lock(&hdata->mutex); 1512 1513 hdmiphy_enable(hdata); 1514 hdmi_conf_apply(hdata); 1515 1516 mutex_unlock(&hdata->mutex); 1517 } 1518 1519 static void hdmi_disable(struct drm_encoder *encoder) 1520 { 1521 struct hdmi_context *hdata = encoder_to_hdmi(encoder); 1522 1523 mutex_lock(&hdata->mutex); 1524 1525 if (hdata->powered) { 1526 /* 1527 * The SFRs of VP and Mixer are updated by Vertical Sync of 1528 * Timing generator which is a part of HDMI so the sequence 1529 * to disable TV Subsystem should be as following, 1530 * VP -> Mixer -> HDMI 1531 * 1532 * To achieve such sequence HDMI is disabled together with 1533 * HDMI PHY, via pipe clock callback. 1534 */ 1535 mutex_unlock(&hdata->mutex); 1536 cancel_delayed_work(&hdata->hotplug_work); 1537 cec_notifier_set_phys_addr(hdata->notifier, 1538 CEC_PHYS_ADDR_INVALID); 1539 return; 1540 } 1541 1542 mutex_unlock(&hdata->mutex); 1543 } 1544 1545 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { 1546 .mode_fixup = hdmi_mode_fixup, 1547 .enable = hdmi_enable, 1548 .disable = hdmi_disable, 1549 }; 1550 1551 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = { 1552 .destroy = drm_encoder_cleanup, 1553 }; 1554 1555 static void hdmi_audio_shutdown(struct device *dev, void *data) 1556 { 1557 struct hdmi_context *hdata = dev_get_drvdata(dev); 1558 1559 mutex_lock(&hdata->mutex); 1560 1561 hdata->audio.mute = true; 1562 1563 if (hdata->powered) 1564 hdmi_audio_control(hdata); 1565 1566 mutex_unlock(&hdata->mutex); 1567 } 1568 1569 static int hdmi_audio_hw_params(struct device *dev, void *data, 1570 struct hdmi_codec_daifmt *daifmt, 1571 struct hdmi_codec_params *params) 1572 { 1573 struct hdmi_context *hdata = dev_get_drvdata(dev); 1574 1575 if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv || 1576 daifmt->frame_clk_inv || daifmt->bit_clk_master || 1577 daifmt->frame_clk_master) { 1578 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1579 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1580 daifmt->bit_clk_master, 1581 daifmt->frame_clk_master); 1582 return -EINVAL; 1583 } 1584 1585 mutex_lock(&hdata->mutex); 1586 1587 hdata->audio.params = *params; 1588 1589 if (hdata->powered) { 1590 hdmi_audio_config(hdata); 1591 hdmi_audio_infoframe_apply(hdata); 1592 } 1593 1594 mutex_unlock(&hdata->mutex); 1595 1596 return 0; 1597 } 1598 1599 static int hdmi_audio_digital_mute(struct device *dev, void *data, bool mute) 1600 { 1601 struct hdmi_context *hdata = dev_get_drvdata(dev); 1602 1603 mutex_lock(&hdata->mutex); 1604 1605 hdata->audio.mute = mute; 1606 1607 if (hdata->powered) 1608 hdmi_audio_control(hdata); 1609 1610 mutex_unlock(&hdata->mutex); 1611 1612 return 0; 1613 } 1614 1615 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, 1616 size_t len) 1617 { 1618 struct hdmi_context *hdata = dev_get_drvdata(dev); 1619 struct drm_connector *connector = &hdata->connector; 1620 1621 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1622 1623 return 0; 1624 } 1625 1626 static const struct hdmi_codec_ops audio_codec_ops = { 1627 .hw_params = hdmi_audio_hw_params, 1628 .audio_shutdown = hdmi_audio_shutdown, 1629 .digital_mute = hdmi_audio_digital_mute, 1630 .get_eld = hdmi_audio_get_eld, 1631 }; 1632 1633 static int hdmi_register_audio_device(struct hdmi_context *hdata) 1634 { 1635 struct hdmi_codec_pdata codec_data = { 1636 .ops = &audio_codec_ops, 1637 .max_i2s_channels = 6, 1638 .i2s = 1, 1639 }; 1640 1641 hdata->audio.pdev = platform_device_register_data( 1642 hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1643 &codec_data, sizeof(codec_data)); 1644 1645 return PTR_ERR_OR_ZERO(hdata->audio.pdev); 1646 } 1647 1648 static void hdmi_hotplug_work_func(struct work_struct *work) 1649 { 1650 struct hdmi_context *hdata; 1651 1652 hdata = container_of(work, struct hdmi_context, hotplug_work.work); 1653 1654 if (hdata->drm_dev) 1655 drm_helper_hpd_irq_event(hdata->drm_dev); 1656 } 1657 1658 static irqreturn_t hdmi_irq_thread(int irq, void *arg) 1659 { 1660 struct hdmi_context *hdata = arg; 1661 1662 mod_delayed_work(system_wq, &hdata->hotplug_work, 1663 msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS)); 1664 1665 return IRQ_HANDLED; 1666 } 1667 1668 static int hdmi_clks_get(struct hdmi_context *hdata, 1669 const struct string_array_spec *names, 1670 struct clk **clks) 1671 { 1672 struct device *dev = hdata->dev; 1673 int i; 1674 1675 for (i = 0; i < names->count; ++i) { 1676 struct clk *clk = devm_clk_get(dev, names->data[i]); 1677 1678 if (IS_ERR(clk)) { 1679 int ret = PTR_ERR(clk); 1680 1681 dev_err(dev, "Cannot get clock %s, %d\n", 1682 names->data[i], ret); 1683 1684 return ret; 1685 } 1686 1687 clks[i] = clk; 1688 } 1689 1690 return 0; 1691 } 1692 1693 static int hdmi_clk_init(struct hdmi_context *hdata) 1694 { 1695 const struct hdmi_driver_data *drv_data = hdata->drv_data; 1696 int count = drv_data->clk_gates.count + drv_data->clk_muxes.count; 1697 struct device *dev = hdata->dev; 1698 struct clk **clks; 1699 int ret; 1700 1701 if (!count) 1702 return 0; 1703 1704 clks = devm_kcalloc(dev, count, sizeof(*clks), GFP_KERNEL); 1705 if (!clks) 1706 return -ENOMEM; 1707 1708 hdata->clk_gates = clks; 1709 hdata->clk_muxes = clks + drv_data->clk_gates.count; 1710 1711 ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates); 1712 if (ret) 1713 return ret; 1714 1715 return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes); 1716 } 1717 1718 1719 static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable) 1720 { 1721 struct hdmi_context *hdata = container_of(clk, struct hdmi_context, 1722 phy_clk); 1723 mutex_lock(&hdata->mutex); 1724 1725 if (enable) 1726 hdmiphy_enable(hdata); 1727 else 1728 hdmiphy_disable(hdata); 1729 1730 mutex_unlock(&hdata->mutex); 1731 } 1732 1733 static int hdmi_bridge_init(struct hdmi_context *hdata) 1734 { 1735 struct device *dev = hdata->dev; 1736 struct device_node *ep, *np; 1737 1738 ep = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1); 1739 if (!ep) 1740 return 0; 1741 1742 np = of_graph_get_remote_port_parent(ep); 1743 of_node_put(ep); 1744 if (!np) { 1745 DRM_DEV_ERROR(dev, "failed to get remote port parent"); 1746 return -EINVAL; 1747 } 1748 1749 hdata->bridge = of_drm_find_bridge(np); 1750 of_node_put(np); 1751 1752 if (!hdata->bridge) 1753 return -EPROBE_DEFER; 1754 1755 return 0; 1756 } 1757 1758 static int hdmi_resources_init(struct hdmi_context *hdata) 1759 { 1760 struct device *dev = hdata->dev; 1761 int i, ret; 1762 1763 DRM_DEV_DEBUG_KMS(dev, "HDMI resource init\n"); 1764 1765 hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); 1766 if (IS_ERR(hdata->hpd_gpio)) { 1767 DRM_DEV_ERROR(dev, "cannot get hpd gpio property\n"); 1768 return PTR_ERR(hdata->hpd_gpio); 1769 } 1770 1771 hdata->irq = gpiod_to_irq(hdata->hpd_gpio); 1772 if (hdata->irq < 0) { 1773 DRM_DEV_ERROR(dev, "failed to get GPIO irq\n"); 1774 return hdata->irq; 1775 } 1776 1777 ret = hdmi_clk_init(hdata); 1778 if (ret) 1779 return ret; 1780 1781 ret = hdmi_clk_set_parents(hdata, false); 1782 if (ret) 1783 return ret; 1784 1785 for (i = 0; i < ARRAY_SIZE(supply); ++i) 1786 hdata->regul_bulk[i].supply = supply[i]; 1787 1788 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk); 1789 if (ret) { 1790 if (ret != -EPROBE_DEFER) 1791 DRM_DEV_ERROR(dev, "failed to get regulators\n"); 1792 return ret; 1793 } 1794 1795 hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en"); 1796 1797 if (PTR_ERR(hdata->reg_hdmi_en) != -ENODEV) { 1798 if (IS_ERR(hdata->reg_hdmi_en)) 1799 return PTR_ERR(hdata->reg_hdmi_en); 1800 1801 ret = regulator_enable(hdata->reg_hdmi_en); 1802 if (ret) { 1803 DRM_DEV_ERROR(dev, 1804 "failed to enable hdmi-en regulator\n"); 1805 return ret; 1806 } 1807 } 1808 1809 return hdmi_bridge_init(hdata); 1810 } 1811 1812 static const struct of_device_id hdmi_match_types[] = { 1813 { 1814 .compatible = "samsung,exynos4210-hdmi", 1815 .data = &exynos4210_hdmi_driver_data, 1816 }, { 1817 .compatible = "samsung,exynos4212-hdmi", 1818 .data = &exynos4212_hdmi_driver_data, 1819 }, { 1820 .compatible = "samsung,exynos5420-hdmi", 1821 .data = &exynos5420_hdmi_driver_data, 1822 }, { 1823 .compatible = "samsung,exynos5433-hdmi", 1824 .data = &exynos5433_hdmi_driver_data, 1825 }, { 1826 /* end node */ 1827 } 1828 }; 1829 MODULE_DEVICE_TABLE (of, hdmi_match_types); 1830 1831 static int hdmi_bind(struct device *dev, struct device *master, void *data) 1832 { 1833 struct drm_device *drm_dev = data; 1834 struct hdmi_context *hdata = dev_get_drvdata(dev); 1835 struct drm_encoder *encoder = &hdata->encoder; 1836 struct exynos_drm_crtc *crtc; 1837 int ret; 1838 1839 hdata->drm_dev = drm_dev; 1840 1841 hdata->phy_clk.enable = hdmiphy_clk_enable; 1842 1843 drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs, 1844 DRM_MODE_ENCODER_TMDS, NULL); 1845 1846 drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs); 1847 1848 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_HDMI); 1849 if (ret < 0) 1850 return ret; 1851 1852 crtc = exynos_drm_crtc_get_by_type(drm_dev, EXYNOS_DISPLAY_TYPE_HDMI); 1853 crtc->pipe_clk = &hdata->phy_clk; 1854 1855 ret = hdmi_create_connector(encoder); 1856 if (ret) { 1857 DRM_DEV_ERROR(dev, "failed to create connector ret = %d\n", 1858 ret); 1859 drm_encoder_cleanup(encoder); 1860 return ret; 1861 } 1862 1863 return 0; 1864 } 1865 1866 static void hdmi_unbind(struct device *dev, struct device *master, void *data) 1867 { 1868 } 1869 1870 static const struct component_ops hdmi_component_ops = { 1871 .bind = hdmi_bind, 1872 .unbind = hdmi_unbind, 1873 }; 1874 1875 static int hdmi_get_ddc_adapter(struct hdmi_context *hdata) 1876 { 1877 const char *compatible_str = "samsung,exynos4210-hdmiddc"; 1878 struct device_node *np; 1879 struct i2c_adapter *adpt; 1880 1881 np = of_find_compatible_node(NULL, NULL, compatible_str); 1882 if (np) 1883 np = of_get_next_parent(np); 1884 else 1885 np = of_parse_phandle(hdata->dev->of_node, "ddc", 0); 1886 1887 if (!np) { 1888 DRM_DEV_ERROR(hdata->dev, 1889 "Failed to find ddc node in device tree\n"); 1890 return -ENODEV; 1891 } 1892 1893 adpt = of_find_i2c_adapter_by_node(np); 1894 of_node_put(np); 1895 1896 if (!adpt) { 1897 DRM_INFO("Failed to get ddc i2c adapter by node\n"); 1898 return -EPROBE_DEFER; 1899 } 1900 1901 hdata->ddc_adpt = adpt; 1902 1903 return 0; 1904 } 1905 1906 static int hdmi_get_phy_io(struct hdmi_context *hdata) 1907 { 1908 const char *compatible_str = "samsung,exynos4212-hdmiphy"; 1909 struct device_node *np; 1910 int ret = 0; 1911 1912 np = of_find_compatible_node(NULL, NULL, compatible_str); 1913 if (!np) { 1914 np = of_parse_phandle(hdata->dev->of_node, "phy", 0); 1915 if (!np) { 1916 DRM_DEV_ERROR(hdata->dev, 1917 "Failed to find hdmiphy node in device tree\n"); 1918 return -ENODEV; 1919 } 1920 } 1921 1922 if (hdata->drv_data->is_apb_phy) { 1923 hdata->regs_hdmiphy = of_iomap(np, 0); 1924 if (!hdata->regs_hdmiphy) { 1925 DRM_DEV_ERROR(hdata->dev, 1926 "failed to ioremap hdmi phy\n"); 1927 ret = -ENOMEM; 1928 goto out; 1929 } 1930 } else { 1931 hdata->hdmiphy_port = of_find_i2c_device_by_node(np); 1932 if (!hdata->hdmiphy_port) { 1933 DRM_INFO("Failed to get hdmi phy i2c client\n"); 1934 ret = -EPROBE_DEFER; 1935 goto out; 1936 } 1937 } 1938 1939 out: 1940 of_node_put(np); 1941 return ret; 1942 } 1943 1944 static int hdmi_probe(struct platform_device *pdev) 1945 { 1946 struct hdmi_audio_infoframe *audio_infoframe; 1947 struct device *dev = &pdev->dev; 1948 struct hdmi_context *hdata; 1949 struct resource *res; 1950 int ret; 1951 1952 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL); 1953 if (!hdata) 1954 return -ENOMEM; 1955 1956 hdata->drv_data = of_device_get_match_data(dev); 1957 1958 platform_set_drvdata(pdev, hdata); 1959 1960 hdata->dev = dev; 1961 1962 mutex_init(&hdata->mutex); 1963 1964 ret = hdmi_resources_init(hdata); 1965 if (ret) { 1966 if (ret != -EPROBE_DEFER) 1967 DRM_DEV_ERROR(dev, "hdmi_resources_init failed\n"); 1968 return ret; 1969 } 1970 1971 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1972 hdata->regs = devm_ioremap_resource(dev, res); 1973 if (IS_ERR(hdata->regs)) { 1974 ret = PTR_ERR(hdata->regs); 1975 return ret; 1976 } 1977 1978 ret = hdmi_get_ddc_adapter(hdata); 1979 if (ret) 1980 return ret; 1981 1982 ret = hdmi_get_phy_io(hdata); 1983 if (ret) 1984 goto err_ddc; 1985 1986 INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func); 1987 1988 ret = devm_request_threaded_irq(dev, hdata->irq, NULL, 1989 hdmi_irq_thread, IRQF_TRIGGER_RISING | 1990 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1991 "hdmi", hdata); 1992 if (ret) { 1993 DRM_DEV_ERROR(dev, "failed to register hdmi interrupt\n"); 1994 goto err_hdmiphy; 1995 } 1996 1997 hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, 1998 "samsung,syscon-phandle"); 1999 if (IS_ERR(hdata->pmureg)) { 2000 DRM_DEV_ERROR(dev, "syscon regmap lookup failed.\n"); 2001 ret = -EPROBE_DEFER; 2002 goto err_hdmiphy; 2003 } 2004 2005 if (hdata->drv_data->has_sysreg) { 2006 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 2007 "samsung,sysreg-phandle"); 2008 if (IS_ERR(hdata->sysreg)) { 2009 DRM_DEV_ERROR(dev, "sysreg regmap lookup failed.\n"); 2010 ret = -EPROBE_DEFER; 2011 goto err_hdmiphy; 2012 } 2013 } 2014 2015 hdata->notifier = cec_notifier_get(&pdev->dev); 2016 if (hdata->notifier == NULL) { 2017 ret = -ENOMEM; 2018 goto err_hdmiphy; 2019 } 2020 2021 pm_runtime_enable(dev); 2022 2023 audio_infoframe = &hdata->audio.infoframe; 2024 hdmi_audio_infoframe_init(audio_infoframe); 2025 audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 2026 audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 2027 audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 2028 audio_infoframe->channels = 2; 2029 2030 ret = hdmi_register_audio_device(hdata); 2031 if (ret) 2032 goto err_notifier_put; 2033 2034 ret = component_add(&pdev->dev, &hdmi_component_ops); 2035 if (ret) 2036 goto err_unregister_audio; 2037 2038 return ret; 2039 2040 err_unregister_audio: 2041 platform_device_unregister(hdata->audio.pdev); 2042 2043 err_notifier_put: 2044 cec_notifier_put(hdata->notifier); 2045 pm_runtime_disable(dev); 2046 2047 err_hdmiphy: 2048 if (hdata->hdmiphy_port) 2049 put_device(&hdata->hdmiphy_port->dev); 2050 if (hdata->regs_hdmiphy) 2051 iounmap(hdata->regs_hdmiphy); 2052 err_ddc: 2053 put_device(&hdata->ddc_adpt->dev); 2054 2055 return ret; 2056 } 2057 2058 static int hdmi_remove(struct platform_device *pdev) 2059 { 2060 struct hdmi_context *hdata = platform_get_drvdata(pdev); 2061 2062 cancel_delayed_work_sync(&hdata->hotplug_work); 2063 cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); 2064 2065 component_del(&pdev->dev, &hdmi_component_ops); 2066 platform_device_unregister(hdata->audio.pdev); 2067 2068 cec_notifier_put(hdata->notifier); 2069 pm_runtime_disable(&pdev->dev); 2070 2071 if (!IS_ERR(hdata->reg_hdmi_en)) 2072 regulator_disable(hdata->reg_hdmi_en); 2073 2074 if (hdata->hdmiphy_port) 2075 put_device(&hdata->hdmiphy_port->dev); 2076 2077 if (hdata->regs_hdmiphy) 2078 iounmap(hdata->regs_hdmiphy); 2079 2080 put_device(&hdata->ddc_adpt->dev); 2081 2082 mutex_destroy(&hdata->mutex); 2083 2084 return 0; 2085 } 2086 2087 static int __maybe_unused exynos_hdmi_suspend(struct device *dev) 2088 { 2089 struct hdmi_context *hdata = dev_get_drvdata(dev); 2090 2091 hdmi_clk_disable_gates(hdata); 2092 2093 return 0; 2094 } 2095 2096 static int __maybe_unused exynos_hdmi_resume(struct device *dev) 2097 { 2098 struct hdmi_context *hdata = dev_get_drvdata(dev); 2099 int ret; 2100 2101 ret = hdmi_clk_enable_gates(hdata); 2102 if (ret < 0) 2103 return ret; 2104 2105 return 0; 2106 } 2107 2108 static const struct dev_pm_ops exynos_hdmi_pm_ops = { 2109 SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL) 2110 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2111 pm_runtime_force_resume) 2112 }; 2113 2114 struct platform_driver hdmi_driver = { 2115 .probe = hdmi_probe, 2116 .remove = hdmi_remove, 2117 .driver = { 2118 .name = "exynos-hdmi", 2119 .owner = THIS_MODULE, 2120 .pm = &exynos_hdmi_pm_ops, 2121 .of_match_table = hdmi_match_types, 2122 }, 2123 }; 2124