1 /* 2 * Copyright (C) 2017 Samsung Electronics Co.Ltd 3 * Author: 4 * Andrzej Pietrasiewicz <andrzej.p@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundationr 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/component.h> 13 #include <linux/err.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/of_device.h> 19 #include <linux/pm_runtime.h> 20 21 #include <drm/drmP.h> 22 #include <drm/exynos_drm.h> 23 #include "regs-scaler.h" 24 #include "exynos_drm_fb.h" 25 #include "exynos_drm_drv.h" 26 #include "exynos_drm_iommu.h" 27 #include "exynos_drm_ipp.h" 28 29 #define scaler_read(offset) readl(scaler->regs + (offset)) 30 #define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset)) 31 #define SCALER_MAX_CLK 4 32 #define SCALER_AUTOSUSPEND_DELAY 2000 33 34 struct scaler_data { 35 const char *clk_name[SCALER_MAX_CLK]; 36 unsigned int num_clk; 37 const struct exynos_drm_ipp_formats *formats; 38 unsigned int num_formats; 39 }; 40 41 struct scaler_context { 42 struct exynos_drm_ipp ipp; 43 struct drm_device *drm_dev; 44 struct device *dev; 45 void __iomem *regs; 46 struct clk *clock[SCALER_MAX_CLK]; 47 struct exynos_drm_ipp_task *task; 48 const struct scaler_data *scaler_data; 49 }; 50 51 static u32 scaler_get_format(u32 drm_fmt) 52 { 53 switch (drm_fmt) { 54 case DRM_FORMAT_NV21: 55 return SCALER_YUV420_2P_UV; 56 case DRM_FORMAT_NV12: 57 return SCALER_YUV420_2P_VU; 58 case DRM_FORMAT_YUV420: 59 return SCALER_YUV420_3P; 60 case DRM_FORMAT_YUYV: 61 return SCALER_YUV422_1P_YUYV; 62 case DRM_FORMAT_UYVY: 63 return SCALER_YUV422_1P_UYVY; 64 case DRM_FORMAT_YVYU: 65 return SCALER_YUV422_1P_YVYU; 66 case DRM_FORMAT_NV61: 67 return SCALER_YUV422_2P_UV; 68 case DRM_FORMAT_NV16: 69 return SCALER_YUV422_2P_VU; 70 case DRM_FORMAT_YUV422: 71 return SCALER_YUV422_3P; 72 case DRM_FORMAT_NV42: 73 return SCALER_YUV444_2P_UV; 74 case DRM_FORMAT_NV24: 75 return SCALER_YUV444_2P_VU; 76 case DRM_FORMAT_YUV444: 77 return SCALER_YUV444_3P; 78 case DRM_FORMAT_RGB565: 79 return SCALER_RGB_565; 80 case DRM_FORMAT_XRGB1555: 81 return SCALER_ARGB1555; 82 case DRM_FORMAT_ARGB1555: 83 return SCALER_ARGB1555; 84 case DRM_FORMAT_XRGB4444: 85 return SCALER_ARGB4444; 86 case DRM_FORMAT_ARGB4444: 87 return SCALER_ARGB4444; 88 case DRM_FORMAT_XRGB8888: 89 return SCALER_ARGB8888; 90 case DRM_FORMAT_ARGB8888: 91 return SCALER_ARGB8888; 92 case DRM_FORMAT_RGBX8888: 93 return SCALER_RGBA8888; 94 case DRM_FORMAT_RGBA8888: 95 return SCALER_RGBA8888; 96 default: 97 break; 98 } 99 100 return 0; 101 } 102 103 static inline void scaler_enable_int(struct scaler_context *scaler) 104 { 105 u32 val; 106 107 val = SCALER_INT_EN_TIMEOUT | 108 SCALER_INT_EN_ILLEGAL_BLEND | 109 SCALER_INT_EN_ILLEGAL_RATIO | 110 SCALER_INT_EN_ILLEGAL_DST_HEIGHT | 111 SCALER_INT_EN_ILLEGAL_DST_WIDTH | 112 SCALER_INT_EN_ILLEGAL_DST_V_POS | 113 SCALER_INT_EN_ILLEGAL_DST_H_POS | 114 SCALER_INT_EN_ILLEGAL_DST_C_SPAN | 115 SCALER_INT_EN_ILLEGAL_DST_Y_SPAN | 116 SCALER_INT_EN_ILLEGAL_DST_CR_BASE | 117 SCALER_INT_EN_ILLEGAL_DST_CB_BASE | 118 SCALER_INT_EN_ILLEGAL_DST_Y_BASE | 119 SCALER_INT_EN_ILLEGAL_DST_COLOR | 120 SCALER_INT_EN_ILLEGAL_SRC_HEIGHT | 121 SCALER_INT_EN_ILLEGAL_SRC_WIDTH | 122 SCALER_INT_EN_ILLEGAL_SRC_CV_POS | 123 SCALER_INT_EN_ILLEGAL_SRC_CH_POS | 124 SCALER_INT_EN_ILLEGAL_SRC_YV_POS | 125 SCALER_INT_EN_ILLEGAL_SRC_YH_POS | 126 SCALER_INT_EN_ILLEGAL_DST_SPAN | 127 SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN | 128 SCALER_INT_EN_ILLEGAL_SRC_CR_BASE | 129 SCALER_INT_EN_ILLEGAL_SRC_CB_BASE | 130 SCALER_INT_EN_ILLEGAL_SRC_Y_BASE | 131 SCALER_INT_EN_ILLEGAL_SRC_COLOR | 132 SCALER_INT_EN_FRAME_END; 133 scaler_write(val, SCALER_INT_EN); 134 } 135 136 static inline void scaler_set_src_fmt(struct scaler_context *scaler, 137 u32 src_fmt) 138 { 139 u32 val; 140 141 val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt); 142 scaler_write(val, SCALER_SRC_CFG); 143 } 144 145 static inline void scaler_set_src_base(struct scaler_context *scaler, 146 struct exynos_drm_ipp_buffer *src_buf) 147 { 148 static unsigned int bases[] = { 149 SCALER_SRC_Y_BASE, 150 SCALER_SRC_CB_BASE, 151 SCALER_SRC_CR_BASE, 152 }; 153 int i; 154 155 for (i = 0; i < src_buf->format->num_planes; ++i) 156 scaler_write(src_buf->dma_addr[i], bases[i]); 157 } 158 159 static inline void scaler_set_src_span(struct scaler_context *scaler, 160 struct exynos_drm_ipp_buffer *src_buf) 161 { 162 u32 val; 163 164 val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] / 165 src_buf->format->cpp[0]); 166 167 if (src_buf->format->num_planes > 1) 168 val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]); 169 170 scaler_write(val, SCALER_SRC_SPAN); 171 } 172 173 static inline void scaler_set_src_luma_pos(struct scaler_context *scaler, 174 struct drm_exynos_ipp_task_rect *src_pos) 175 { 176 u32 val; 177 178 val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2); 179 val |= SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2); 180 scaler_write(val, SCALER_SRC_Y_POS); 181 scaler_write(val, SCALER_SRC_C_POS); /* ATTENTION! */ 182 } 183 184 static inline void scaler_set_src_wh(struct scaler_context *scaler, 185 struct drm_exynos_ipp_task_rect *src_pos) 186 { 187 u32 val; 188 189 val = SCALER_SRC_WH_SET_WIDTH(src_pos->w); 190 val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h); 191 scaler_write(val, SCALER_SRC_WH); 192 } 193 194 static inline void scaler_set_dst_fmt(struct scaler_context *scaler, 195 u32 dst_fmt) 196 { 197 u32 val; 198 199 val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt); 200 scaler_write(val, SCALER_DST_CFG); 201 } 202 203 static inline void scaler_set_dst_base(struct scaler_context *scaler, 204 struct exynos_drm_ipp_buffer *dst_buf) 205 { 206 static unsigned int bases[] = { 207 SCALER_DST_Y_BASE, 208 SCALER_DST_CB_BASE, 209 SCALER_DST_CR_BASE, 210 }; 211 int i; 212 213 for (i = 0; i < dst_buf->format->num_planes; ++i) 214 scaler_write(dst_buf->dma_addr[i], bases[i]); 215 } 216 217 static inline void scaler_set_dst_span(struct scaler_context *scaler, 218 struct exynos_drm_ipp_buffer *dst_buf) 219 { 220 u32 val; 221 222 val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] / 223 dst_buf->format->cpp[0]); 224 225 if (dst_buf->format->num_planes > 1) 226 val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]); 227 228 scaler_write(val, SCALER_DST_SPAN); 229 } 230 231 static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler, 232 struct drm_exynos_ipp_task_rect *dst_pos) 233 { 234 u32 val; 235 236 val = SCALER_DST_WH_SET_WIDTH(dst_pos->w); 237 val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h); 238 scaler_write(val, SCALER_DST_WH); 239 } 240 241 static inline void scaler_set_dst_wh(struct scaler_context *scaler, 242 struct drm_exynos_ipp_task_rect *dst_pos) 243 { 244 u32 val; 245 246 val = SCALER_DST_POS_SET_H_POS(dst_pos->x); 247 val |= SCALER_DST_POS_SET_V_POS(dst_pos->y); 248 scaler_write(val, SCALER_DST_POS); 249 } 250 251 static inline void scaler_set_hv_ratio(struct scaler_context *scaler, 252 unsigned int rotation, 253 struct drm_exynos_ipp_task_rect *src_pos, 254 struct drm_exynos_ipp_task_rect *dst_pos) 255 { 256 u32 val, h_ratio, v_ratio; 257 258 if (drm_rotation_90_or_270(rotation)) { 259 h_ratio = (src_pos->h << 16) / dst_pos->w; 260 v_ratio = (src_pos->w << 16) / dst_pos->h; 261 } else { 262 h_ratio = (src_pos->w << 16) / dst_pos->w; 263 v_ratio = (src_pos->h << 16) / dst_pos->h; 264 } 265 266 val = SCALER_H_RATIO_SET(h_ratio); 267 scaler_write(val, SCALER_H_RATIO); 268 269 val = SCALER_V_RATIO_SET(v_ratio); 270 scaler_write(val, SCALER_V_RATIO); 271 } 272 273 static inline void scaler_set_rotation(struct scaler_context *scaler, 274 unsigned int rotation) 275 { 276 u32 val = 0; 277 278 if (rotation & DRM_MODE_ROTATE_90) 279 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90); 280 else if (rotation & DRM_MODE_ROTATE_180) 281 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180); 282 else if (rotation & DRM_MODE_ROTATE_270) 283 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270); 284 if (rotation & DRM_MODE_REFLECT_X) 285 val |= SCALER_ROT_CFG_FLIP_X_EN; 286 if (rotation & DRM_MODE_REFLECT_Y) 287 val |= SCALER_ROT_CFG_FLIP_Y_EN; 288 scaler_write(val, SCALER_ROT_CFG); 289 } 290 291 static inline void scaler_set_csc(struct scaler_context *scaler, 292 const struct drm_format_info *fmt) 293 { 294 static const u32 csc_mtx[2][3][3] = { 295 { /* YCbCr to RGB */ 296 {0x254, 0x000, 0x331}, 297 {0x254, 0xf38, 0xe60}, 298 {0x254, 0x409, 0x000}, 299 }, 300 { /* RGB to YCbCr */ 301 {0x084, 0x102, 0x032}, 302 {0xfb4, 0xf6b, 0x0e1}, 303 {0x0e1, 0xf44, 0xfdc}, 304 }, 305 }; 306 int i, j, dir; 307 308 switch (fmt->format) { 309 case DRM_FORMAT_RGB565: 310 case DRM_FORMAT_XRGB1555: 311 case DRM_FORMAT_ARGB1555: 312 case DRM_FORMAT_XRGB4444: 313 case DRM_FORMAT_ARGB4444: 314 case DRM_FORMAT_XRGB8888: 315 case DRM_FORMAT_ARGB8888: 316 case DRM_FORMAT_RGBX8888: 317 case DRM_FORMAT_RGBA8888: 318 dir = 1; 319 break; 320 default: 321 dir = 0; 322 } 323 324 for (i = 0; i < 3; i++) 325 for (j = 0; j < 3; j++) 326 scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i)); 327 } 328 329 static inline void scaler_set_timer(struct scaler_context *scaler, 330 unsigned int timer, unsigned int divider) 331 { 332 u32 val; 333 334 val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE; 335 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer); 336 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider); 337 scaler_write(val, SCALER_TIMEOUT_CTRL); 338 } 339 340 static inline void scaler_start_hw(struct scaler_context *scaler) 341 { 342 scaler_write(SCALER_CFG_START_CMD, SCALER_CFG); 343 } 344 345 static int scaler_commit(struct exynos_drm_ipp *ipp, 346 struct exynos_drm_ipp_task *task) 347 { 348 struct scaler_context *scaler = 349 container_of(ipp, struct scaler_context, ipp); 350 351 u32 src_fmt = scaler_get_format(task->src.buf.fourcc); 352 struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect; 353 354 u32 dst_fmt = scaler_get_format(task->dst.buf.fourcc); 355 struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect; 356 357 scaler->task = task; 358 359 pm_runtime_get_sync(scaler->dev); 360 361 scaler_set_src_fmt(scaler, src_fmt); 362 scaler_set_src_base(scaler, &task->src); 363 scaler_set_src_span(scaler, &task->src); 364 scaler_set_src_luma_pos(scaler, src_pos); 365 scaler_set_src_wh(scaler, src_pos); 366 367 scaler_set_dst_fmt(scaler, dst_fmt); 368 scaler_set_dst_base(scaler, &task->dst); 369 scaler_set_dst_span(scaler, &task->dst); 370 scaler_set_dst_luma_pos(scaler, dst_pos); 371 scaler_set_dst_wh(scaler, dst_pos); 372 373 scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos); 374 scaler_set_rotation(scaler, task->transform.rotation); 375 376 scaler_set_csc(scaler, task->src.format); 377 378 scaler_set_timer(scaler, 0xffff, 0xf); 379 380 scaler_enable_int(scaler); 381 scaler_start_hw(scaler); 382 383 return 0; 384 } 385 386 static struct exynos_drm_ipp_funcs ipp_funcs = { 387 .commit = scaler_commit, 388 }; 389 390 static inline void scaler_disable_int(struct scaler_context *scaler) 391 { 392 scaler_write(0, SCALER_INT_EN); 393 } 394 395 static inline u32 scaler_get_int_status(struct scaler_context *scaler) 396 { 397 return scaler_read(SCALER_INT_STATUS); 398 } 399 400 static inline int scaler_task_done(u32 val) 401 { 402 return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL; 403 } 404 405 static irqreturn_t scaler_irq_handler(int irq, void *arg) 406 { 407 struct scaler_context *scaler = arg; 408 409 u32 val = scaler_get_int_status(scaler); 410 411 scaler_disable_int(scaler); 412 413 if (scaler->task) { 414 struct exynos_drm_ipp_task *task = scaler->task; 415 416 scaler->task = NULL; 417 pm_runtime_mark_last_busy(scaler->dev); 418 pm_runtime_put_autosuspend(scaler->dev); 419 exynos_drm_ipp_task_done(task, scaler_task_done(val)); 420 } 421 422 return IRQ_HANDLED; 423 } 424 425 static int scaler_bind(struct device *dev, struct device *master, void *data) 426 { 427 struct scaler_context *scaler = dev_get_drvdata(dev); 428 struct drm_device *drm_dev = data; 429 struct exynos_drm_ipp *ipp = &scaler->ipp; 430 431 scaler->drm_dev = drm_dev; 432 drm_iommu_attach_device(drm_dev, dev); 433 434 exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs, 435 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE | 436 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT, 437 scaler->scaler_data->formats, 438 scaler->scaler_data->num_formats, "scaler"); 439 440 dev_info(dev, "The exynos scaler has been probed successfully\n"); 441 442 return 0; 443 } 444 445 static void scaler_unbind(struct device *dev, struct device *master, 446 void *data) 447 { 448 struct scaler_context *scaler = dev_get_drvdata(dev); 449 struct drm_device *drm_dev = data; 450 struct exynos_drm_ipp *ipp = &scaler->ipp; 451 452 exynos_drm_ipp_unregister(drm_dev, ipp); 453 drm_iommu_detach_device(scaler->drm_dev, scaler->dev); 454 } 455 456 static const struct component_ops scaler_component_ops = { 457 .bind = scaler_bind, 458 .unbind = scaler_unbind, 459 }; 460 461 static int scaler_probe(struct platform_device *pdev) 462 { 463 struct device *dev = &pdev->dev; 464 struct resource *regs_res; 465 struct scaler_context *scaler; 466 int irq; 467 int ret, i; 468 469 scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL); 470 if (!scaler) 471 return -ENOMEM; 472 473 scaler->scaler_data = 474 (struct scaler_data *)of_device_get_match_data(dev); 475 476 scaler->dev = dev; 477 regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 478 scaler->regs = devm_ioremap_resource(dev, regs_res); 479 if (IS_ERR(scaler->regs)) 480 return PTR_ERR(scaler->regs); 481 482 irq = platform_get_irq(pdev, 0); 483 if (irq < 0) { 484 dev_err(dev, "failed to get irq\n"); 485 return irq; 486 } 487 488 ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler, 489 IRQF_ONESHOT, "drm_scaler", scaler); 490 if (ret < 0) { 491 dev_err(dev, "failed to request irq\n"); 492 return ret; 493 } 494 495 for (i = 0; i < scaler->scaler_data->num_clk; ++i) { 496 scaler->clock[i] = devm_clk_get(dev, 497 scaler->scaler_data->clk_name[i]); 498 if (IS_ERR(scaler->clock[i])) { 499 dev_err(dev, "failed to get clock\n"); 500 return PTR_ERR(scaler->clock[i]); 501 } 502 } 503 504 pm_runtime_use_autosuspend(dev); 505 pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY); 506 pm_runtime_enable(dev); 507 platform_set_drvdata(pdev, scaler); 508 509 ret = component_add(dev, &scaler_component_ops); 510 if (ret) 511 goto err_ippdrv_register; 512 513 return 0; 514 515 err_ippdrv_register: 516 pm_runtime_dont_use_autosuspend(dev); 517 pm_runtime_disable(dev); 518 return ret; 519 } 520 521 static int scaler_remove(struct platform_device *pdev) 522 { 523 struct device *dev = &pdev->dev; 524 525 component_del(dev, &scaler_component_ops); 526 pm_runtime_dont_use_autosuspend(dev); 527 pm_runtime_disable(dev); 528 529 return 0; 530 } 531 532 #ifdef CONFIG_PM 533 534 static int clk_disable_unprepare_wrapper(struct clk *clk) 535 { 536 clk_disable_unprepare(clk); 537 538 return 0; 539 } 540 541 static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable) 542 { 543 int (*clk_fun)(struct clk *clk), i; 544 545 clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper; 546 547 for (i = 0; i < scaler->scaler_data->num_clk; ++i) 548 clk_fun(scaler->clock[i]); 549 550 return 0; 551 } 552 553 static int scaler_runtime_suspend(struct device *dev) 554 { 555 struct scaler_context *scaler = dev_get_drvdata(dev); 556 557 return scaler_clk_ctrl(scaler, false); 558 } 559 560 static int scaler_runtime_resume(struct device *dev) 561 { 562 struct scaler_context *scaler = dev_get_drvdata(dev); 563 564 return scaler_clk_ctrl(scaler, true); 565 } 566 #endif 567 568 static const struct dev_pm_ops scaler_pm_ops = { 569 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 570 pm_runtime_force_resume) 571 SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL) 572 }; 573 574 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = { 575 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 576 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) }, 577 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 578 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 579 }; 580 581 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = { 582 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 583 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) }, 584 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 585 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 586 }; 587 588 static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = { 589 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 590 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 591 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 592 }; 593 594 static const struct exynos_drm_ipp_formats exynos5420_formats[] = { 595 /* SCALER_YUV420_2P_UV */ 596 { IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) }, 597 598 /* SCALER_YUV420_2P_VU */ 599 { IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) }, 600 601 /* SCALER_YUV420_3P */ 602 { IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) }, 603 604 /* SCALER_YUV422_1P_YUYV */ 605 { IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) }, 606 607 /* SCALER_YUV422_1P_UYVY */ 608 { IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) }, 609 610 /* SCALER_YUV422_1P_YVYU */ 611 { IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) }, 612 613 /* SCALER_YUV422_2P_UV */ 614 { IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) }, 615 616 /* SCALER_YUV422_2P_VU */ 617 { IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) }, 618 619 /* SCALER_YUV422_3P */ 620 { IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) }, 621 622 /* SCALER_YUV444_2P_UV */ 623 { IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) }, 624 625 /* SCALER_YUV444_2P_VU */ 626 { IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) }, 627 628 /* SCALER_YUV444_3P */ 629 { IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) }, 630 631 /* SCALER_RGB_565 */ 632 { IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) }, 633 634 /* SCALER_ARGB1555 */ 635 { IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) }, 636 637 /* SCALER_ARGB1555 */ 638 { IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) }, 639 640 /* SCALER_ARGB4444 */ 641 { IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) }, 642 643 /* SCALER_ARGB4444 */ 644 { IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) }, 645 646 /* SCALER_ARGB8888 */ 647 { IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) }, 648 649 /* SCALER_ARGB8888 */ 650 { IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) }, 651 652 /* SCALER_RGBA8888 */ 653 { IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) }, 654 655 /* SCALER_RGBA8888 */ 656 { IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) }, 657 }; 658 659 static const struct scaler_data exynos5420_data = { 660 .clk_name = {"mscl"}, 661 .num_clk = 1, 662 .formats = exynos5420_formats, 663 .num_formats = ARRAY_SIZE(exynos5420_formats), 664 }; 665 666 static const struct scaler_data exynos5433_data = { 667 .clk_name = {"pclk", "aclk", "aclk_xiu"}, 668 .num_clk = 3, 669 .formats = exynos5420_formats, /* intentional */ 670 .num_formats = ARRAY_SIZE(exynos5420_formats), 671 }; 672 673 static const struct of_device_id exynos_scaler_match[] = { 674 { 675 .compatible = "samsung,exynos5420-scaler", 676 .data = &exynos5420_data, 677 }, { 678 .compatible = "samsung,exynos5433-scaler", 679 .data = &exynos5433_data, 680 }, { 681 }, 682 }; 683 MODULE_DEVICE_TABLE(of, exynos_scaler_match); 684 685 struct platform_driver scaler_driver = { 686 .probe = scaler_probe, 687 .remove = scaler_remove, 688 .driver = { 689 .name = "exynos-scaler", 690 .owner = THIS_MODULE, 691 .pm = &scaler_pm_ops, 692 .of_match_table = exynos_scaler_match, 693 }, 694 }; 695