1 /* 2 * Copyright (C) 2017 Samsung Electronics Co.Ltd 3 * Author: 4 * Andrzej Pietrasiewicz <andrzej.p@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundationr 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/component.h> 13 #include <linux/err.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/of_device.h> 19 #include <linux/pm_runtime.h> 20 21 #include <drm/drmP.h> 22 #include <drm/exynos_drm.h> 23 #include "regs-scaler.h" 24 #include "exynos_drm_fb.h" 25 #include "exynos_drm_drv.h" 26 #include "exynos_drm_iommu.h" 27 #include "exynos_drm_ipp.h" 28 29 #define scaler_read(offset) readl(scaler->regs + (offset)) 30 #define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset)) 31 #define SCALER_MAX_CLK 4 32 #define SCALER_AUTOSUSPEND_DELAY 2000 33 #define SCALER_RESET_WAIT_RETRIES 100 34 35 struct scaler_data { 36 const char *clk_name[SCALER_MAX_CLK]; 37 unsigned int num_clk; 38 const struct exynos_drm_ipp_formats *formats; 39 unsigned int num_formats; 40 }; 41 42 struct scaler_context { 43 struct exynos_drm_ipp ipp; 44 struct drm_device *drm_dev; 45 struct device *dev; 46 void __iomem *regs; 47 struct clk *clock[SCALER_MAX_CLK]; 48 struct exynos_drm_ipp_task *task; 49 const struct scaler_data *scaler_data; 50 }; 51 52 static u32 scaler_get_format(u32 drm_fmt) 53 { 54 switch (drm_fmt) { 55 case DRM_FORMAT_NV12: 56 return SCALER_YUV420_2P_UV; 57 case DRM_FORMAT_NV21: 58 return SCALER_YUV420_2P_VU; 59 case DRM_FORMAT_YUV420: 60 return SCALER_YUV420_3P; 61 case DRM_FORMAT_YUYV: 62 return SCALER_YUV422_1P_YUYV; 63 case DRM_FORMAT_UYVY: 64 return SCALER_YUV422_1P_UYVY; 65 case DRM_FORMAT_YVYU: 66 return SCALER_YUV422_1P_YVYU; 67 case DRM_FORMAT_NV16: 68 return SCALER_YUV422_2P_UV; 69 case DRM_FORMAT_NV61: 70 return SCALER_YUV422_2P_VU; 71 case DRM_FORMAT_YUV422: 72 return SCALER_YUV422_3P; 73 case DRM_FORMAT_NV24: 74 return SCALER_YUV444_2P_UV; 75 case DRM_FORMAT_NV42: 76 return SCALER_YUV444_2P_VU; 77 case DRM_FORMAT_YUV444: 78 return SCALER_YUV444_3P; 79 case DRM_FORMAT_RGB565: 80 return SCALER_RGB_565; 81 case DRM_FORMAT_XRGB1555: 82 return SCALER_ARGB1555; 83 case DRM_FORMAT_ARGB1555: 84 return SCALER_ARGB1555; 85 case DRM_FORMAT_XRGB4444: 86 return SCALER_ARGB4444; 87 case DRM_FORMAT_ARGB4444: 88 return SCALER_ARGB4444; 89 case DRM_FORMAT_XRGB8888: 90 return SCALER_ARGB8888; 91 case DRM_FORMAT_ARGB8888: 92 return SCALER_ARGB8888; 93 case DRM_FORMAT_RGBX8888: 94 return SCALER_RGBA8888; 95 case DRM_FORMAT_RGBA8888: 96 return SCALER_RGBA8888; 97 default: 98 break; 99 } 100 101 return 0; 102 } 103 104 static inline int scaler_reset(struct scaler_context *scaler) 105 { 106 int retry = SCALER_RESET_WAIT_RETRIES; 107 108 scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG); 109 do { 110 cpu_relax(); 111 } while (retry > 1 && 112 scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET); 113 do { 114 cpu_relax(); 115 scaler_write(1, SCALER_INT_EN); 116 } while (retry > 0 && scaler_read(SCALER_INT_EN) != 1); 117 118 return retry ? 0 : -EIO; 119 } 120 121 static inline void scaler_enable_int(struct scaler_context *scaler) 122 { 123 u32 val; 124 125 val = SCALER_INT_EN_TIMEOUT | 126 SCALER_INT_EN_ILLEGAL_BLEND | 127 SCALER_INT_EN_ILLEGAL_RATIO | 128 SCALER_INT_EN_ILLEGAL_DST_HEIGHT | 129 SCALER_INT_EN_ILLEGAL_DST_WIDTH | 130 SCALER_INT_EN_ILLEGAL_DST_V_POS | 131 SCALER_INT_EN_ILLEGAL_DST_H_POS | 132 SCALER_INT_EN_ILLEGAL_DST_C_SPAN | 133 SCALER_INT_EN_ILLEGAL_DST_Y_SPAN | 134 SCALER_INT_EN_ILLEGAL_DST_CR_BASE | 135 SCALER_INT_EN_ILLEGAL_DST_CB_BASE | 136 SCALER_INT_EN_ILLEGAL_DST_Y_BASE | 137 SCALER_INT_EN_ILLEGAL_DST_COLOR | 138 SCALER_INT_EN_ILLEGAL_SRC_HEIGHT | 139 SCALER_INT_EN_ILLEGAL_SRC_WIDTH | 140 SCALER_INT_EN_ILLEGAL_SRC_CV_POS | 141 SCALER_INT_EN_ILLEGAL_SRC_CH_POS | 142 SCALER_INT_EN_ILLEGAL_SRC_YV_POS | 143 SCALER_INT_EN_ILLEGAL_SRC_YH_POS | 144 SCALER_INT_EN_ILLEGAL_DST_SPAN | 145 SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN | 146 SCALER_INT_EN_ILLEGAL_SRC_CR_BASE | 147 SCALER_INT_EN_ILLEGAL_SRC_CB_BASE | 148 SCALER_INT_EN_ILLEGAL_SRC_Y_BASE | 149 SCALER_INT_EN_ILLEGAL_SRC_COLOR | 150 SCALER_INT_EN_FRAME_END; 151 scaler_write(val, SCALER_INT_EN); 152 } 153 154 static inline void scaler_set_src_fmt(struct scaler_context *scaler, 155 u32 src_fmt) 156 { 157 u32 val; 158 159 val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt); 160 scaler_write(val, SCALER_SRC_CFG); 161 } 162 163 static inline void scaler_set_src_base(struct scaler_context *scaler, 164 struct exynos_drm_ipp_buffer *src_buf) 165 { 166 static unsigned int bases[] = { 167 SCALER_SRC_Y_BASE, 168 SCALER_SRC_CB_BASE, 169 SCALER_SRC_CR_BASE, 170 }; 171 int i; 172 173 for (i = 0; i < src_buf->format->num_planes; ++i) 174 scaler_write(src_buf->dma_addr[i], bases[i]); 175 } 176 177 static inline void scaler_set_src_span(struct scaler_context *scaler, 178 struct exynos_drm_ipp_buffer *src_buf) 179 { 180 u32 val; 181 182 val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] / 183 src_buf->format->cpp[0]); 184 185 if (src_buf->format->num_planes > 1) 186 val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]); 187 188 scaler_write(val, SCALER_SRC_SPAN); 189 } 190 191 static inline void scaler_set_src_luma_pos(struct scaler_context *scaler, 192 struct drm_exynos_ipp_task_rect *src_pos) 193 { 194 u32 val; 195 196 val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2); 197 val |= SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2); 198 scaler_write(val, SCALER_SRC_Y_POS); 199 scaler_write(val, SCALER_SRC_C_POS); /* ATTENTION! */ 200 } 201 202 static inline void scaler_set_src_wh(struct scaler_context *scaler, 203 struct drm_exynos_ipp_task_rect *src_pos) 204 { 205 u32 val; 206 207 val = SCALER_SRC_WH_SET_WIDTH(src_pos->w); 208 val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h); 209 scaler_write(val, SCALER_SRC_WH); 210 } 211 212 static inline void scaler_set_dst_fmt(struct scaler_context *scaler, 213 u32 dst_fmt) 214 { 215 u32 val; 216 217 val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt); 218 scaler_write(val, SCALER_DST_CFG); 219 } 220 221 static inline void scaler_set_dst_base(struct scaler_context *scaler, 222 struct exynos_drm_ipp_buffer *dst_buf) 223 { 224 static unsigned int bases[] = { 225 SCALER_DST_Y_BASE, 226 SCALER_DST_CB_BASE, 227 SCALER_DST_CR_BASE, 228 }; 229 int i; 230 231 for (i = 0; i < dst_buf->format->num_planes; ++i) 232 scaler_write(dst_buf->dma_addr[i], bases[i]); 233 } 234 235 static inline void scaler_set_dst_span(struct scaler_context *scaler, 236 struct exynos_drm_ipp_buffer *dst_buf) 237 { 238 u32 val; 239 240 val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] / 241 dst_buf->format->cpp[0]); 242 243 if (dst_buf->format->num_planes > 1) 244 val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]); 245 246 scaler_write(val, SCALER_DST_SPAN); 247 } 248 249 static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler, 250 struct drm_exynos_ipp_task_rect *dst_pos) 251 { 252 u32 val; 253 254 val = SCALER_DST_WH_SET_WIDTH(dst_pos->w); 255 val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h); 256 scaler_write(val, SCALER_DST_WH); 257 } 258 259 static inline void scaler_set_dst_wh(struct scaler_context *scaler, 260 struct drm_exynos_ipp_task_rect *dst_pos) 261 { 262 u32 val; 263 264 val = SCALER_DST_POS_SET_H_POS(dst_pos->x); 265 val |= SCALER_DST_POS_SET_V_POS(dst_pos->y); 266 scaler_write(val, SCALER_DST_POS); 267 } 268 269 static inline void scaler_set_hv_ratio(struct scaler_context *scaler, 270 unsigned int rotation, 271 struct drm_exynos_ipp_task_rect *src_pos, 272 struct drm_exynos_ipp_task_rect *dst_pos) 273 { 274 u32 val, h_ratio, v_ratio; 275 276 if (drm_rotation_90_or_270(rotation)) { 277 h_ratio = (src_pos->h << 16) / dst_pos->w; 278 v_ratio = (src_pos->w << 16) / dst_pos->h; 279 } else { 280 h_ratio = (src_pos->w << 16) / dst_pos->w; 281 v_ratio = (src_pos->h << 16) / dst_pos->h; 282 } 283 284 val = SCALER_H_RATIO_SET(h_ratio); 285 scaler_write(val, SCALER_H_RATIO); 286 287 val = SCALER_V_RATIO_SET(v_ratio); 288 scaler_write(val, SCALER_V_RATIO); 289 } 290 291 static inline void scaler_set_rotation(struct scaler_context *scaler, 292 unsigned int rotation) 293 { 294 u32 val = 0; 295 296 if (rotation & DRM_MODE_ROTATE_90) 297 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90); 298 else if (rotation & DRM_MODE_ROTATE_180) 299 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180); 300 else if (rotation & DRM_MODE_ROTATE_270) 301 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270); 302 if (rotation & DRM_MODE_REFLECT_X) 303 val |= SCALER_ROT_CFG_FLIP_X_EN; 304 if (rotation & DRM_MODE_REFLECT_Y) 305 val |= SCALER_ROT_CFG_FLIP_Y_EN; 306 scaler_write(val, SCALER_ROT_CFG); 307 } 308 309 static inline void scaler_set_csc(struct scaler_context *scaler, 310 const struct drm_format_info *fmt) 311 { 312 static const u32 csc_mtx[2][3][3] = { 313 { /* YCbCr to RGB */ 314 {0x254, 0x000, 0x331}, 315 {0x254, 0xf38, 0xe60}, 316 {0x254, 0x409, 0x000}, 317 }, 318 { /* RGB to YCbCr */ 319 {0x084, 0x102, 0x032}, 320 {0xfb4, 0xf6b, 0x0e1}, 321 {0x0e1, 0xf44, 0xfdc}, 322 }, 323 }; 324 int i, j, dir; 325 326 switch (fmt->format) { 327 case DRM_FORMAT_RGB565: 328 case DRM_FORMAT_XRGB1555: 329 case DRM_FORMAT_ARGB1555: 330 case DRM_FORMAT_XRGB4444: 331 case DRM_FORMAT_ARGB4444: 332 case DRM_FORMAT_XRGB8888: 333 case DRM_FORMAT_ARGB8888: 334 case DRM_FORMAT_RGBX8888: 335 case DRM_FORMAT_RGBA8888: 336 dir = 1; 337 break; 338 default: 339 dir = 0; 340 } 341 342 for (i = 0; i < 3; i++) 343 for (j = 0; j < 3; j++) 344 scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i)); 345 } 346 347 static inline void scaler_set_timer(struct scaler_context *scaler, 348 unsigned int timer, unsigned int divider) 349 { 350 u32 val; 351 352 val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE; 353 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer); 354 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider); 355 scaler_write(val, SCALER_TIMEOUT_CTRL); 356 } 357 358 static inline void scaler_start_hw(struct scaler_context *scaler) 359 { 360 scaler_write(SCALER_CFG_START_CMD, SCALER_CFG); 361 } 362 363 static int scaler_commit(struct exynos_drm_ipp *ipp, 364 struct exynos_drm_ipp_task *task) 365 { 366 struct scaler_context *scaler = 367 container_of(ipp, struct scaler_context, ipp); 368 369 u32 src_fmt = scaler_get_format(task->src.buf.fourcc); 370 struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect; 371 372 u32 dst_fmt = scaler_get_format(task->dst.buf.fourcc); 373 struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect; 374 375 pm_runtime_get_sync(scaler->dev); 376 if (scaler_reset(scaler)) { 377 pm_runtime_put(scaler->dev); 378 return -EIO; 379 } 380 381 scaler->task = task; 382 383 scaler_set_src_fmt(scaler, src_fmt); 384 scaler_set_src_base(scaler, &task->src); 385 scaler_set_src_span(scaler, &task->src); 386 scaler_set_src_luma_pos(scaler, src_pos); 387 scaler_set_src_wh(scaler, src_pos); 388 389 scaler_set_dst_fmt(scaler, dst_fmt); 390 scaler_set_dst_base(scaler, &task->dst); 391 scaler_set_dst_span(scaler, &task->dst); 392 scaler_set_dst_luma_pos(scaler, dst_pos); 393 scaler_set_dst_wh(scaler, dst_pos); 394 395 scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos); 396 scaler_set_rotation(scaler, task->transform.rotation); 397 398 scaler_set_csc(scaler, task->src.format); 399 400 scaler_set_timer(scaler, 0xffff, 0xf); 401 402 scaler_enable_int(scaler); 403 scaler_start_hw(scaler); 404 405 return 0; 406 } 407 408 static struct exynos_drm_ipp_funcs ipp_funcs = { 409 .commit = scaler_commit, 410 }; 411 412 static inline void scaler_disable_int(struct scaler_context *scaler) 413 { 414 scaler_write(0, SCALER_INT_EN); 415 } 416 417 static inline u32 scaler_get_int_status(struct scaler_context *scaler) 418 { 419 u32 val = scaler_read(SCALER_INT_STATUS); 420 421 scaler_write(val, SCALER_INT_STATUS); 422 423 return val; 424 } 425 426 static inline int scaler_task_done(u32 val) 427 { 428 return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL; 429 } 430 431 static irqreturn_t scaler_irq_handler(int irq, void *arg) 432 { 433 struct scaler_context *scaler = arg; 434 435 u32 val = scaler_get_int_status(scaler); 436 437 scaler_disable_int(scaler); 438 439 if (scaler->task) { 440 struct exynos_drm_ipp_task *task = scaler->task; 441 442 scaler->task = NULL; 443 pm_runtime_mark_last_busy(scaler->dev); 444 pm_runtime_put_autosuspend(scaler->dev); 445 exynos_drm_ipp_task_done(task, scaler_task_done(val)); 446 } 447 448 return IRQ_HANDLED; 449 } 450 451 static int scaler_bind(struct device *dev, struct device *master, void *data) 452 { 453 struct scaler_context *scaler = dev_get_drvdata(dev); 454 struct drm_device *drm_dev = data; 455 struct exynos_drm_ipp *ipp = &scaler->ipp; 456 457 scaler->drm_dev = drm_dev; 458 drm_iommu_attach_device(drm_dev, dev); 459 460 exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs, 461 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE | 462 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT, 463 scaler->scaler_data->formats, 464 scaler->scaler_data->num_formats, "scaler"); 465 466 dev_info(dev, "The exynos scaler has been probed successfully\n"); 467 468 return 0; 469 } 470 471 static void scaler_unbind(struct device *dev, struct device *master, 472 void *data) 473 { 474 struct scaler_context *scaler = dev_get_drvdata(dev); 475 struct drm_device *drm_dev = data; 476 struct exynos_drm_ipp *ipp = &scaler->ipp; 477 478 exynos_drm_ipp_unregister(drm_dev, ipp); 479 drm_iommu_detach_device(scaler->drm_dev, scaler->dev); 480 } 481 482 static const struct component_ops scaler_component_ops = { 483 .bind = scaler_bind, 484 .unbind = scaler_unbind, 485 }; 486 487 static int scaler_probe(struct platform_device *pdev) 488 { 489 struct device *dev = &pdev->dev; 490 struct resource *regs_res; 491 struct scaler_context *scaler; 492 int irq; 493 int ret, i; 494 495 scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL); 496 if (!scaler) 497 return -ENOMEM; 498 499 scaler->scaler_data = 500 (struct scaler_data *)of_device_get_match_data(dev); 501 502 scaler->dev = dev; 503 regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 504 scaler->regs = devm_ioremap_resource(dev, regs_res); 505 if (IS_ERR(scaler->regs)) 506 return PTR_ERR(scaler->regs); 507 508 irq = platform_get_irq(pdev, 0); 509 if (irq < 0) { 510 dev_err(dev, "failed to get irq\n"); 511 return irq; 512 } 513 514 ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler, 515 IRQF_ONESHOT, "drm_scaler", scaler); 516 if (ret < 0) { 517 dev_err(dev, "failed to request irq\n"); 518 return ret; 519 } 520 521 for (i = 0; i < scaler->scaler_data->num_clk; ++i) { 522 scaler->clock[i] = devm_clk_get(dev, 523 scaler->scaler_data->clk_name[i]); 524 if (IS_ERR(scaler->clock[i])) { 525 dev_err(dev, "failed to get clock\n"); 526 return PTR_ERR(scaler->clock[i]); 527 } 528 } 529 530 pm_runtime_use_autosuspend(dev); 531 pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY); 532 pm_runtime_enable(dev); 533 platform_set_drvdata(pdev, scaler); 534 535 ret = component_add(dev, &scaler_component_ops); 536 if (ret) 537 goto err_ippdrv_register; 538 539 return 0; 540 541 err_ippdrv_register: 542 pm_runtime_dont_use_autosuspend(dev); 543 pm_runtime_disable(dev); 544 return ret; 545 } 546 547 static int scaler_remove(struct platform_device *pdev) 548 { 549 struct device *dev = &pdev->dev; 550 551 component_del(dev, &scaler_component_ops); 552 pm_runtime_dont_use_autosuspend(dev); 553 pm_runtime_disable(dev); 554 555 return 0; 556 } 557 558 #ifdef CONFIG_PM 559 560 static int clk_disable_unprepare_wrapper(struct clk *clk) 561 { 562 clk_disable_unprepare(clk); 563 564 return 0; 565 } 566 567 static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable) 568 { 569 int (*clk_fun)(struct clk *clk), i; 570 571 clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper; 572 573 for (i = 0; i < scaler->scaler_data->num_clk; ++i) 574 clk_fun(scaler->clock[i]); 575 576 return 0; 577 } 578 579 static int scaler_runtime_suspend(struct device *dev) 580 { 581 struct scaler_context *scaler = dev_get_drvdata(dev); 582 583 return scaler_clk_ctrl(scaler, false); 584 } 585 586 static int scaler_runtime_resume(struct device *dev) 587 { 588 struct scaler_context *scaler = dev_get_drvdata(dev); 589 590 return scaler_clk_ctrl(scaler, true); 591 } 592 #endif 593 594 static const struct dev_pm_ops scaler_pm_ops = { 595 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 596 pm_runtime_force_resume) 597 SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL) 598 }; 599 600 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = { 601 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 602 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) }, 603 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 604 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 605 }; 606 607 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = { 608 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 609 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) }, 610 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 611 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 612 }; 613 614 static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = { 615 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 616 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 617 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 618 }; 619 620 static const struct exynos_drm_ipp_formats exynos5420_formats[] = { 621 /* SCALER_YUV420_2P_UV */ 622 { IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) }, 623 624 /* SCALER_YUV420_2P_VU */ 625 { IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) }, 626 627 /* SCALER_YUV420_3P */ 628 { IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) }, 629 630 /* SCALER_YUV422_1P_YUYV */ 631 { IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) }, 632 633 /* SCALER_YUV422_1P_UYVY */ 634 { IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) }, 635 636 /* SCALER_YUV422_1P_YVYU */ 637 { IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) }, 638 639 /* SCALER_YUV422_2P_UV */ 640 { IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) }, 641 642 /* SCALER_YUV422_2P_VU */ 643 { IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) }, 644 645 /* SCALER_YUV422_3P */ 646 { IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) }, 647 648 /* SCALER_YUV444_2P_UV */ 649 { IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) }, 650 651 /* SCALER_YUV444_2P_VU */ 652 { IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) }, 653 654 /* SCALER_YUV444_3P */ 655 { IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) }, 656 657 /* SCALER_RGB_565 */ 658 { IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) }, 659 660 /* SCALER_ARGB1555 */ 661 { IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) }, 662 663 /* SCALER_ARGB1555 */ 664 { IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) }, 665 666 /* SCALER_ARGB4444 */ 667 { IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) }, 668 669 /* SCALER_ARGB4444 */ 670 { IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) }, 671 672 /* SCALER_ARGB8888 */ 673 { IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) }, 674 675 /* SCALER_ARGB8888 */ 676 { IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) }, 677 678 /* SCALER_RGBA8888 */ 679 { IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) }, 680 681 /* SCALER_RGBA8888 */ 682 { IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) }, 683 }; 684 685 static const struct scaler_data exynos5420_data = { 686 .clk_name = {"mscl"}, 687 .num_clk = 1, 688 .formats = exynos5420_formats, 689 .num_formats = ARRAY_SIZE(exynos5420_formats), 690 }; 691 692 static const struct scaler_data exynos5433_data = { 693 .clk_name = {"pclk", "aclk", "aclk_xiu"}, 694 .num_clk = 3, 695 .formats = exynos5420_formats, /* intentional */ 696 .num_formats = ARRAY_SIZE(exynos5420_formats), 697 }; 698 699 static const struct of_device_id exynos_scaler_match[] = { 700 { 701 .compatible = "samsung,exynos5420-scaler", 702 .data = &exynos5420_data, 703 }, { 704 .compatible = "samsung,exynos5433-scaler", 705 .data = &exynos5433_data, 706 }, { 707 }, 708 }; 709 MODULE_DEVICE_TABLE(of, exynos_scaler_match); 710 711 struct platform_driver scaler_driver = { 712 .probe = scaler_probe, 713 .remove = scaler_remove, 714 .driver = { 715 .name = "exynos-scaler", 716 .owner = THIS_MODULE, 717 .pm = &scaler_pm_ops, 718 .of_match_table = exynos_scaler_match, 719 }, 720 }; 721