1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 Samsung Electronics Co.Ltd 4 * Author: 5 * Andrzej Pietrasiewicz <andrzejtp2010@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/err.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 18 #include <drm/drm_fourcc.h> 19 #include <drm/exynos_drm.h> 20 21 #include "exynos_drm_drv.h" 22 #include "exynos_drm_fb.h" 23 #include "exynos_drm_ipp.h" 24 #include "regs-scaler.h" 25 26 #define scaler_read(offset) readl(scaler->regs + (offset)) 27 #define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset)) 28 #define SCALER_MAX_CLK 4 29 #define SCALER_AUTOSUSPEND_DELAY 2000 30 #define SCALER_RESET_WAIT_RETRIES 100 31 32 struct scaler_data { 33 const char *clk_name[SCALER_MAX_CLK]; 34 unsigned int num_clk; 35 const struct exynos_drm_ipp_formats *formats; 36 unsigned int num_formats; 37 }; 38 39 struct scaler_context { 40 struct exynos_drm_ipp ipp; 41 struct drm_device *drm_dev; 42 struct device *dev; 43 void __iomem *regs; 44 struct clk *clock[SCALER_MAX_CLK]; 45 struct exynos_drm_ipp_task *task; 46 const struct scaler_data *scaler_data; 47 }; 48 49 struct scaler_format { 50 u32 drm_fmt; 51 u32 internal_fmt; 52 u32 chroma_tile_w; 53 u32 chroma_tile_h; 54 }; 55 56 static const struct scaler_format scaler_formats[] = { 57 { DRM_FORMAT_NV12, SCALER_YUV420_2P_UV, 8, 8 }, 58 { DRM_FORMAT_NV21, SCALER_YUV420_2P_VU, 8, 8 }, 59 { DRM_FORMAT_YUV420, SCALER_YUV420_3P, 8, 8 }, 60 { DRM_FORMAT_YUYV, SCALER_YUV422_1P_YUYV, 16, 16 }, 61 { DRM_FORMAT_UYVY, SCALER_YUV422_1P_UYVY, 16, 16 }, 62 { DRM_FORMAT_YVYU, SCALER_YUV422_1P_YVYU, 16, 16 }, 63 { DRM_FORMAT_NV16, SCALER_YUV422_2P_UV, 8, 16 }, 64 { DRM_FORMAT_NV61, SCALER_YUV422_2P_VU, 8, 16 }, 65 { DRM_FORMAT_YUV422, SCALER_YUV422_3P, 8, 16 }, 66 { DRM_FORMAT_NV24, SCALER_YUV444_2P_UV, 16, 16 }, 67 { DRM_FORMAT_NV42, SCALER_YUV444_2P_VU, 16, 16 }, 68 { DRM_FORMAT_YUV444, SCALER_YUV444_3P, 16, 16 }, 69 { DRM_FORMAT_RGB565, SCALER_RGB_565, 0, 0 }, 70 { DRM_FORMAT_XRGB1555, SCALER_ARGB1555, 0, 0 }, 71 { DRM_FORMAT_ARGB1555, SCALER_ARGB1555, 0, 0 }, 72 { DRM_FORMAT_XRGB4444, SCALER_ARGB4444, 0, 0 }, 73 { DRM_FORMAT_ARGB4444, SCALER_ARGB4444, 0, 0 }, 74 { DRM_FORMAT_XRGB8888, SCALER_ARGB8888, 0, 0 }, 75 { DRM_FORMAT_ARGB8888, SCALER_ARGB8888, 0, 0 }, 76 { DRM_FORMAT_RGBX8888, SCALER_RGBA8888, 0, 0 }, 77 { DRM_FORMAT_RGBA8888, SCALER_RGBA8888, 0, 0 }, 78 }; 79 80 static const struct scaler_format *scaler_get_format(u32 drm_fmt) 81 { 82 int i; 83 84 for (i = 0; i < ARRAY_SIZE(scaler_formats); i++) 85 if (scaler_formats[i].drm_fmt == drm_fmt) 86 return &scaler_formats[i]; 87 88 return NULL; 89 } 90 91 static inline int scaler_reset(struct scaler_context *scaler) 92 { 93 int retry = SCALER_RESET_WAIT_RETRIES; 94 95 scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG); 96 do { 97 cpu_relax(); 98 } while (--retry > 1 && 99 scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET); 100 do { 101 cpu_relax(); 102 scaler_write(1, SCALER_INT_EN); 103 } while (--retry > 0 && scaler_read(SCALER_INT_EN) != 1); 104 105 return retry ? 0 : -EIO; 106 } 107 108 static inline void scaler_enable_int(struct scaler_context *scaler) 109 { 110 u32 val; 111 112 val = SCALER_INT_EN_TIMEOUT | 113 SCALER_INT_EN_ILLEGAL_BLEND | 114 SCALER_INT_EN_ILLEGAL_RATIO | 115 SCALER_INT_EN_ILLEGAL_DST_HEIGHT | 116 SCALER_INT_EN_ILLEGAL_DST_WIDTH | 117 SCALER_INT_EN_ILLEGAL_DST_V_POS | 118 SCALER_INT_EN_ILLEGAL_DST_H_POS | 119 SCALER_INT_EN_ILLEGAL_DST_C_SPAN | 120 SCALER_INT_EN_ILLEGAL_DST_Y_SPAN | 121 SCALER_INT_EN_ILLEGAL_DST_CR_BASE | 122 SCALER_INT_EN_ILLEGAL_DST_CB_BASE | 123 SCALER_INT_EN_ILLEGAL_DST_Y_BASE | 124 SCALER_INT_EN_ILLEGAL_DST_COLOR | 125 SCALER_INT_EN_ILLEGAL_SRC_HEIGHT | 126 SCALER_INT_EN_ILLEGAL_SRC_WIDTH | 127 SCALER_INT_EN_ILLEGAL_SRC_CV_POS | 128 SCALER_INT_EN_ILLEGAL_SRC_CH_POS | 129 SCALER_INT_EN_ILLEGAL_SRC_YV_POS | 130 SCALER_INT_EN_ILLEGAL_SRC_YH_POS | 131 SCALER_INT_EN_ILLEGAL_DST_SPAN | 132 SCALER_INT_EN_ILLEGAL_SRC_Y_SPAN | 133 SCALER_INT_EN_ILLEGAL_SRC_CR_BASE | 134 SCALER_INT_EN_ILLEGAL_SRC_CB_BASE | 135 SCALER_INT_EN_ILLEGAL_SRC_Y_BASE | 136 SCALER_INT_EN_ILLEGAL_SRC_COLOR | 137 SCALER_INT_EN_FRAME_END; 138 scaler_write(val, SCALER_INT_EN); 139 } 140 141 static inline void scaler_set_src_fmt(struct scaler_context *scaler, 142 u32 src_fmt, u32 tile) 143 { 144 u32 val; 145 146 val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10); 147 scaler_write(val, SCALER_SRC_CFG); 148 } 149 150 static inline void scaler_set_src_base(struct scaler_context *scaler, 151 struct exynos_drm_ipp_buffer *src_buf) 152 { 153 static unsigned int bases[] = { 154 SCALER_SRC_Y_BASE, 155 SCALER_SRC_CB_BASE, 156 SCALER_SRC_CR_BASE, 157 }; 158 int i; 159 160 for (i = 0; i < src_buf->format->num_planes; ++i) 161 scaler_write(src_buf->dma_addr[i], bases[i]); 162 } 163 164 static inline void scaler_set_src_span(struct scaler_context *scaler, 165 struct exynos_drm_ipp_buffer *src_buf) 166 { 167 u32 val; 168 169 val = SCALER_SRC_SPAN_SET_Y_SPAN(src_buf->buf.pitch[0] / 170 src_buf->format->cpp[0]); 171 172 if (src_buf->format->num_planes > 1) 173 val |= SCALER_SRC_SPAN_SET_C_SPAN(src_buf->buf.pitch[1]); 174 175 scaler_write(val, SCALER_SRC_SPAN); 176 } 177 178 static inline void scaler_set_src_luma_chroma_pos(struct scaler_context *scaler, 179 struct drm_exynos_ipp_task_rect *src_pos, 180 const struct scaler_format *fmt) 181 { 182 u32 val; 183 184 val = SCALER_SRC_Y_POS_SET_YH_POS(src_pos->x << 2); 185 val |= SCALER_SRC_Y_POS_SET_YV_POS(src_pos->y << 2); 186 scaler_write(val, SCALER_SRC_Y_POS); 187 val = SCALER_SRC_C_POS_SET_CH_POS( 188 (src_pos->x * fmt->chroma_tile_w / 16) << 2); 189 val |= SCALER_SRC_C_POS_SET_CV_POS( 190 (src_pos->y * fmt->chroma_tile_h / 16) << 2); 191 scaler_write(val, SCALER_SRC_C_POS); 192 } 193 194 static inline void scaler_set_src_wh(struct scaler_context *scaler, 195 struct drm_exynos_ipp_task_rect *src_pos) 196 { 197 u32 val; 198 199 val = SCALER_SRC_WH_SET_WIDTH(src_pos->w); 200 val |= SCALER_SRC_WH_SET_HEIGHT(src_pos->h); 201 scaler_write(val, SCALER_SRC_WH); 202 } 203 204 static inline void scaler_set_dst_fmt(struct scaler_context *scaler, 205 u32 dst_fmt) 206 { 207 u32 val; 208 209 val = SCALER_DST_CFG_SET_COLOR_FORMAT(dst_fmt); 210 scaler_write(val, SCALER_DST_CFG); 211 } 212 213 static inline void scaler_set_dst_base(struct scaler_context *scaler, 214 struct exynos_drm_ipp_buffer *dst_buf) 215 { 216 static unsigned int bases[] = { 217 SCALER_DST_Y_BASE, 218 SCALER_DST_CB_BASE, 219 SCALER_DST_CR_BASE, 220 }; 221 int i; 222 223 for (i = 0; i < dst_buf->format->num_planes; ++i) 224 scaler_write(dst_buf->dma_addr[i], bases[i]); 225 } 226 227 static inline void scaler_set_dst_span(struct scaler_context *scaler, 228 struct exynos_drm_ipp_buffer *dst_buf) 229 { 230 u32 val; 231 232 val = SCALER_DST_SPAN_SET_Y_SPAN(dst_buf->buf.pitch[0] / 233 dst_buf->format->cpp[0]); 234 235 if (dst_buf->format->num_planes > 1) 236 val |= SCALER_DST_SPAN_SET_C_SPAN(dst_buf->buf.pitch[1]); 237 238 scaler_write(val, SCALER_DST_SPAN); 239 } 240 241 static inline void scaler_set_dst_luma_pos(struct scaler_context *scaler, 242 struct drm_exynos_ipp_task_rect *dst_pos) 243 { 244 u32 val; 245 246 val = SCALER_DST_WH_SET_WIDTH(dst_pos->w); 247 val |= SCALER_DST_WH_SET_HEIGHT(dst_pos->h); 248 scaler_write(val, SCALER_DST_WH); 249 } 250 251 static inline void scaler_set_dst_wh(struct scaler_context *scaler, 252 struct drm_exynos_ipp_task_rect *dst_pos) 253 { 254 u32 val; 255 256 val = SCALER_DST_POS_SET_H_POS(dst_pos->x); 257 val |= SCALER_DST_POS_SET_V_POS(dst_pos->y); 258 scaler_write(val, SCALER_DST_POS); 259 } 260 261 static inline void scaler_set_hv_ratio(struct scaler_context *scaler, 262 unsigned int rotation, 263 struct drm_exynos_ipp_task_rect *src_pos, 264 struct drm_exynos_ipp_task_rect *dst_pos) 265 { 266 u32 val, h_ratio, v_ratio; 267 268 if (drm_rotation_90_or_270(rotation)) { 269 h_ratio = (src_pos->h << 16) / dst_pos->w; 270 v_ratio = (src_pos->w << 16) / dst_pos->h; 271 } else { 272 h_ratio = (src_pos->w << 16) / dst_pos->w; 273 v_ratio = (src_pos->h << 16) / dst_pos->h; 274 } 275 276 val = SCALER_H_RATIO_SET(h_ratio); 277 scaler_write(val, SCALER_H_RATIO); 278 279 val = SCALER_V_RATIO_SET(v_ratio); 280 scaler_write(val, SCALER_V_RATIO); 281 } 282 283 static inline void scaler_set_rotation(struct scaler_context *scaler, 284 unsigned int rotation) 285 { 286 u32 val = 0; 287 288 if (rotation & DRM_MODE_ROTATE_90) 289 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_90); 290 else if (rotation & DRM_MODE_ROTATE_180) 291 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_180); 292 else if (rotation & DRM_MODE_ROTATE_270) 293 val |= SCALER_ROT_CFG_SET_ROTMODE(SCALER_ROT_MODE_270); 294 if (rotation & DRM_MODE_REFLECT_X) 295 val |= SCALER_ROT_CFG_FLIP_X_EN; 296 if (rotation & DRM_MODE_REFLECT_Y) 297 val |= SCALER_ROT_CFG_FLIP_Y_EN; 298 scaler_write(val, SCALER_ROT_CFG); 299 } 300 301 static inline void scaler_set_csc(struct scaler_context *scaler, 302 const struct drm_format_info *fmt) 303 { 304 static const u32 csc_mtx[2][3][3] = { 305 { /* YCbCr to RGB */ 306 {0x254, 0x000, 0x331}, 307 {0x254, 0xf38, 0xe60}, 308 {0x254, 0x409, 0x000}, 309 }, 310 { /* RGB to YCbCr */ 311 {0x084, 0x102, 0x032}, 312 {0xfb4, 0xf6b, 0x0e1}, 313 {0x0e1, 0xf44, 0xfdc}, 314 }, 315 }; 316 int i, j, dir; 317 318 switch (fmt->format) { 319 case DRM_FORMAT_RGB565: 320 case DRM_FORMAT_XRGB1555: 321 case DRM_FORMAT_ARGB1555: 322 case DRM_FORMAT_XRGB4444: 323 case DRM_FORMAT_ARGB4444: 324 case DRM_FORMAT_XRGB8888: 325 case DRM_FORMAT_ARGB8888: 326 case DRM_FORMAT_RGBX8888: 327 case DRM_FORMAT_RGBA8888: 328 dir = 1; 329 break; 330 default: 331 dir = 0; 332 } 333 334 for (i = 0; i < 3; i++) 335 for (j = 0; j < 3; j++) 336 scaler_write(csc_mtx[dir][i][j], SCALER_CSC_COEF(j, i)); 337 } 338 339 static inline void scaler_set_timer(struct scaler_context *scaler, 340 unsigned int timer, unsigned int divider) 341 { 342 u32 val; 343 344 val = SCALER_TIMEOUT_CTRL_TIMER_ENABLE; 345 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_VALUE(timer); 346 val |= SCALER_TIMEOUT_CTRL_SET_TIMER_DIV(divider); 347 scaler_write(val, SCALER_TIMEOUT_CTRL); 348 } 349 350 static inline void scaler_start_hw(struct scaler_context *scaler) 351 { 352 scaler_write(SCALER_CFG_START_CMD, SCALER_CFG); 353 } 354 355 static int scaler_commit(struct exynos_drm_ipp *ipp, 356 struct exynos_drm_ipp_task *task) 357 { 358 struct scaler_context *scaler = 359 container_of(ipp, struct scaler_context, ipp); 360 361 struct drm_exynos_ipp_task_rect *src_pos = &task->src.rect; 362 struct drm_exynos_ipp_task_rect *dst_pos = &task->dst.rect; 363 const struct scaler_format *src_fmt, *dst_fmt; 364 365 src_fmt = scaler_get_format(task->src.buf.fourcc); 366 dst_fmt = scaler_get_format(task->dst.buf.fourcc); 367 368 pm_runtime_get_sync(scaler->dev); 369 if (scaler_reset(scaler)) { 370 pm_runtime_put(scaler->dev); 371 return -EIO; 372 } 373 374 scaler->task = task; 375 376 scaler_set_src_fmt( 377 scaler, src_fmt->internal_fmt, task->src.buf.modifier != 0); 378 scaler_set_src_base(scaler, &task->src); 379 scaler_set_src_span(scaler, &task->src); 380 scaler_set_src_luma_chroma_pos(scaler, src_pos, src_fmt); 381 scaler_set_src_wh(scaler, src_pos); 382 383 scaler_set_dst_fmt(scaler, dst_fmt->internal_fmt); 384 scaler_set_dst_base(scaler, &task->dst); 385 scaler_set_dst_span(scaler, &task->dst); 386 scaler_set_dst_luma_pos(scaler, dst_pos); 387 scaler_set_dst_wh(scaler, dst_pos); 388 389 scaler_set_hv_ratio(scaler, task->transform.rotation, src_pos, dst_pos); 390 scaler_set_rotation(scaler, task->transform.rotation); 391 392 scaler_set_csc(scaler, task->src.format); 393 394 scaler_set_timer(scaler, 0xffff, 0xf); 395 396 scaler_enable_int(scaler); 397 scaler_start_hw(scaler); 398 399 return 0; 400 } 401 402 static struct exynos_drm_ipp_funcs ipp_funcs = { 403 .commit = scaler_commit, 404 }; 405 406 static inline void scaler_disable_int(struct scaler_context *scaler) 407 { 408 scaler_write(0, SCALER_INT_EN); 409 } 410 411 static inline u32 scaler_get_int_status(struct scaler_context *scaler) 412 { 413 u32 val = scaler_read(SCALER_INT_STATUS); 414 415 scaler_write(val, SCALER_INT_STATUS); 416 417 return val; 418 } 419 420 static inline int scaler_task_done(u32 val) 421 { 422 return val & SCALER_INT_STATUS_FRAME_END ? 0 : -EINVAL; 423 } 424 425 static irqreturn_t scaler_irq_handler(int irq, void *arg) 426 { 427 struct scaler_context *scaler = arg; 428 429 u32 val = scaler_get_int_status(scaler); 430 431 scaler_disable_int(scaler); 432 433 if (scaler->task) { 434 struct exynos_drm_ipp_task *task = scaler->task; 435 436 scaler->task = NULL; 437 pm_runtime_mark_last_busy(scaler->dev); 438 pm_runtime_put_autosuspend(scaler->dev); 439 exynos_drm_ipp_task_done(task, scaler_task_done(val)); 440 } 441 442 return IRQ_HANDLED; 443 } 444 445 static int scaler_bind(struct device *dev, struct device *master, void *data) 446 { 447 struct scaler_context *scaler = dev_get_drvdata(dev); 448 struct drm_device *drm_dev = data; 449 struct exynos_drm_ipp *ipp = &scaler->ipp; 450 451 scaler->drm_dev = drm_dev; 452 ipp->drm_dev = drm_dev; 453 exynos_drm_register_dma(drm_dev, dev); 454 455 exynos_drm_ipp_register(dev, ipp, &ipp_funcs, 456 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE | 457 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT, 458 scaler->scaler_data->formats, 459 scaler->scaler_data->num_formats, "scaler"); 460 461 dev_info(dev, "The exynos scaler has been probed successfully\n"); 462 463 return 0; 464 } 465 466 static void scaler_unbind(struct device *dev, struct device *master, 467 void *data) 468 { 469 struct scaler_context *scaler = dev_get_drvdata(dev); 470 struct exynos_drm_ipp *ipp = &scaler->ipp; 471 472 exynos_drm_ipp_unregister(dev, ipp); 473 exynos_drm_unregister_dma(scaler->drm_dev, scaler->dev); 474 } 475 476 static const struct component_ops scaler_component_ops = { 477 .bind = scaler_bind, 478 .unbind = scaler_unbind, 479 }; 480 481 static int scaler_probe(struct platform_device *pdev) 482 { 483 struct device *dev = &pdev->dev; 484 struct resource *regs_res; 485 struct scaler_context *scaler; 486 int irq; 487 int ret, i; 488 489 scaler = devm_kzalloc(dev, sizeof(*scaler), GFP_KERNEL); 490 if (!scaler) 491 return -ENOMEM; 492 493 scaler->scaler_data = 494 (struct scaler_data *)of_device_get_match_data(dev); 495 496 scaler->dev = dev; 497 regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 498 scaler->regs = devm_ioremap_resource(dev, regs_res); 499 if (IS_ERR(scaler->regs)) 500 return PTR_ERR(scaler->regs); 501 502 irq = platform_get_irq(pdev, 0); 503 if (irq < 0) { 504 dev_err(dev, "failed to get irq\n"); 505 return irq; 506 } 507 508 ret = devm_request_threaded_irq(dev, irq, NULL, scaler_irq_handler, 509 IRQF_ONESHOT, "drm_scaler", scaler); 510 if (ret < 0) { 511 dev_err(dev, "failed to request irq\n"); 512 return ret; 513 } 514 515 for (i = 0; i < scaler->scaler_data->num_clk; ++i) { 516 scaler->clock[i] = devm_clk_get(dev, 517 scaler->scaler_data->clk_name[i]); 518 if (IS_ERR(scaler->clock[i])) { 519 dev_err(dev, "failed to get clock\n"); 520 return PTR_ERR(scaler->clock[i]); 521 } 522 } 523 524 pm_runtime_use_autosuspend(dev); 525 pm_runtime_set_autosuspend_delay(dev, SCALER_AUTOSUSPEND_DELAY); 526 pm_runtime_enable(dev); 527 platform_set_drvdata(pdev, scaler); 528 529 ret = component_add(dev, &scaler_component_ops); 530 if (ret) 531 goto err_ippdrv_register; 532 533 return 0; 534 535 err_ippdrv_register: 536 pm_runtime_dont_use_autosuspend(dev); 537 pm_runtime_disable(dev); 538 return ret; 539 } 540 541 static int scaler_remove(struct platform_device *pdev) 542 { 543 struct device *dev = &pdev->dev; 544 545 component_del(dev, &scaler_component_ops); 546 pm_runtime_dont_use_autosuspend(dev); 547 pm_runtime_disable(dev); 548 549 return 0; 550 } 551 552 #ifdef CONFIG_PM 553 554 static int clk_disable_unprepare_wrapper(struct clk *clk) 555 { 556 clk_disable_unprepare(clk); 557 558 return 0; 559 } 560 561 static int scaler_clk_ctrl(struct scaler_context *scaler, bool enable) 562 { 563 int (*clk_fun)(struct clk *clk), i; 564 565 clk_fun = enable ? clk_prepare_enable : clk_disable_unprepare_wrapper; 566 567 for (i = 0; i < scaler->scaler_data->num_clk; ++i) 568 clk_fun(scaler->clock[i]); 569 570 return 0; 571 } 572 573 static int scaler_runtime_suspend(struct device *dev) 574 { 575 struct scaler_context *scaler = dev_get_drvdata(dev); 576 577 return scaler_clk_ctrl(scaler, false); 578 } 579 580 static int scaler_runtime_resume(struct device *dev) 581 { 582 struct scaler_context *scaler = dev_get_drvdata(dev); 583 584 return scaler_clk_ctrl(scaler, true); 585 } 586 #endif 587 588 static const struct dev_pm_ops scaler_pm_ops = { 589 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 590 pm_runtime_force_resume) 591 SET_RUNTIME_PM_OPS(scaler_runtime_suspend, scaler_runtime_resume, NULL) 592 }; 593 594 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_hv_limits[] = { 595 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 596 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) }, 597 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 598 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 599 }; 600 601 static const struct drm_exynos_ipp_limit scaler_5420_two_pixel_h_limits[] = { 602 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 603 { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 1) }, 604 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 605 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 606 }; 607 608 static const struct drm_exynos_ipp_limit scaler_5420_one_pixel_limits[] = { 609 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K }) }, 610 { IPP_SCALE_LIMIT(.h = { 65536 * 1 / 4, 65536 * 16 }, 611 .v = { 65536 * 1 / 4, 65536 * 16 }) }, 612 }; 613 614 static const struct drm_exynos_ipp_limit scaler_5420_tile_limits[] = { 615 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, SZ_8K }, .v = { 16, SZ_8K })}, 616 { IPP_SIZE_LIMIT(AREA, .h.align = 16, .v.align = 16) }, 617 { IPP_SCALE_LIMIT(.h = {1, 1}, .v = {1, 1})}, 618 { } 619 }; 620 621 #define IPP_SRCDST_TILE_FORMAT(f, l) \ 622 IPP_SRCDST_MFORMAT(f, DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, (l)) 623 624 static const struct exynos_drm_ipp_formats exynos5420_formats[] = { 625 /* SCALER_YUV420_2P_UV */ 626 { IPP_SRCDST_FORMAT(NV21, scaler_5420_two_pixel_hv_limits) }, 627 628 /* SCALER_YUV420_2P_VU */ 629 { IPP_SRCDST_FORMAT(NV12, scaler_5420_two_pixel_hv_limits) }, 630 631 /* SCALER_YUV420_3P */ 632 { IPP_SRCDST_FORMAT(YUV420, scaler_5420_two_pixel_hv_limits) }, 633 634 /* SCALER_YUV422_1P_YUYV */ 635 { IPP_SRCDST_FORMAT(YUYV, scaler_5420_two_pixel_h_limits) }, 636 637 /* SCALER_YUV422_1P_UYVY */ 638 { IPP_SRCDST_FORMAT(UYVY, scaler_5420_two_pixel_h_limits) }, 639 640 /* SCALER_YUV422_1P_YVYU */ 641 { IPP_SRCDST_FORMAT(YVYU, scaler_5420_two_pixel_h_limits) }, 642 643 /* SCALER_YUV422_2P_UV */ 644 { IPP_SRCDST_FORMAT(NV61, scaler_5420_two_pixel_h_limits) }, 645 646 /* SCALER_YUV422_2P_VU */ 647 { IPP_SRCDST_FORMAT(NV16, scaler_5420_two_pixel_h_limits) }, 648 649 /* SCALER_YUV422_3P */ 650 { IPP_SRCDST_FORMAT(YUV422, scaler_5420_two_pixel_h_limits) }, 651 652 /* SCALER_YUV444_2P_UV */ 653 { IPP_SRCDST_FORMAT(NV42, scaler_5420_one_pixel_limits) }, 654 655 /* SCALER_YUV444_2P_VU */ 656 { IPP_SRCDST_FORMAT(NV24, scaler_5420_one_pixel_limits) }, 657 658 /* SCALER_YUV444_3P */ 659 { IPP_SRCDST_FORMAT(YUV444, scaler_5420_one_pixel_limits) }, 660 661 /* SCALER_RGB_565 */ 662 { IPP_SRCDST_FORMAT(RGB565, scaler_5420_one_pixel_limits) }, 663 664 /* SCALER_ARGB1555 */ 665 { IPP_SRCDST_FORMAT(XRGB1555, scaler_5420_one_pixel_limits) }, 666 667 /* SCALER_ARGB1555 */ 668 { IPP_SRCDST_FORMAT(ARGB1555, scaler_5420_one_pixel_limits) }, 669 670 /* SCALER_ARGB4444 */ 671 { IPP_SRCDST_FORMAT(XRGB4444, scaler_5420_one_pixel_limits) }, 672 673 /* SCALER_ARGB4444 */ 674 { IPP_SRCDST_FORMAT(ARGB4444, scaler_5420_one_pixel_limits) }, 675 676 /* SCALER_ARGB8888 */ 677 { IPP_SRCDST_FORMAT(XRGB8888, scaler_5420_one_pixel_limits) }, 678 679 /* SCALER_ARGB8888 */ 680 { IPP_SRCDST_FORMAT(ARGB8888, scaler_5420_one_pixel_limits) }, 681 682 /* SCALER_RGBA8888 */ 683 { IPP_SRCDST_FORMAT(RGBX8888, scaler_5420_one_pixel_limits) }, 684 685 /* SCALER_RGBA8888 */ 686 { IPP_SRCDST_FORMAT(RGBA8888, scaler_5420_one_pixel_limits) }, 687 688 /* SCALER_YUV420_2P_UV TILE */ 689 { IPP_SRCDST_TILE_FORMAT(NV21, scaler_5420_tile_limits) }, 690 691 /* SCALER_YUV420_2P_VU TILE */ 692 { IPP_SRCDST_TILE_FORMAT(NV12, scaler_5420_tile_limits) }, 693 694 /* SCALER_YUV420_3P TILE */ 695 { IPP_SRCDST_TILE_FORMAT(YUV420, scaler_5420_tile_limits) }, 696 697 /* SCALER_YUV422_1P_YUYV TILE */ 698 { IPP_SRCDST_TILE_FORMAT(YUYV, scaler_5420_tile_limits) }, 699 }; 700 701 static const struct scaler_data exynos5420_data = { 702 .clk_name = {"mscl"}, 703 .num_clk = 1, 704 .formats = exynos5420_formats, 705 .num_formats = ARRAY_SIZE(exynos5420_formats), 706 }; 707 708 static const struct scaler_data exynos5433_data = { 709 .clk_name = {"pclk", "aclk", "aclk_xiu"}, 710 .num_clk = 3, 711 .formats = exynos5420_formats, /* intentional */ 712 .num_formats = ARRAY_SIZE(exynos5420_formats), 713 }; 714 715 static const struct of_device_id exynos_scaler_match[] = { 716 { 717 .compatible = "samsung,exynos5420-scaler", 718 .data = &exynos5420_data, 719 }, { 720 .compatible = "samsung,exynos5433-scaler", 721 .data = &exynos5433_data, 722 }, { 723 }, 724 }; 725 MODULE_DEVICE_TABLE(of, exynos_scaler_match); 726 727 struct platform_driver scaler_driver = { 728 .probe = scaler_probe, 729 .remove = scaler_remove, 730 .driver = { 731 .name = "exynos-scaler", 732 .owner = THIS_MODULE, 733 .pm = &scaler_pm_ops, 734 .of_match_table = exynos_scaler_match, 735 }, 736 }; 737