1 /*
2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
3  * Authors:
4  *	YoungJun Cho <yj44.cho@samsung.com>
5  *	Eunchul Kim <chulspro.kim@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundationr
10  */
11 
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/pm_runtime.h>
19 
20 #include <drm/drmP.h>
21 #include <drm/exynos_drm.h>
22 #include "regs-rotator.h"
23 #include "exynos_drm.h"
24 #include "exynos_drm_ipp.h"
25 
26 /*
27  * Rotator supports image crop/rotator and input/output DMA operations.
28  * input DMA reads image data from the memory.
29  * output DMA writes image data to memory.
30  *
31  * M2M operation : supports crop/scale/rotation/csc so on.
32  * Memory ----> Rotator H/W ----> Memory.
33  */
34 
35 /*
36  * TODO
37  * 1. check suspend/resume api if needed.
38  * 2. need to check use case platform_device_id.
39  * 3. check src/dst size with, height.
40  * 4. need to add supported list in prop_list.
41  */
42 
43 #define get_rot_context(dev)	platform_get_drvdata(to_platform_device(dev))
44 #define get_ctx_from_ippdrv(ippdrv)	container_of(ippdrv,\
45 					struct rot_context, ippdrv);
46 #define rot_read(offset)		readl(rot->regs + (offset))
47 #define rot_write(cfg, offset)	writel(cfg, rot->regs + (offset))
48 
49 enum rot_irq_status {
50 	ROT_IRQ_STATUS_COMPLETE	= 8,
51 	ROT_IRQ_STATUS_ILLEGAL	= 9,
52 };
53 
54 /*
55  * A structure of limitation.
56  *
57  * @min_w: minimum width.
58  * @min_h: minimum height.
59  * @max_w: maximum width.
60  * @max_h: maximum height.
61  * @align: align size.
62  */
63 struct rot_limit {
64 	u32	min_w;
65 	u32	min_h;
66 	u32	max_w;
67 	u32	max_h;
68 	u32	align;
69 };
70 
71 /*
72  * A structure of limitation table.
73  *
74  * @ycbcr420_2p: case of YUV.
75  * @rgb888: case of RGB.
76  */
77 struct rot_limit_table {
78 	struct rot_limit	ycbcr420_2p;
79 	struct rot_limit	rgb888;
80 };
81 
82 /*
83  * A structure of rotator context.
84  * @ippdrv: prepare initialization using ippdrv.
85  * @regs_res: register resources.
86  * @regs: memory mapped io registers.
87  * @clock: rotator gate clock.
88  * @limit_tbl: limitation of rotator.
89  * @irq: irq number.
90  * @cur_buf_id: current operation buffer id.
91  * @suspended: suspended state.
92  */
93 struct rot_context {
94 	struct exynos_drm_ippdrv	ippdrv;
95 	struct resource	*regs_res;
96 	void __iomem	*regs;
97 	struct clk	*clock;
98 	struct rot_limit_table	*limit_tbl;
99 	int	irq;
100 	int	cur_buf_id[EXYNOS_DRM_OPS_MAX];
101 	bool	suspended;
102 };
103 
104 static void rotator_reg_set_irq(struct rot_context *rot, bool enable)
105 {
106 	u32 val = rot_read(ROT_CONFIG);
107 
108 	if (enable == true)
109 		val |= ROT_CONFIG_IRQ;
110 	else
111 		val &= ~ROT_CONFIG_IRQ;
112 
113 	rot_write(val, ROT_CONFIG);
114 }
115 
116 static u32 rotator_reg_get_fmt(struct rot_context *rot)
117 {
118 	u32 val = rot_read(ROT_CONTROL);
119 
120 	val &= ROT_CONTROL_FMT_MASK;
121 
122 	return val;
123 }
124 
125 static enum rot_irq_status rotator_reg_get_irq_status(struct rot_context *rot)
126 {
127 	u32 val = rot_read(ROT_STATUS);
128 
129 	val = ROT_STATUS_IRQ(val);
130 
131 	if (val == ROT_STATUS_IRQ_VAL_COMPLETE)
132 		return ROT_IRQ_STATUS_COMPLETE;
133 
134 	return ROT_IRQ_STATUS_ILLEGAL;
135 }
136 
137 static irqreturn_t rotator_irq_handler(int irq, void *arg)
138 {
139 	struct rot_context *rot = arg;
140 	struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
141 	struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
142 	struct drm_exynos_ipp_event_work *event_work = c_node->event_work;
143 	enum rot_irq_status irq_status;
144 	u32 val;
145 
146 	/* Get execution result */
147 	irq_status = rotator_reg_get_irq_status(rot);
148 
149 	/* clear status */
150 	val = rot_read(ROT_STATUS);
151 	val |= ROT_STATUS_IRQ_PENDING((u32)irq_status);
152 	rot_write(val, ROT_STATUS);
153 
154 	if (irq_status == ROT_IRQ_STATUS_COMPLETE) {
155 		event_work->ippdrv = ippdrv;
156 		event_work->buf_id[EXYNOS_DRM_OPS_DST] =
157 			rot->cur_buf_id[EXYNOS_DRM_OPS_DST];
158 		queue_work(ippdrv->event_workq,
159 			(struct work_struct *)event_work);
160 	} else
161 		DRM_ERROR("the SFR is set illegally\n");
162 
163 	return IRQ_HANDLED;
164 }
165 
166 static void rotator_align_size(struct rot_context *rot, u32 fmt, u32 *hsize,
167 		u32 *vsize)
168 {
169 	struct rot_limit_table *limit_tbl = rot->limit_tbl;
170 	struct rot_limit *limit;
171 	u32 mask, val;
172 
173 	/* Get size limit */
174 	if (fmt == ROT_CONTROL_FMT_RGB888)
175 		limit = &limit_tbl->rgb888;
176 	else
177 		limit = &limit_tbl->ycbcr420_2p;
178 
179 	/* Get mask for rounding to nearest aligned val */
180 	mask = ~((1 << limit->align) - 1);
181 
182 	/* Set aligned width */
183 	val = ROT_ALIGN(*hsize, limit->align, mask);
184 	if (val < limit->min_w)
185 		*hsize = ROT_MIN(limit->min_w, mask);
186 	else if (val > limit->max_w)
187 		*hsize = ROT_MAX(limit->max_w, mask);
188 	else
189 		*hsize = val;
190 
191 	/* Set aligned height */
192 	val = ROT_ALIGN(*vsize, limit->align, mask);
193 	if (val < limit->min_h)
194 		*vsize = ROT_MIN(limit->min_h, mask);
195 	else if (val > limit->max_h)
196 		*vsize = ROT_MAX(limit->max_h, mask);
197 	else
198 		*vsize = val;
199 }
200 
201 static int rotator_src_set_fmt(struct device *dev, u32 fmt)
202 {
203 	struct rot_context *rot = dev_get_drvdata(dev);
204 	u32 val;
205 
206 	val = rot_read(ROT_CONTROL);
207 	val &= ~ROT_CONTROL_FMT_MASK;
208 
209 	switch (fmt) {
210 	case DRM_FORMAT_NV12:
211 		val |= ROT_CONTROL_FMT_YCBCR420_2P;
212 		break;
213 	case DRM_FORMAT_XRGB8888:
214 		val |= ROT_CONTROL_FMT_RGB888;
215 		break;
216 	default:
217 		DRM_ERROR("invalid image format\n");
218 		return -EINVAL;
219 	}
220 
221 	rot_write(val, ROT_CONTROL);
222 
223 	return 0;
224 }
225 
226 static inline bool rotator_check_reg_fmt(u32 fmt)
227 {
228 	if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) ||
229 	    (fmt == ROT_CONTROL_FMT_RGB888))
230 		return true;
231 
232 	return false;
233 }
234 
235 static int rotator_src_set_size(struct device *dev, int swap,
236 		struct drm_exynos_pos *pos,
237 		struct drm_exynos_sz *sz)
238 {
239 	struct rot_context *rot = dev_get_drvdata(dev);
240 	u32 fmt, hsize, vsize;
241 	u32 val;
242 
243 	/* Get format */
244 	fmt = rotator_reg_get_fmt(rot);
245 	if (!rotator_check_reg_fmt(fmt)) {
246 		DRM_ERROR("invalid format.\n");
247 		return -EINVAL;
248 	}
249 
250 	/* Align buffer size */
251 	hsize = sz->hsize;
252 	vsize = sz->vsize;
253 	rotator_align_size(rot, fmt, &hsize, &vsize);
254 
255 	/* Set buffer size configuration */
256 	val = ROT_SET_BUF_SIZE_H(vsize) | ROT_SET_BUF_SIZE_W(hsize);
257 	rot_write(val, ROT_SRC_BUF_SIZE);
258 
259 	/* Set crop image position configuration */
260 	val = ROT_CROP_POS_Y(pos->y) | ROT_CROP_POS_X(pos->x);
261 	rot_write(val, ROT_SRC_CROP_POS);
262 	val = ROT_SRC_CROP_SIZE_H(pos->h) | ROT_SRC_CROP_SIZE_W(pos->w);
263 	rot_write(val, ROT_SRC_CROP_SIZE);
264 
265 	return 0;
266 }
267 
268 static int rotator_src_set_addr(struct device *dev,
269 		struct drm_exynos_ipp_buf_info *buf_info,
270 		u32 buf_id, enum drm_exynos_ipp_buf_type buf_type)
271 {
272 	struct rot_context *rot = dev_get_drvdata(dev);
273 	dma_addr_t addr[EXYNOS_DRM_PLANAR_MAX];
274 	u32 val, fmt, hsize, vsize;
275 	int i;
276 
277 	/* Set current buf_id */
278 	rot->cur_buf_id[EXYNOS_DRM_OPS_SRC] = buf_id;
279 
280 	switch (buf_type) {
281 	case IPP_BUF_ENQUEUE:
282 		/* Set address configuration */
283 		for_each_ipp_planar(i)
284 			addr[i] = buf_info->base[i];
285 
286 		/* Get format */
287 		fmt = rotator_reg_get_fmt(rot);
288 		if (!rotator_check_reg_fmt(fmt)) {
289 			DRM_ERROR("invalid format.\n");
290 			return -EINVAL;
291 		}
292 
293 		/* Re-set cb planar for NV12 format */
294 		if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) &&
295 		    !addr[EXYNOS_DRM_PLANAR_CB]) {
296 
297 			val = rot_read(ROT_SRC_BUF_SIZE);
298 			hsize = ROT_GET_BUF_SIZE_W(val);
299 			vsize = ROT_GET_BUF_SIZE_H(val);
300 
301 			/* Set cb planar */
302 			addr[EXYNOS_DRM_PLANAR_CB] =
303 				addr[EXYNOS_DRM_PLANAR_Y] + hsize * vsize;
304 		}
305 
306 		for_each_ipp_planar(i)
307 			rot_write(addr[i], ROT_SRC_BUF_ADDR(i));
308 		break;
309 	case IPP_BUF_DEQUEUE:
310 		for_each_ipp_planar(i)
311 			rot_write(0x0, ROT_SRC_BUF_ADDR(i));
312 		break;
313 	default:
314 		/* Nothing to do */
315 		break;
316 	}
317 
318 	return 0;
319 }
320 
321 static int rotator_dst_set_transf(struct device *dev,
322 		enum drm_exynos_degree degree,
323 		enum drm_exynos_flip flip, bool *swap)
324 {
325 	struct rot_context *rot = dev_get_drvdata(dev);
326 	u32 val;
327 
328 	/* Set transform configuration */
329 	val = rot_read(ROT_CONTROL);
330 	val &= ~ROT_CONTROL_FLIP_MASK;
331 
332 	switch (flip) {
333 	case EXYNOS_DRM_FLIP_VERTICAL:
334 		val |= ROT_CONTROL_FLIP_VERTICAL;
335 		break;
336 	case EXYNOS_DRM_FLIP_HORIZONTAL:
337 		val |= ROT_CONTROL_FLIP_HORIZONTAL;
338 		break;
339 	default:
340 		/* Flip None */
341 		break;
342 	}
343 
344 	val &= ~ROT_CONTROL_ROT_MASK;
345 
346 	switch (degree) {
347 	case EXYNOS_DRM_DEGREE_90:
348 		val |= ROT_CONTROL_ROT_90;
349 		break;
350 	case EXYNOS_DRM_DEGREE_180:
351 		val |= ROT_CONTROL_ROT_180;
352 		break;
353 	case EXYNOS_DRM_DEGREE_270:
354 		val |= ROT_CONTROL_ROT_270;
355 		break;
356 	default:
357 		/* Rotation 0 Degree */
358 		break;
359 	}
360 
361 	rot_write(val, ROT_CONTROL);
362 
363 	/* Check degree for setting buffer size swap */
364 	if ((degree == EXYNOS_DRM_DEGREE_90) ||
365 	    (degree == EXYNOS_DRM_DEGREE_270))
366 		*swap = true;
367 	else
368 		*swap = false;
369 
370 	return 0;
371 }
372 
373 static int rotator_dst_set_size(struct device *dev, int swap,
374 		struct drm_exynos_pos *pos,
375 		struct drm_exynos_sz *sz)
376 {
377 	struct rot_context *rot = dev_get_drvdata(dev);
378 	u32 val, fmt, hsize, vsize;
379 
380 	/* Get format */
381 	fmt = rotator_reg_get_fmt(rot);
382 	if (!rotator_check_reg_fmt(fmt)) {
383 		DRM_ERROR("invalid format.\n");
384 		return -EINVAL;
385 	}
386 
387 	/* Align buffer size */
388 	hsize = sz->hsize;
389 	vsize = sz->vsize;
390 	rotator_align_size(rot, fmt, &hsize, &vsize);
391 
392 	/* Set buffer size configuration */
393 	val = ROT_SET_BUF_SIZE_H(vsize) | ROT_SET_BUF_SIZE_W(hsize);
394 	rot_write(val, ROT_DST_BUF_SIZE);
395 
396 	/* Set crop image position configuration */
397 	val = ROT_CROP_POS_Y(pos->y) | ROT_CROP_POS_X(pos->x);
398 	rot_write(val, ROT_DST_CROP_POS);
399 
400 	return 0;
401 }
402 
403 static int rotator_dst_set_addr(struct device *dev,
404 		struct drm_exynos_ipp_buf_info *buf_info,
405 		u32 buf_id, enum drm_exynos_ipp_buf_type buf_type)
406 {
407 	struct rot_context *rot = dev_get_drvdata(dev);
408 	dma_addr_t addr[EXYNOS_DRM_PLANAR_MAX];
409 	u32 val, fmt, hsize, vsize;
410 	int i;
411 
412 	/* Set current buf_id */
413 	rot->cur_buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
414 
415 	switch (buf_type) {
416 	case IPP_BUF_ENQUEUE:
417 		/* Set address configuration */
418 		for_each_ipp_planar(i)
419 			addr[i] = buf_info->base[i];
420 
421 		/* Get format */
422 		fmt = rotator_reg_get_fmt(rot);
423 		if (!rotator_check_reg_fmt(fmt)) {
424 			DRM_ERROR("invalid format.\n");
425 			return -EINVAL;
426 		}
427 
428 		/* Re-set cb planar for NV12 format */
429 		if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) &&
430 		    !addr[EXYNOS_DRM_PLANAR_CB]) {
431 			/* Get buf size */
432 			val = rot_read(ROT_DST_BUF_SIZE);
433 
434 			hsize = ROT_GET_BUF_SIZE_W(val);
435 			vsize = ROT_GET_BUF_SIZE_H(val);
436 
437 			/* Set cb planar */
438 			addr[EXYNOS_DRM_PLANAR_CB] =
439 				addr[EXYNOS_DRM_PLANAR_Y] + hsize * vsize;
440 		}
441 
442 		for_each_ipp_planar(i)
443 			rot_write(addr[i], ROT_DST_BUF_ADDR(i));
444 		break;
445 	case IPP_BUF_DEQUEUE:
446 		for_each_ipp_planar(i)
447 			rot_write(0x0, ROT_DST_BUF_ADDR(i));
448 		break;
449 	default:
450 		/* Nothing to do */
451 		break;
452 	}
453 
454 	return 0;
455 }
456 
457 static struct exynos_drm_ipp_ops rot_src_ops = {
458 	.set_fmt	=	rotator_src_set_fmt,
459 	.set_size	=	rotator_src_set_size,
460 	.set_addr	=	rotator_src_set_addr,
461 };
462 
463 static struct exynos_drm_ipp_ops rot_dst_ops = {
464 	.set_transf	=	rotator_dst_set_transf,
465 	.set_size	=	rotator_dst_set_size,
466 	.set_addr	=	rotator_dst_set_addr,
467 };
468 
469 static int rotator_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
470 {
471 	struct drm_exynos_ipp_prop_list *prop_list;
472 
473 	prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL);
474 	if (!prop_list) {
475 		DRM_ERROR("failed to alloc property list.\n");
476 		return -ENOMEM;
477 	}
478 
479 	prop_list->version = 1;
480 	prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
481 				(1 << EXYNOS_DRM_FLIP_HORIZONTAL);
482 	prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
483 				(1 << EXYNOS_DRM_DEGREE_90) |
484 				(1 << EXYNOS_DRM_DEGREE_180) |
485 				(1 << EXYNOS_DRM_DEGREE_270);
486 	prop_list->csc = 0;
487 	prop_list->crop = 0;
488 	prop_list->scale = 0;
489 
490 	ippdrv->prop_list = prop_list;
491 
492 	return 0;
493 }
494 
495 static inline bool rotator_check_drm_fmt(u32 fmt)
496 {
497 	switch (fmt) {
498 	case DRM_FORMAT_XRGB8888:
499 	case DRM_FORMAT_NV12:
500 		return true;
501 	default:
502 		DRM_DEBUG_KMS("not support format\n");
503 		return false;
504 	}
505 }
506 
507 static inline bool rotator_check_drm_flip(enum drm_exynos_flip flip)
508 {
509 	switch (flip) {
510 	case EXYNOS_DRM_FLIP_NONE:
511 	case EXYNOS_DRM_FLIP_VERTICAL:
512 	case EXYNOS_DRM_FLIP_HORIZONTAL:
513 	case EXYNOS_DRM_FLIP_BOTH:
514 		return true;
515 	default:
516 		DRM_DEBUG_KMS("invalid flip\n");
517 		return false;
518 	}
519 }
520 
521 static int rotator_ippdrv_check_property(struct device *dev,
522 		struct drm_exynos_ipp_property *property)
523 {
524 	struct drm_exynos_ipp_config *src_config =
525 					&property->config[EXYNOS_DRM_OPS_SRC];
526 	struct drm_exynos_ipp_config *dst_config =
527 					&property->config[EXYNOS_DRM_OPS_DST];
528 	struct drm_exynos_pos *src_pos = &src_config->pos;
529 	struct drm_exynos_pos *dst_pos = &dst_config->pos;
530 	struct drm_exynos_sz *src_sz = &src_config->sz;
531 	struct drm_exynos_sz *dst_sz = &dst_config->sz;
532 	bool swap = false;
533 
534 	/* Check format configuration */
535 	if (src_config->fmt != dst_config->fmt) {
536 		DRM_DEBUG_KMS("not support csc feature\n");
537 		return -EINVAL;
538 	}
539 
540 	if (!rotator_check_drm_fmt(dst_config->fmt)) {
541 		DRM_DEBUG_KMS("invalid format\n");
542 		return -EINVAL;
543 	}
544 
545 	/* Check transform configuration */
546 	if (src_config->degree != EXYNOS_DRM_DEGREE_0) {
547 		DRM_DEBUG_KMS("not support source-side rotation\n");
548 		return -EINVAL;
549 	}
550 
551 	switch (dst_config->degree) {
552 	case EXYNOS_DRM_DEGREE_90:
553 	case EXYNOS_DRM_DEGREE_270:
554 		swap = true;
555 	case EXYNOS_DRM_DEGREE_0:
556 	case EXYNOS_DRM_DEGREE_180:
557 		/* No problem */
558 		break;
559 	default:
560 		DRM_DEBUG_KMS("invalid degree\n");
561 		return -EINVAL;
562 	}
563 
564 	if (src_config->flip != EXYNOS_DRM_FLIP_NONE) {
565 		DRM_DEBUG_KMS("not support source-side flip\n");
566 		return -EINVAL;
567 	}
568 
569 	if (!rotator_check_drm_flip(dst_config->flip)) {
570 		DRM_DEBUG_KMS("invalid flip\n");
571 		return -EINVAL;
572 	}
573 
574 	/* Check size configuration */
575 	if ((src_pos->x + src_pos->w > src_sz->hsize) ||
576 		(src_pos->y + src_pos->h > src_sz->vsize)) {
577 		DRM_DEBUG_KMS("out of source buffer bound\n");
578 		return -EINVAL;
579 	}
580 
581 	if (swap) {
582 		if ((dst_pos->x + dst_pos->h > dst_sz->vsize) ||
583 			(dst_pos->y + dst_pos->w > dst_sz->hsize)) {
584 			DRM_DEBUG_KMS("out of destination buffer bound\n");
585 			return -EINVAL;
586 		}
587 
588 		if ((src_pos->w != dst_pos->h) || (src_pos->h != dst_pos->w)) {
589 			DRM_DEBUG_KMS("not support scale feature\n");
590 			return -EINVAL;
591 		}
592 	} else {
593 		if ((dst_pos->x + dst_pos->w > dst_sz->hsize) ||
594 			(dst_pos->y + dst_pos->h > dst_sz->vsize)) {
595 			DRM_DEBUG_KMS("out of destination buffer bound\n");
596 			return -EINVAL;
597 		}
598 
599 		if ((src_pos->w != dst_pos->w) || (src_pos->h != dst_pos->h)) {
600 			DRM_DEBUG_KMS("not support scale feature\n");
601 			return -EINVAL;
602 		}
603 	}
604 
605 	return 0;
606 }
607 
608 static int rotator_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
609 {
610 	struct rot_context *rot = dev_get_drvdata(dev);
611 	u32 val;
612 
613 	if (rot->suspended) {
614 		DRM_ERROR("suspended state\n");
615 		return -EPERM;
616 	}
617 
618 	if (cmd != IPP_CMD_M2M) {
619 		DRM_ERROR("not support cmd: %d\n", cmd);
620 		return -EINVAL;
621 	}
622 
623 	/* Set interrupt enable */
624 	rotator_reg_set_irq(rot, true);
625 
626 	val = rot_read(ROT_CONTROL);
627 	val |= ROT_CONTROL_START;
628 
629 	rot_write(val, ROT_CONTROL);
630 
631 	return 0;
632 }
633 
634 static int rotator_probe(struct platform_device *pdev)
635 {
636 	struct device *dev = &pdev->dev;
637 	struct rot_context *rot;
638 	struct exynos_drm_ippdrv *ippdrv;
639 	int ret;
640 
641 	rot = devm_kzalloc(dev, sizeof(*rot), GFP_KERNEL);
642 	if (!rot) {
643 		dev_err(dev, "failed to allocate rot\n");
644 		return -ENOMEM;
645 	}
646 
647 	rot->limit_tbl = (struct rot_limit_table *)
648 				platform_get_device_id(pdev)->driver_data;
649 
650 	rot->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
651 	rot->regs = devm_ioremap_resource(dev, rot->regs_res);
652 	if (IS_ERR(rot->regs))
653 		return PTR_ERR(rot->regs);
654 
655 	rot->irq = platform_get_irq(pdev, 0);
656 	if (rot->irq < 0) {
657 		dev_err(dev, "failed to get irq\n");
658 		return rot->irq;
659 	}
660 
661 	ret = devm_request_threaded_irq(dev, rot->irq, NULL,
662 			rotator_irq_handler, IRQF_ONESHOT, "drm_rotator", rot);
663 	if (ret < 0) {
664 		dev_err(dev, "failed to request irq\n");
665 		return ret;
666 	}
667 
668 	rot->clock = devm_clk_get(dev, "rotator");
669 	if (IS_ERR(rot->clock)) {
670 		dev_err(dev, "failed to get clock\n");
671 		return PTR_ERR(rot->clock);
672 	}
673 
674 	pm_runtime_enable(dev);
675 
676 	ippdrv = &rot->ippdrv;
677 	ippdrv->dev = dev;
678 	ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &rot_src_ops;
679 	ippdrv->ops[EXYNOS_DRM_OPS_DST] = &rot_dst_ops;
680 	ippdrv->check_property = rotator_ippdrv_check_property;
681 	ippdrv->start = rotator_ippdrv_start;
682 	ret = rotator_init_prop_list(ippdrv);
683 	if (ret < 0) {
684 		dev_err(dev, "failed to init property list.\n");
685 		goto err_ippdrv_register;
686 	}
687 
688 	DRM_DEBUG_KMS("ippdrv[0x%x]\n", (int)ippdrv);
689 
690 	platform_set_drvdata(pdev, rot);
691 
692 	ret = exynos_drm_ippdrv_register(ippdrv);
693 	if (ret < 0) {
694 		dev_err(dev, "failed to register drm rotator device\n");
695 		goto err_ippdrv_register;
696 	}
697 
698 	dev_info(dev, "The exynos rotator is probed successfully\n");
699 
700 	return 0;
701 
702 err_ippdrv_register:
703 	pm_runtime_disable(dev);
704 	return ret;
705 }
706 
707 static int rotator_remove(struct platform_device *pdev)
708 {
709 	struct device *dev = &pdev->dev;
710 	struct rot_context *rot = dev_get_drvdata(dev);
711 	struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
712 
713 	exynos_drm_ippdrv_unregister(ippdrv);
714 
715 	pm_runtime_disable(dev);
716 
717 	return 0;
718 }
719 
720 static struct rot_limit_table rot_limit_tbl = {
721 	.ycbcr420_2p = {
722 		.min_w = 32,
723 		.min_h = 32,
724 		.max_w = SZ_32K,
725 		.max_h = SZ_32K,
726 		.align = 3,
727 	},
728 	.rgb888 = {
729 		.min_w = 8,
730 		.min_h = 8,
731 		.max_w = SZ_8K,
732 		.max_h = SZ_8K,
733 		.align = 2,
734 	},
735 };
736 
737 static struct platform_device_id rotator_driver_ids[] = {
738 	{
739 		.name		= "exynos-rot",
740 		.driver_data	= (unsigned long)&rot_limit_tbl,
741 	},
742 	{},
743 };
744 
745 static int rotator_clk_crtl(struct rot_context *rot, bool enable)
746 {
747 	if (enable) {
748 		clk_enable(rot->clock);
749 		rot->suspended = false;
750 	} else {
751 		clk_disable(rot->clock);
752 		rot->suspended = true;
753 	}
754 
755 	return 0;
756 }
757 
758 
759 #ifdef CONFIG_PM_SLEEP
760 static int rotator_suspend(struct device *dev)
761 {
762 	struct rot_context *rot = dev_get_drvdata(dev);
763 
764 	if (pm_runtime_suspended(dev))
765 		return 0;
766 
767 	return rotator_clk_crtl(rot, false);
768 }
769 
770 static int rotator_resume(struct device *dev)
771 {
772 	struct rot_context *rot = dev_get_drvdata(dev);
773 
774 	if (!pm_runtime_suspended(dev))
775 		return rotator_clk_crtl(rot, true);
776 
777 	return 0;
778 }
779 #endif
780 
781 #ifdef CONFIG_PM_RUNTIME
782 static int rotator_runtime_suspend(struct device *dev)
783 {
784 	struct rot_context *rot = dev_get_drvdata(dev);
785 
786 	return  rotator_clk_crtl(rot, false);
787 }
788 
789 static int rotator_runtime_resume(struct device *dev)
790 {
791 	struct rot_context *rot = dev_get_drvdata(dev);
792 
793 	return  rotator_clk_crtl(rot, true);
794 }
795 #endif
796 
797 static const struct dev_pm_ops rotator_pm_ops = {
798 	SET_SYSTEM_SLEEP_PM_OPS(rotator_suspend, rotator_resume)
799 	SET_RUNTIME_PM_OPS(rotator_runtime_suspend, rotator_runtime_resume,
800 									NULL)
801 };
802 
803 struct platform_driver rotator_driver = {
804 	.probe		= rotator_probe,
805 	.remove		= rotator_remove,
806 	.id_table	= rotator_driver_ids,
807 	.driver		= {
808 		.name	= "exynos-rot",
809 		.owner	= THIS_MODULE,
810 		.pm	= &rotator_pm_ops,
811 	},
812 };
813