1 /*
2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
3  * Authors:
4  *	YoungJun Cho <yj44.cho@samsung.com>
5  *	Eunchul Kim <chulspro.kim@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundationr
10  */
11 
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/of_device.h>
19 #include <linux/pm_runtime.h>
20 
21 #include <drm/drmP.h>
22 #include <drm/exynos_drm.h>
23 #include "regs-rotator.h"
24 #include "exynos_drm_drv.h"
25 #include "exynos_drm_ipp.h"
26 
27 /*
28  * Rotator supports image crop/rotator and input/output DMA operations.
29  * input DMA reads image data from the memory.
30  * output DMA writes image data to memory.
31  *
32  * M2M operation : supports crop/scale/rotation/csc so on.
33  * Memory ----> Rotator H/W ----> Memory.
34  */
35 
36 /*
37  * TODO
38  * 1. check suspend/resume api if needed.
39  * 2. need to check use case platform_device_id.
40  * 3. check src/dst size with, height.
41  * 4. need to add supported list in prop_list.
42  */
43 
44 #define get_rot_context(dev)	platform_get_drvdata(to_platform_device(dev))
45 #define get_ctx_from_ippdrv(ippdrv)	container_of(ippdrv,\
46 					struct rot_context, ippdrv);
47 #define rot_read(offset)		readl(rot->regs + (offset))
48 #define rot_write(cfg, offset)	writel(cfg, rot->regs + (offset))
49 
50 enum rot_irq_status {
51 	ROT_IRQ_STATUS_COMPLETE	= 8,
52 	ROT_IRQ_STATUS_ILLEGAL	= 9,
53 };
54 
55 /*
56  * A structure of limitation.
57  *
58  * @min_w: minimum width.
59  * @min_h: minimum height.
60  * @max_w: maximum width.
61  * @max_h: maximum height.
62  * @align: align size.
63  */
64 struct rot_limit {
65 	u32	min_w;
66 	u32	min_h;
67 	u32	max_w;
68 	u32	max_h;
69 	u32	align;
70 };
71 
72 /*
73  * A structure of limitation table.
74  *
75  * @ycbcr420_2p: case of YUV.
76  * @rgb888: case of RGB.
77  */
78 struct rot_limit_table {
79 	struct rot_limit	ycbcr420_2p;
80 	struct rot_limit	rgb888;
81 };
82 
83 /*
84  * A structure of rotator context.
85  * @ippdrv: prepare initialization using ippdrv.
86  * @regs_res: register resources.
87  * @regs: memory mapped io registers.
88  * @clock: rotator gate clock.
89  * @limit_tbl: limitation of rotator.
90  * @irq: irq number.
91  * @cur_buf_id: current operation buffer id.
92  * @suspended: suspended state.
93  */
94 struct rot_context {
95 	struct exynos_drm_ippdrv	ippdrv;
96 	struct resource	*regs_res;
97 	void __iomem	*regs;
98 	struct clk	*clock;
99 	struct rot_limit_table	*limit_tbl;
100 	int	irq;
101 	int	cur_buf_id[EXYNOS_DRM_OPS_MAX];
102 	bool	suspended;
103 };
104 
105 static void rotator_reg_set_irq(struct rot_context *rot, bool enable)
106 {
107 	u32 val = rot_read(ROT_CONFIG);
108 
109 	if (enable == true)
110 		val |= ROT_CONFIG_IRQ;
111 	else
112 		val &= ~ROT_CONFIG_IRQ;
113 
114 	rot_write(val, ROT_CONFIG);
115 }
116 
117 static u32 rotator_reg_get_fmt(struct rot_context *rot)
118 {
119 	u32 val = rot_read(ROT_CONTROL);
120 
121 	val &= ROT_CONTROL_FMT_MASK;
122 
123 	return val;
124 }
125 
126 static enum rot_irq_status rotator_reg_get_irq_status(struct rot_context *rot)
127 {
128 	u32 val = rot_read(ROT_STATUS);
129 
130 	val = ROT_STATUS_IRQ(val);
131 
132 	if (val == ROT_STATUS_IRQ_VAL_COMPLETE)
133 		return ROT_IRQ_STATUS_COMPLETE;
134 
135 	return ROT_IRQ_STATUS_ILLEGAL;
136 }
137 
138 static irqreturn_t rotator_irq_handler(int irq, void *arg)
139 {
140 	struct rot_context *rot = arg;
141 	struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
142 	struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
143 	struct drm_exynos_ipp_event_work *event_work = c_node->event_work;
144 	enum rot_irq_status irq_status;
145 	u32 val;
146 
147 	/* Get execution result */
148 	irq_status = rotator_reg_get_irq_status(rot);
149 
150 	/* clear status */
151 	val = rot_read(ROT_STATUS);
152 	val |= ROT_STATUS_IRQ_PENDING((u32)irq_status);
153 	rot_write(val, ROT_STATUS);
154 
155 	if (irq_status == ROT_IRQ_STATUS_COMPLETE) {
156 		event_work->ippdrv = ippdrv;
157 		event_work->buf_id[EXYNOS_DRM_OPS_DST] =
158 			rot->cur_buf_id[EXYNOS_DRM_OPS_DST];
159 		queue_work(ippdrv->event_workq, &event_work->work);
160 	} else {
161 		DRM_ERROR("the SFR is set illegally\n");
162 	}
163 
164 	return IRQ_HANDLED;
165 }
166 
167 static void rotator_align_size(struct rot_context *rot, u32 fmt, u32 *hsize,
168 		u32 *vsize)
169 {
170 	struct rot_limit_table *limit_tbl = rot->limit_tbl;
171 	struct rot_limit *limit;
172 	u32 mask, val;
173 
174 	/* Get size limit */
175 	if (fmt == ROT_CONTROL_FMT_RGB888)
176 		limit = &limit_tbl->rgb888;
177 	else
178 		limit = &limit_tbl->ycbcr420_2p;
179 
180 	/* Get mask for rounding to nearest aligned val */
181 	mask = ~((1 << limit->align) - 1);
182 
183 	/* Set aligned width */
184 	val = ROT_ALIGN(*hsize, limit->align, mask);
185 	if (val < limit->min_w)
186 		*hsize = ROT_MIN(limit->min_w, mask);
187 	else if (val > limit->max_w)
188 		*hsize = ROT_MAX(limit->max_w, mask);
189 	else
190 		*hsize = val;
191 
192 	/* Set aligned height */
193 	val = ROT_ALIGN(*vsize, limit->align, mask);
194 	if (val < limit->min_h)
195 		*vsize = ROT_MIN(limit->min_h, mask);
196 	else if (val > limit->max_h)
197 		*vsize = ROT_MAX(limit->max_h, mask);
198 	else
199 		*vsize = val;
200 }
201 
202 static int rotator_src_set_fmt(struct device *dev, u32 fmt)
203 {
204 	struct rot_context *rot = dev_get_drvdata(dev);
205 	u32 val;
206 
207 	val = rot_read(ROT_CONTROL);
208 	val &= ~ROT_CONTROL_FMT_MASK;
209 
210 	switch (fmt) {
211 	case DRM_FORMAT_NV12:
212 		val |= ROT_CONTROL_FMT_YCBCR420_2P;
213 		break;
214 	case DRM_FORMAT_XRGB8888:
215 		val |= ROT_CONTROL_FMT_RGB888;
216 		break;
217 	default:
218 		DRM_ERROR("invalid image format\n");
219 		return -EINVAL;
220 	}
221 
222 	rot_write(val, ROT_CONTROL);
223 
224 	return 0;
225 }
226 
227 static inline bool rotator_check_reg_fmt(u32 fmt)
228 {
229 	if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) ||
230 	    (fmt == ROT_CONTROL_FMT_RGB888))
231 		return true;
232 
233 	return false;
234 }
235 
236 static int rotator_src_set_size(struct device *dev, int swap,
237 		struct drm_exynos_pos *pos,
238 		struct drm_exynos_sz *sz)
239 {
240 	struct rot_context *rot = dev_get_drvdata(dev);
241 	u32 fmt, hsize, vsize;
242 	u32 val;
243 
244 	/* Get format */
245 	fmt = rotator_reg_get_fmt(rot);
246 	if (!rotator_check_reg_fmt(fmt)) {
247 		DRM_ERROR("invalid format.\n");
248 		return -EINVAL;
249 	}
250 
251 	/* Align buffer size */
252 	hsize = sz->hsize;
253 	vsize = sz->vsize;
254 	rotator_align_size(rot, fmt, &hsize, &vsize);
255 
256 	/* Set buffer size configuration */
257 	val = ROT_SET_BUF_SIZE_H(vsize) | ROT_SET_BUF_SIZE_W(hsize);
258 	rot_write(val, ROT_SRC_BUF_SIZE);
259 
260 	/* Set crop image position configuration */
261 	val = ROT_CROP_POS_Y(pos->y) | ROT_CROP_POS_X(pos->x);
262 	rot_write(val, ROT_SRC_CROP_POS);
263 	val = ROT_SRC_CROP_SIZE_H(pos->h) | ROT_SRC_CROP_SIZE_W(pos->w);
264 	rot_write(val, ROT_SRC_CROP_SIZE);
265 
266 	return 0;
267 }
268 
269 static int rotator_src_set_addr(struct device *dev,
270 		struct drm_exynos_ipp_buf_info *buf_info,
271 		u32 buf_id, enum drm_exynos_ipp_buf_type buf_type)
272 {
273 	struct rot_context *rot = dev_get_drvdata(dev);
274 	dma_addr_t addr[EXYNOS_DRM_PLANAR_MAX];
275 	u32 val, fmt, hsize, vsize;
276 	int i;
277 
278 	/* Set current buf_id */
279 	rot->cur_buf_id[EXYNOS_DRM_OPS_SRC] = buf_id;
280 
281 	switch (buf_type) {
282 	case IPP_BUF_ENQUEUE:
283 		/* Set address configuration */
284 		for_each_ipp_planar(i)
285 			addr[i] = buf_info->base[i];
286 
287 		/* Get format */
288 		fmt = rotator_reg_get_fmt(rot);
289 		if (!rotator_check_reg_fmt(fmt)) {
290 			DRM_ERROR("invalid format.\n");
291 			return -EINVAL;
292 		}
293 
294 		/* Re-set cb planar for NV12 format */
295 		if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) &&
296 		    !addr[EXYNOS_DRM_PLANAR_CB]) {
297 
298 			val = rot_read(ROT_SRC_BUF_SIZE);
299 			hsize = ROT_GET_BUF_SIZE_W(val);
300 			vsize = ROT_GET_BUF_SIZE_H(val);
301 
302 			/* Set cb planar */
303 			addr[EXYNOS_DRM_PLANAR_CB] =
304 				addr[EXYNOS_DRM_PLANAR_Y] + hsize * vsize;
305 		}
306 
307 		for_each_ipp_planar(i)
308 			rot_write(addr[i], ROT_SRC_BUF_ADDR(i));
309 		break;
310 	case IPP_BUF_DEQUEUE:
311 		for_each_ipp_planar(i)
312 			rot_write(0x0, ROT_SRC_BUF_ADDR(i));
313 		break;
314 	default:
315 		/* Nothing to do */
316 		break;
317 	}
318 
319 	return 0;
320 }
321 
322 static int rotator_dst_set_transf(struct device *dev,
323 		enum drm_exynos_degree degree,
324 		enum drm_exynos_flip flip, bool *swap)
325 {
326 	struct rot_context *rot = dev_get_drvdata(dev);
327 	u32 val;
328 
329 	/* Set transform configuration */
330 	val = rot_read(ROT_CONTROL);
331 	val &= ~ROT_CONTROL_FLIP_MASK;
332 
333 	switch (flip) {
334 	case EXYNOS_DRM_FLIP_VERTICAL:
335 		val |= ROT_CONTROL_FLIP_VERTICAL;
336 		break;
337 	case EXYNOS_DRM_FLIP_HORIZONTAL:
338 		val |= ROT_CONTROL_FLIP_HORIZONTAL;
339 		break;
340 	default:
341 		/* Flip None */
342 		break;
343 	}
344 
345 	val &= ~ROT_CONTROL_ROT_MASK;
346 
347 	switch (degree) {
348 	case EXYNOS_DRM_DEGREE_90:
349 		val |= ROT_CONTROL_ROT_90;
350 		break;
351 	case EXYNOS_DRM_DEGREE_180:
352 		val |= ROT_CONTROL_ROT_180;
353 		break;
354 	case EXYNOS_DRM_DEGREE_270:
355 		val |= ROT_CONTROL_ROT_270;
356 		break;
357 	default:
358 		/* Rotation 0 Degree */
359 		break;
360 	}
361 
362 	rot_write(val, ROT_CONTROL);
363 
364 	/* Check degree for setting buffer size swap */
365 	if ((degree == EXYNOS_DRM_DEGREE_90) ||
366 	    (degree == EXYNOS_DRM_DEGREE_270))
367 		*swap = true;
368 	else
369 		*swap = false;
370 
371 	return 0;
372 }
373 
374 static int rotator_dst_set_size(struct device *dev, int swap,
375 		struct drm_exynos_pos *pos,
376 		struct drm_exynos_sz *sz)
377 {
378 	struct rot_context *rot = dev_get_drvdata(dev);
379 	u32 val, fmt, hsize, vsize;
380 
381 	/* Get format */
382 	fmt = rotator_reg_get_fmt(rot);
383 	if (!rotator_check_reg_fmt(fmt)) {
384 		DRM_ERROR("invalid format.\n");
385 		return -EINVAL;
386 	}
387 
388 	/* Align buffer size */
389 	hsize = sz->hsize;
390 	vsize = sz->vsize;
391 	rotator_align_size(rot, fmt, &hsize, &vsize);
392 
393 	/* Set buffer size configuration */
394 	val = ROT_SET_BUF_SIZE_H(vsize) | ROT_SET_BUF_SIZE_W(hsize);
395 	rot_write(val, ROT_DST_BUF_SIZE);
396 
397 	/* Set crop image position configuration */
398 	val = ROT_CROP_POS_Y(pos->y) | ROT_CROP_POS_X(pos->x);
399 	rot_write(val, ROT_DST_CROP_POS);
400 
401 	return 0;
402 }
403 
404 static int rotator_dst_set_addr(struct device *dev,
405 		struct drm_exynos_ipp_buf_info *buf_info,
406 		u32 buf_id, enum drm_exynos_ipp_buf_type buf_type)
407 {
408 	struct rot_context *rot = dev_get_drvdata(dev);
409 	dma_addr_t addr[EXYNOS_DRM_PLANAR_MAX];
410 	u32 val, fmt, hsize, vsize;
411 	int i;
412 
413 	/* Set current buf_id */
414 	rot->cur_buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
415 
416 	switch (buf_type) {
417 	case IPP_BUF_ENQUEUE:
418 		/* Set address configuration */
419 		for_each_ipp_planar(i)
420 			addr[i] = buf_info->base[i];
421 
422 		/* Get format */
423 		fmt = rotator_reg_get_fmt(rot);
424 		if (!rotator_check_reg_fmt(fmt)) {
425 			DRM_ERROR("invalid format.\n");
426 			return -EINVAL;
427 		}
428 
429 		/* Re-set cb planar for NV12 format */
430 		if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) &&
431 		    !addr[EXYNOS_DRM_PLANAR_CB]) {
432 			/* Get buf size */
433 			val = rot_read(ROT_DST_BUF_SIZE);
434 
435 			hsize = ROT_GET_BUF_SIZE_W(val);
436 			vsize = ROT_GET_BUF_SIZE_H(val);
437 
438 			/* Set cb planar */
439 			addr[EXYNOS_DRM_PLANAR_CB] =
440 				addr[EXYNOS_DRM_PLANAR_Y] + hsize * vsize;
441 		}
442 
443 		for_each_ipp_planar(i)
444 			rot_write(addr[i], ROT_DST_BUF_ADDR(i));
445 		break;
446 	case IPP_BUF_DEQUEUE:
447 		for_each_ipp_planar(i)
448 			rot_write(0x0, ROT_DST_BUF_ADDR(i));
449 		break;
450 	default:
451 		/* Nothing to do */
452 		break;
453 	}
454 
455 	return 0;
456 }
457 
458 static struct exynos_drm_ipp_ops rot_src_ops = {
459 	.set_fmt	=	rotator_src_set_fmt,
460 	.set_size	=	rotator_src_set_size,
461 	.set_addr	=	rotator_src_set_addr,
462 };
463 
464 static struct exynos_drm_ipp_ops rot_dst_ops = {
465 	.set_transf	=	rotator_dst_set_transf,
466 	.set_size	=	rotator_dst_set_size,
467 	.set_addr	=	rotator_dst_set_addr,
468 };
469 
470 static int rotator_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
471 {
472 	struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
473 
474 	prop_list->version = 1;
475 	prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
476 				(1 << EXYNOS_DRM_FLIP_HORIZONTAL);
477 	prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
478 				(1 << EXYNOS_DRM_DEGREE_90) |
479 				(1 << EXYNOS_DRM_DEGREE_180) |
480 				(1 << EXYNOS_DRM_DEGREE_270);
481 	prop_list->csc = 0;
482 	prop_list->crop = 0;
483 	prop_list->scale = 0;
484 
485 	return 0;
486 }
487 
488 static inline bool rotator_check_drm_fmt(u32 fmt)
489 {
490 	switch (fmt) {
491 	case DRM_FORMAT_XRGB8888:
492 	case DRM_FORMAT_NV12:
493 		return true;
494 	default:
495 		DRM_DEBUG_KMS("not support format\n");
496 		return false;
497 	}
498 }
499 
500 static inline bool rotator_check_drm_flip(enum drm_exynos_flip flip)
501 {
502 	switch (flip) {
503 	case EXYNOS_DRM_FLIP_NONE:
504 	case EXYNOS_DRM_FLIP_VERTICAL:
505 	case EXYNOS_DRM_FLIP_HORIZONTAL:
506 	case EXYNOS_DRM_FLIP_BOTH:
507 		return true;
508 	default:
509 		DRM_DEBUG_KMS("invalid flip\n");
510 		return false;
511 	}
512 }
513 
514 static int rotator_ippdrv_check_property(struct device *dev,
515 		struct drm_exynos_ipp_property *property)
516 {
517 	struct drm_exynos_ipp_config *src_config =
518 					&property->config[EXYNOS_DRM_OPS_SRC];
519 	struct drm_exynos_ipp_config *dst_config =
520 					&property->config[EXYNOS_DRM_OPS_DST];
521 	struct drm_exynos_pos *src_pos = &src_config->pos;
522 	struct drm_exynos_pos *dst_pos = &dst_config->pos;
523 	struct drm_exynos_sz *src_sz = &src_config->sz;
524 	struct drm_exynos_sz *dst_sz = &dst_config->sz;
525 	bool swap = false;
526 
527 	/* Check format configuration */
528 	if (src_config->fmt != dst_config->fmt) {
529 		DRM_DEBUG_KMS("not support csc feature\n");
530 		return -EINVAL;
531 	}
532 
533 	if (!rotator_check_drm_fmt(dst_config->fmt)) {
534 		DRM_DEBUG_KMS("invalid format\n");
535 		return -EINVAL;
536 	}
537 
538 	/* Check transform configuration */
539 	if (src_config->degree != EXYNOS_DRM_DEGREE_0) {
540 		DRM_DEBUG_KMS("not support source-side rotation\n");
541 		return -EINVAL;
542 	}
543 
544 	switch (dst_config->degree) {
545 	case EXYNOS_DRM_DEGREE_90:
546 	case EXYNOS_DRM_DEGREE_270:
547 		swap = true;
548 	case EXYNOS_DRM_DEGREE_0:
549 	case EXYNOS_DRM_DEGREE_180:
550 		/* No problem */
551 		break;
552 	default:
553 		DRM_DEBUG_KMS("invalid degree\n");
554 		return -EINVAL;
555 	}
556 
557 	if (src_config->flip != EXYNOS_DRM_FLIP_NONE) {
558 		DRM_DEBUG_KMS("not support source-side flip\n");
559 		return -EINVAL;
560 	}
561 
562 	if (!rotator_check_drm_flip(dst_config->flip)) {
563 		DRM_DEBUG_KMS("invalid flip\n");
564 		return -EINVAL;
565 	}
566 
567 	/* Check size configuration */
568 	if ((src_pos->x + src_pos->w > src_sz->hsize) ||
569 		(src_pos->y + src_pos->h > src_sz->vsize)) {
570 		DRM_DEBUG_KMS("out of source buffer bound\n");
571 		return -EINVAL;
572 	}
573 
574 	if (swap) {
575 		if ((dst_pos->x + dst_pos->h > dst_sz->vsize) ||
576 			(dst_pos->y + dst_pos->w > dst_sz->hsize)) {
577 			DRM_DEBUG_KMS("out of destination buffer bound\n");
578 			return -EINVAL;
579 		}
580 
581 		if ((src_pos->w != dst_pos->h) || (src_pos->h != dst_pos->w)) {
582 			DRM_DEBUG_KMS("not support scale feature\n");
583 			return -EINVAL;
584 		}
585 	} else {
586 		if ((dst_pos->x + dst_pos->w > dst_sz->hsize) ||
587 			(dst_pos->y + dst_pos->h > dst_sz->vsize)) {
588 			DRM_DEBUG_KMS("out of destination buffer bound\n");
589 			return -EINVAL;
590 		}
591 
592 		if ((src_pos->w != dst_pos->w) || (src_pos->h != dst_pos->h)) {
593 			DRM_DEBUG_KMS("not support scale feature\n");
594 			return -EINVAL;
595 		}
596 	}
597 
598 	return 0;
599 }
600 
601 static int rotator_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
602 {
603 	struct rot_context *rot = dev_get_drvdata(dev);
604 	u32 val;
605 
606 	if (rot->suspended) {
607 		DRM_ERROR("suspended state\n");
608 		return -EPERM;
609 	}
610 
611 	if (cmd != IPP_CMD_M2M) {
612 		DRM_ERROR("not support cmd: %d\n", cmd);
613 		return -EINVAL;
614 	}
615 
616 	/* Set interrupt enable */
617 	rotator_reg_set_irq(rot, true);
618 
619 	val = rot_read(ROT_CONTROL);
620 	val |= ROT_CONTROL_START;
621 
622 	rot_write(val, ROT_CONTROL);
623 
624 	return 0;
625 }
626 
627 static struct rot_limit_table rot_limit_tbl_4210 = {
628 	.ycbcr420_2p = {
629 		.min_w = 32,
630 		.min_h = 32,
631 		.max_w = SZ_64K,
632 		.max_h = SZ_64K,
633 		.align = 3,
634 	},
635 	.rgb888 = {
636 		.min_w = 8,
637 		.min_h = 8,
638 		.max_w = SZ_16K,
639 		.max_h = SZ_16K,
640 		.align = 2,
641 	},
642 };
643 
644 static struct rot_limit_table rot_limit_tbl_4x12 = {
645 	.ycbcr420_2p = {
646 		.min_w = 32,
647 		.min_h = 32,
648 		.max_w = SZ_32K,
649 		.max_h = SZ_32K,
650 		.align = 3,
651 	},
652 	.rgb888 = {
653 		.min_w = 8,
654 		.min_h = 8,
655 		.max_w = SZ_8K,
656 		.max_h = SZ_8K,
657 		.align = 2,
658 	},
659 };
660 
661 static struct rot_limit_table rot_limit_tbl_5250 = {
662 	.ycbcr420_2p = {
663 		.min_w = 32,
664 		.min_h = 32,
665 		.max_w = SZ_32K,
666 		.max_h = SZ_32K,
667 		.align = 3,
668 	},
669 	.rgb888 = {
670 		.min_w = 8,
671 		.min_h = 8,
672 		.max_w = SZ_8K,
673 		.max_h = SZ_8K,
674 		.align = 1,
675 	},
676 };
677 
678 static const struct of_device_id exynos_rotator_match[] = {
679 	{
680 		.compatible = "samsung,exynos4210-rotator",
681 		.data = &rot_limit_tbl_4210,
682 	},
683 	{
684 		.compatible = "samsung,exynos4212-rotator",
685 		.data = &rot_limit_tbl_4x12,
686 	},
687 	{
688 		.compatible = "samsung,exynos5250-rotator",
689 		.data = &rot_limit_tbl_5250,
690 	},
691 	{},
692 };
693 MODULE_DEVICE_TABLE(of, exynos_rotator_match);
694 
695 static int rotator_probe(struct platform_device *pdev)
696 {
697 	struct device *dev = &pdev->dev;
698 	struct rot_context *rot;
699 	struct exynos_drm_ippdrv *ippdrv;
700 	int ret;
701 
702 	if (!dev->of_node) {
703 		dev_err(dev, "cannot find of_node.\n");
704 		return -ENODEV;
705 	}
706 
707 	rot = devm_kzalloc(dev, sizeof(*rot), GFP_KERNEL);
708 	if (!rot)
709 		return -ENOMEM;
710 
711 	rot->limit_tbl = (struct rot_limit_table *)
712 				of_device_get_match_data(dev);
713 	rot->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
714 	rot->regs = devm_ioremap_resource(dev, rot->regs_res);
715 	if (IS_ERR(rot->regs))
716 		return PTR_ERR(rot->regs);
717 
718 	rot->irq = platform_get_irq(pdev, 0);
719 	if (rot->irq < 0) {
720 		dev_err(dev, "failed to get irq\n");
721 		return rot->irq;
722 	}
723 
724 	ret = devm_request_threaded_irq(dev, rot->irq, NULL,
725 			rotator_irq_handler, IRQF_ONESHOT, "drm_rotator", rot);
726 	if (ret < 0) {
727 		dev_err(dev, "failed to request irq\n");
728 		return ret;
729 	}
730 
731 	rot->clock = devm_clk_get(dev, "rotator");
732 	if (IS_ERR(rot->clock)) {
733 		dev_err(dev, "failed to get clock\n");
734 		return PTR_ERR(rot->clock);
735 	}
736 
737 	pm_runtime_enable(dev);
738 
739 	ippdrv = &rot->ippdrv;
740 	ippdrv->dev = dev;
741 	ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &rot_src_ops;
742 	ippdrv->ops[EXYNOS_DRM_OPS_DST] = &rot_dst_ops;
743 	ippdrv->check_property = rotator_ippdrv_check_property;
744 	ippdrv->start = rotator_ippdrv_start;
745 	ret = rotator_init_prop_list(ippdrv);
746 	if (ret < 0) {
747 		dev_err(dev, "failed to init property list.\n");
748 		goto err_ippdrv_register;
749 	}
750 
751 	DRM_DEBUG_KMS("ippdrv[%pK]\n", ippdrv);
752 
753 	platform_set_drvdata(pdev, rot);
754 
755 	ret = exynos_drm_ippdrv_register(ippdrv);
756 	if (ret < 0) {
757 		dev_err(dev, "failed to register drm rotator device\n");
758 		goto err_ippdrv_register;
759 	}
760 
761 	dev_info(dev, "The exynos rotator is probed successfully\n");
762 
763 	return 0;
764 
765 err_ippdrv_register:
766 	pm_runtime_disable(dev);
767 	return ret;
768 }
769 
770 static int rotator_remove(struct platform_device *pdev)
771 {
772 	struct device *dev = &pdev->dev;
773 	struct rot_context *rot = dev_get_drvdata(dev);
774 	struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
775 
776 	exynos_drm_ippdrv_unregister(ippdrv);
777 
778 	pm_runtime_disable(dev);
779 
780 	return 0;
781 }
782 
783 #ifdef CONFIG_PM
784 static int rotator_clk_crtl(struct rot_context *rot, bool enable)
785 {
786 	if (enable) {
787 		clk_prepare_enable(rot->clock);
788 		rot->suspended = false;
789 	} else {
790 		clk_disable_unprepare(rot->clock);
791 		rot->suspended = true;
792 	}
793 
794 	return 0;
795 }
796 
797 static int rotator_runtime_suspend(struct device *dev)
798 {
799 	struct rot_context *rot = dev_get_drvdata(dev);
800 
801 	return  rotator_clk_crtl(rot, false);
802 }
803 
804 static int rotator_runtime_resume(struct device *dev)
805 {
806 	struct rot_context *rot = dev_get_drvdata(dev);
807 
808 	return  rotator_clk_crtl(rot, true);
809 }
810 #endif
811 
812 static const struct dev_pm_ops rotator_pm_ops = {
813 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
814 				pm_runtime_force_resume)
815 	SET_RUNTIME_PM_OPS(rotator_runtime_suspend, rotator_runtime_resume,
816 									NULL)
817 };
818 
819 struct platform_driver rotator_driver = {
820 	.probe		= rotator_probe,
821 	.remove		= rotator_remove,
822 	.driver		= {
823 		.name	= "exynos-rot",
824 		.owner	= THIS_MODULE,
825 		.pm	= &rotator_pm_ops,
826 		.of_match_table = exynos_rotator_match,
827 	},
828 };
829