1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2012 Samsung Electronics Co.Ltd
4  * Authors:
5  *	Eunchul Kim <chulspro.kim@samsung.com>
6  *	Jinyoung Jeon <jy0.jeon@samsung.com>
7  *	Sangmin Lee <lsmin.lee@samsung.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_print.h>
21 #include <drm/exynos_drm.h>
22 
23 #include "exynos_drm_drv.h"
24 #include "exynos_drm_ipp.h"
25 #include "regs-gsc.h"
26 
27 /*
28  * GSC stands for General SCaler and
29  * supports image scaler/rotator and input/output DMA operations.
30  * input DMA reads image data from the memory.
31  * output DMA writes image data to memory.
32  * GSC supports image rotation and image effect functions.
33  */
34 
35 
36 #define GSC_MAX_CLOCKS	8
37 #define GSC_MAX_SRC		4
38 #define GSC_MAX_DST		16
39 #define GSC_RESET_TIMEOUT	50
40 #define GSC_BUF_STOP	1
41 #define GSC_BUF_START	2
42 #define GSC_REG_SZ		16
43 #define GSC_WIDTH_ITU_709	1280
44 #define GSC_SC_UP_MAX_RATIO		65536
45 #define GSC_SC_DOWN_RATIO_7_8		74898
46 #define GSC_SC_DOWN_RATIO_6_8		87381
47 #define GSC_SC_DOWN_RATIO_5_8		104857
48 #define GSC_SC_DOWN_RATIO_4_8		131072
49 #define GSC_SC_DOWN_RATIO_3_8		174762
50 #define GSC_SC_DOWN_RATIO_2_8		262144
51 #define GSC_CROP_MAX	8192
52 #define GSC_CROP_MIN	32
53 #define GSC_SCALE_MAX	4224
54 #define GSC_SCALE_MIN	32
55 #define GSC_COEF_RATIO	7
56 #define GSC_COEF_PHASE	9
57 #define GSC_COEF_ATTR	16
58 #define GSC_COEF_H_8T	8
59 #define GSC_COEF_V_4T	4
60 #define GSC_COEF_DEPTH	3
61 #define GSC_AUTOSUSPEND_DELAY		2000
62 
63 #define get_gsc_context(dev)	dev_get_drvdata(dev)
64 #define gsc_read(offset)		readl(ctx->regs + (offset))
65 #define gsc_write(cfg, offset)	writel(cfg, ctx->regs + (offset))
66 
67 /*
68  * A structure of scaler.
69  *
70  * @range: narrow, wide.
71  * @pre_shfactor: pre sclaer shift factor.
72  * @pre_hratio: horizontal ratio of the prescaler.
73  * @pre_vratio: vertical ratio of the prescaler.
74  * @main_hratio: the main scaler's horizontal ratio.
75  * @main_vratio: the main scaler's vertical ratio.
76  */
77 struct gsc_scaler {
78 	bool	range;
79 	u32	pre_shfactor;
80 	u32	pre_hratio;
81 	u32	pre_vratio;
82 	unsigned long main_hratio;
83 	unsigned long main_vratio;
84 };
85 
86 /*
87  * A structure of gsc context.
88  *
89  * @regs_res: register resources.
90  * @regs: memory mapped io registers.
91  * @gsc_clk: gsc gate clock.
92  * @sc: scaler infomations.
93  * @id: gsc id.
94  * @irq: irq number.
95  * @rotation: supports rotation of src.
96  */
97 struct gsc_context {
98 	struct exynos_drm_ipp ipp;
99 	struct drm_device *drm_dev;
100 	void		*dma_priv;
101 	struct device	*dev;
102 	struct exynos_drm_ipp_task	*task;
103 	struct exynos_drm_ipp_formats	*formats;
104 	unsigned int			num_formats;
105 
106 	struct resource	*regs_res;
107 	void __iomem	*regs;
108 	const char	**clk_names;
109 	struct clk	*clocks[GSC_MAX_CLOCKS];
110 	int		num_clocks;
111 	struct gsc_scaler	sc;
112 	int	id;
113 	int	irq;
114 	bool	rotation;
115 };
116 
117 /**
118  * struct gsc_driverdata - per device type driver data for init time.
119  *
120  * @limits: picture size limits array
121  * @clk_names: names of clocks needed by this variant
122  * @num_clocks: the number of clocks needed by this variant
123  */
124 struct gsc_driverdata {
125 	const struct drm_exynos_ipp_limit *limits;
126 	int		num_limits;
127 	const char	*clk_names[GSC_MAX_CLOCKS];
128 	int		num_clocks;
129 };
130 
131 /* 8-tap Filter Coefficient */
132 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
133 	{	/* Ratio <= 65536 (~8:8) */
134 		{  0,  0,   0, 128,   0,   0,  0,  0 },
135 		{ -1,  2,  -6, 127,   7,  -2,  1,  0 },
136 		{ -1,  4, -12, 125,  16,  -5,  1,  0 },
137 		{ -1,  5, -15, 120,  25,  -8,  2,  0 },
138 		{ -1,  6, -18, 114,  35, -10,  3, -1 },
139 		{ -1,  6, -20, 107,  46, -13,  4, -1 },
140 		{ -2,  7, -21,  99,  57, -16,  5, -1 },
141 		{ -1,  6, -20,  89,  68, -18,  5, -1 },
142 		{ -1,  6, -20,  79,  79, -20,  6, -1 },
143 		{ -1,  5, -18,  68,  89, -20,  6, -1 },
144 		{ -1,  5, -16,  57,  99, -21,  7, -2 },
145 		{ -1,  4, -13,  46, 107, -20,  6, -1 },
146 		{ -1,  3, -10,  35, 114, -18,  6, -1 },
147 		{  0,  2,  -8,  25, 120, -15,  5, -1 },
148 		{  0,  1,  -5,  16, 125, -12,  4, -1 },
149 		{  0,  1,  -2,   7, 127,  -6,  2, -1 }
150 	}, {	/* 65536 < Ratio <= 74898 (~8:7) */
151 		{  3, -8,  14, 111,  13,  -8,  3,  0 },
152 		{  2, -6,   7, 112,  21, -10,  3, -1 },
153 		{  2, -4,   1, 110,  28, -12,  4, -1 },
154 		{  1, -2,  -3, 106,  36, -13,  4, -1 },
155 		{  1, -1,  -7, 103,  44, -15,  4, -1 },
156 		{  1,  1, -11,  97,  53, -16,  4, -1 },
157 		{  0,  2, -13,  91,  61, -16,  4, -1 },
158 		{  0,  3, -15,  85,  69, -17,  4, -1 },
159 		{  0,  3, -16,  77,  77, -16,  3,  0 },
160 		{ -1,  4, -17,  69,  85, -15,  3,  0 },
161 		{ -1,  4, -16,  61,  91, -13,  2,  0 },
162 		{ -1,  4, -16,  53,  97, -11,  1,  1 },
163 		{ -1,  4, -15,  44, 103,  -7, -1,  1 },
164 		{ -1,  4, -13,  36, 106,  -3, -2,  1 },
165 		{ -1,  4, -12,  28, 110,   1, -4,  2 },
166 		{ -1,  3, -10,  21, 112,   7, -6,  2 }
167 	}, {	/* 74898 < Ratio <= 87381 (~8:6) */
168 		{ 2, -11,  25,  96, 25, -11,   2,  0 },
169 		{ 2, -10,  19,  96, 31, -12,   2,  0 },
170 		{ 2,  -9,  14,  94, 37, -12,   2,  0 },
171 		{ 2,  -8,  10,  92, 43, -12,   1,  0 },
172 		{ 2,  -7,   5,  90, 49, -12,   1,  0 },
173 		{ 2,  -5,   1,  86, 55, -12,   0,  1 },
174 		{ 2,  -4,  -2,  82, 61, -11,  -1,  1 },
175 		{ 1,  -3,  -5,  77, 67,  -9,  -1,  1 },
176 		{ 1,  -2,  -7,  72, 72,  -7,  -2,  1 },
177 		{ 1,  -1,  -9,  67, 77,  -5,  -3,  1 },
178 		{ 1,  -1, -11,  61, 82,  -2,  -4,  2 },
179 		{ 1,   0, -12,  55, 86,   1,  -5,  2 },
180 		{ 0,   1, -12,  49, 90,   5,  -7,  2 },
181 		{ 0,   1, -12,  43, 92,  10,  -8,  2 },
182 		{ 0,   2, -12,  37, 94,  14,  -9,  2 },
183 		{ 0,   2, -12,  31, 96,  19, -10,  2 }
184 	}, {	/* 87381 < Ratio <= 104857 (~8:5) */
185 		{ -1,  -8, 33,  80, 33,  -8,  -1,  0 },
186 		{ -1,  -8, 28,  80, 37,  -7,  -2,  1 },
187 		{  0,  -8, 24,  79, 41,  -7,  -2,  1 },
188 		{  0,  -8, 20,  78, 46,  -6,  -3,  1 },
189 		{  0,  -8, 16,  76, 50,  -4,  -3,  1 },
190 		{  0,  -7, 13,  74, 54,  -3,  -4,  1 },
191 		{  1,  -7, 10,  71, 58,  -1,  -5,  1 },
192 		{  1,  -6,  6,  68, 62,   1,  -5,  1 },
193 		{  1,  -6,  4,  65, 65,   4,  -6,  1 },
194 		{  1,  -5,  1,  62, 68,   6,  -6,  1 },
195 		{  1,  -5, -1,  58, 71,  10,  -7,  1 },
196 		{  1,  -4, -3,  54, 74,  13,  -7,  0 },
197 		{  1,  -3, -4,  50, 76,  16,  -8,  0 },
198 		{  1,  -3, -6,  46, 78,  20,  -8,  0 },
199 		{  1,  -2, -7,  41, 79,  24,  -8,  0 },
200 		{  1,  -2, -7,  37, 80,  28,  -8, -1 }
201 	}, {	/* 104857 < Ratio <= 131072 (~8:4) */
202 		{ -3,   0, 35,  64, 35,   0,  -3,  0 },
203 		{ -3,  -1, 32,  64, 38,   1,  -3,  0 },
204 		{ -2,  -2, 29,  63, 41,   2,  -3,  0 },
205 		{ -2,  -3, 27,  63, 43,   4,  -4,  0 },
206 		{ -2,  -3, 24,  61, 46,   6,  -4,  0 },
207 		{ -2,  -3, 21,  60, 49,   7,  -4,  0 },
208 		{ -1,  -4, 19,  59, 51,   9,  -4, -1 },
209 		{ -1,  -4, 16,  57, 53,  12,  -4, -1 },
210 		{ -1,  -4, 14,  55, 55,  14,  -4, -1 },
211 		{ -1,  -4, 12,  53, 57,  16,  -4, -1 },
212 		{ -1,  -4,  9,  51, 59,  19,  -4, -1 },
213 		{  0,  -4,  7,  49, 60,  21,  -3, -2 },
214 		{  0,  -4,  6,  46, 61,  24,  -3, -2 },
215 		{  0,  -4,  4,  43, 63,  27,  -3, -2 },
216 		{  0,  -3,  2,  41, 63,  29,  -2, -2 },
217 		{  0,  -3,  1,  38, 64,  32,  -1, -3 }
218 	}, {	/* 131072 < Ratio <= 174762 (~8:3) */
219 		{ -1,   8, 33,  48, 33,   8,  -1,  0 },
220 		{ -1,   7, 31,  49, 35,   9,  -1, -1 },
221 		{ -1,   6, 30,  49, 36,  10,  -1, -1 },
222 		{ -1,   5, 28,  48, 38,  12,  -1, -1 },
223 		{ -1,   4, 26,  48, 39,  13,   0, -1 },
224 		{ -1,   3, 24,  47, 41,  15,   0, -1 },
225 		{ -1,   2, 23,  47, 42,  16,   0, -1 },
226 		{ -1,   2, 21,  45, 43,  18,   1, -1 },
227 		{ -1,   1, 19,  45, 45,  19,   1, -1 },
228 		{ -1,   1, 18,  43, 45,  21,   2, -1 },
229 		{ -1,   0, 16,  42, 47,  23,   2, -1 },
230 		{ -1,   0, 15,  41, 47,  24,   3, -1 },
231 		{ -1,   0, 13,  39, 48,  26,   4, -1 },
232 		{ -1,  -1, 12,  38, 48,  28,   5, -1 },
233 		{ -1,  -1, 10,  36, 49,  30,   6, -1 },
234 		{ -1,  -1,  9,  35, 49,  31,   7, -1 }
235 	}, {	/* 174762 < Ratio <= 262144 (~8:2) */
236 		{  2,  13, 30,  38, 30,  13,   2,  0 },
237 		{  2,  12, 29,  38, 30,  14,   3,  0 },
238 		{  2,  11, 28,  38, 31,  15,   3,  0 },
239 		{  2,  10, 26,  38, 32,  16,   4,  0 },
240 		{  1,  10, 26,  37, 33,  17,   4,  0 },
241 		{  1,   9, 24,  37, 34,  18,   5,  0 },
242 		{  1,   8, 24,  37, 34,  19,   5,  0 },
243 		{  1,   7, 22,  36, 35,  20,   6,  1 },
244 		{  1,   6, 21,  36, 36,  21,   6,  1 },
245 		{  1,   6, 20,  35, 36,  22,   7,  1 },
246 		{  0,   5, 19,  34, 37,  24,   8,  1 },
247 		{  0,   5, 18,  34, 37,  24,   9,  1 },
248 		{  0,   4, 17,  33, 37,  26,  10,  1 },
249 		{  0,   4, 16,  32, 38,  26,  10,  2 },
250 		{  0,   3, 15,  31, 38,  28,  11,  2 },
251 		{  0,   3, 14,  30, 38,  29,  12,  2 }
252 	}
253 };
254 
255 /* 4-tap Filter Coefficient */
256 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
257 	{	/* Ratio <= 65536 (~8:8) */
258 		{  0, 128,   0,  0 },
259 		{ -4, 127,   5,  0 },
260 		{ -6, 124,  11, -1 },
261 		{ -8, 118,  19, -1 },
262 		{ -8, 111,  27, -2 },
263 		{ -8, 102,  37, -3 },
264 		{ -8,  92,  48, -4 },
265 		{ -7,  81,  59, -5 },
266 		{ -6,  70,  70, -6 },
267 		{ -5,  59,  81, -7 },
268 		{ -4,  48,  92, -8 },
269 		{ -3,  37, 102, -8 },
270 		{ -2,  27, 111, -8 },
271 		{ -1,  19, 118, -8 },
272 		{ -1,  11, 124, -6 },
273 		{  0,   5, 127, -4 }
274 	}, {	/* 65536 < Ratio <= 74898 (~8:7) */
275 		{  8, 112,   8,  0 },
276 		{  4, 111,  14, -1 },
277 		{  1, 109,  20, -2 },
278 		{ -2, 105,  27, -2 },
279 		{ -3, 100,  34, -3 },
280 		{ -5,  93,  43, -3 },
281 		{ -5,  86,  51, -4 },
282 		{ -5,  77,  60, -4 },
283 		{ -5,  69,  69, -5 },
284 		{ -4,  60,  77, -5 },
285 		{ -4,  51,  86, -5 },
286 		{ -3,  43,  93, -5 },
287 		{ -3,  34, 100, -3 },
288 		{ -2,  27, 105, -2 },
289 		{ -2,  20, 109,  1 },
290 		{ -1,  14, 111,  4 }
291 	}, {	/* 74898 < Ratio <= 87381 (~8:6) */
292 		{ 16,  96,  16,  0 },
293 		{ 12,  97,  21, -2 },
294 		{  8,  96,  26, -2 },
295 		{  5,  93,  32, -2 },
296 		{  2,  89,  39, -2 },
297 		{  0,  84,  46, -2 },
298 		{ -1,  79,  53, -3 },
299 		{ -2,  73,  59, -2 },
300 		{ -2,  66,  66, -2 },
301 		{ -2,  59,  73, -2 },
302 		{ -3,  53,  79, -1 },
303 		{ -2,  46,  84,  0 },
304 		{ -2,  39,  89,  2 },
305 		{ -2,  32,  93,  5 },
306 		{ -2,  26,  96,  8 },
307 		{ -2,  21,  97, 12 }
308 	}, {	/* 87381 < Ratio <= 104857 (~8:5) */
309 		{ 22,  84,  22,  0 },
310 		{ 18,  85,  26, -1 },
311 		{ 14,  84,  31, -1 },
312 		{ 11,  82,  36, -1 },
313 		{  8,  79,  42, -1 },
314 		{  6,  76,  47, -1 },
315 		{  4,  72,  52,  0 },
316 		{  2,  68,  58,  0 },
317 		{  1,  63,  63,  1 },
318 		{  0,  58,  68,  2 },
319 		{  0,  52,  72,  4 },
320 		{ -1,  47,  76,  6 },
321 		{ -1,  42,  79,  8 },
322 		{ -1,  36,  82, 11 },
323 		{ -1,  31,  84, 14 },
324 		{ -1,  26,  85, 18 }
325 	}, {	/* 104857 < Ratio <= 131072 (~8:4) */
326 		{ 26,  76,  26,  0 },
327 		{ 22,  76,  30,  0 },
328 		{ 19,  75,  34,  0 },
329 		{ 16,  73,  38,  1 },
330 		{ 13,  71,  43,  1 },
331 		{ 10,  69,  47,  2 },
332 		{  8,  66,  51,  3 },
333 		{  6,  63,  55,  4 },
334 		{  5,  59,  59,  5 },
335 		{  4,  55,  63,  6 },
336 		{  3,  51,  66,  8 },
337 		{  2,  47,  69, 10 },
338 		{  1,  43,  71, 13 },
339 		{  1,  38,  73, 16 },
340 		{  0,  34,  75, 19 },
341 		{  0,  30,  76, 22 }
342 	}, {	/* 131072 < Ratio <= 174762 (~8:3) */
343 		{ 29,  70,  29,  0 },
344 		{ 26,  68,  32,  2 },
345 		{ 23,  67,  36,  2 },
346 		{ 20,  66,  39,  3 },
347 		{ 17,  65,  43,  3 },
348 		{ 15,  63,  46,  4 },
349 		{ 12,  61,  50,  5 },
350 		{ 10,  58,  53,  7 },
351 		{  8,  56,  56,  8 },
352 		{  7,  53,  58, 10 },
353 		{  5,  50,  61, 12 },
354 		{  4,  46,  63, 15 },
355 		{  3,  43,  65, 17 },
356 		{  3,  39,  66, 20 },
357 		{  2,  36,  67, 23 },
358 		{  2,  32,  68, 26 }
359 	}, {	/* 174762 < Ratio <= 262144 (~8:2) */
360 		{ 32,  64,  32,  0 },
361 		{ 28,  63,  34,  3 },
362 		{ 25,  62,  37,  4 },
363 		{ 22,  62,  40,  4 },
364 		{ 19,  61,  43,  5 },
365 		{ 17,  59,  46,  6 },
366 		{ 15,  58,  48,  7 },
367 		{ 13,  55,  51,  9 },
368 		{ 11,  53,  53, 11 },
369 		{  9,  51,  55, 13 },
370 		{  7,  48,  58, 15 },
371 		{  6,  46,  59, 17 },
372 		{  5,  43,  61, 19 },
373 		{  4,  40,  62, 22 },
374 		{  4,  37,  62, 25 },
375 		{  3,  34,  63, 28 }
376 	}
377 };
378 
379 static int gsc_sw_reset(struct gsc_context *ctx)
380 {
381 	u32 cfg;
382 	int count = GSC_RESET_TIMEOUT;
383 
384 	/* s/w reset */
385 	cfg = (GSC_SW_RESET_SRESET);
386 	gsc_write(cfg, GSC_SW_RESET);
387 
388 	/* wait s/w reset complete */
389 	while (count--) {
390 		cfg = gsc_read(GSC_SW_RESET);
391 		if (!cfg)
392 			break;
393 		usleep_range(1000, 2000);
394 	}
395 
396 	if (cfg) {
397 		DRM_DEV_ERROR(ctx->dev, "failed to reset gsc h/w.\n");
398 		return -EBUSY;
399 	}
400 
401 	/* reset sequence */
402 	cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
403 	cfg |= (GSC_IN_BASE_ADDR_MASK |
404 		GSC_IN_BASE_ADDR_PINGPONG(0));
405 	gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
406 	gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
407 	gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
408 
409 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
410 	cfg |= (GSC_OUT_BASE_ADDR_MASK |
411 		GSC_OUT_BASE_ADDR_PINGPONG(0));
412 	gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
413 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
414 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
415 
416 	return 0;
417 }
418 
419 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
420 		bool overflow, bool done)
421 {
422 	u32 cfg;
423 
424 	DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]overflow[%d]level[%d]\n",
425 			  enable, overflow, done);
426 
427 	cfg = gsc_read(GSC_IRQ);
428 	cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
429 
430 	if (enable)
431 		cfg |= GSC_IRQ_ENABLE;
432 	else
433 		cfg &= ~GSC_IRQ_ENABLE;
434 
435 	if (overflow)
436 		cfg &= ~GSC_IRQ_OR_MASK;
437 	else
438 		cfg |= GSC_IRQ_OR_MASK;
439 
440 	if (done)
441 		cfg &= ~GSC_IRQ_FRMDONE_MASK;
442 	else
443 		cfg |= GSC_IRQ_FRMDONE_MASK;
444 
445 	gsc_write(cfg, GSC_IRQ);
446 }
447 
448 
449 static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
450 {
451 	u32 cfg;
452 
453 	DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
454 
455 	cfg = gsc_read(GSC_IN_CON);
456 	cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
457 		 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
458 		 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
459 		 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
460 
461 	switch (fmt) {
462 	case DRM_FORMAT_RGB565:
463 		cfg |= GSC_IN_RGB565;
464 		break;
465 	case DRM_FORMAT_XRGB8888:
466 	case DRM_FORMAT_ARGB8888:
467 		cfg |= GSC_IN_XRGB8888;
468 		break;
469 	case DRM_FORMAT_BGRX8888:
470 		cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
471 		break;
472 	case DRM_FORMAT_YUYV:
473 		cfg |= (GSC_IN_YUV422_1P |
474 			GSC_IN_YUV422_1P_ORDER_LSB_Y |
475 			GSC_IN_CHROMA_ORDER_CBCR);
476 		break;
477 	case DRM_FORMAT_YVYU:
478 		cfg |= (GSC_IN_YUV422_1P |
479 			GSC_IN_YUV422_1P_ORDER_LSB_Y |
480 			GSC_IN_CHROMA_ORDER_CRCB);
481 		break;
482 	case DRM_FORMAT_UYVY:
483 		cfg |= (GSC_IN_YUV422_1P |
484 			GSC_IN_YUV422_1P_OEDER_LSB_C |
485 			GSC_IN_CHROMA_ORDER_CBCR);
486 		break;
487 	case DRM_FORMAT_VYUY:
488 		cfg |= (GSC_IN_YUV422_1P |
489 			GSC_IN_YUV422_1P_OEDER_LSB_C |
490 			GSC_IN_CHROMA_ORDER_CRCB);
491 		break;
492 	case DRM_FORMAT_NV21:
493 		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
494 		break;
495 	case DRM_FORMAT_NV61:
496 		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
497 		break;
498 	case DRM_FORMAT_YUV422:
499 		cfg |= GSC_IN_YUV422_3P;
500 		break;
501 	case DRM_FORMAT_YUV420:
502 		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
503 		break;
504 	case DRM_FORMAT_YVU420:
505 		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
506 		break;
507 	case DRM_FORMAT_NV12:
508 		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
509 		break;
510 	case DRM_FORMAT_NV16:
511 		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
512 		break;
513 	}
514 
515 	if (tiled)
516 		cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
517 
518 	gsc_write(cfg, GSC_IN_CON);
519 }
520 
521 static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation)
522 {
523 	unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
524 	u32 cfg;
525 
526 	cfg = gsc_read(GSC_IN_CON);
527 	cfg &= ~GSC_IN_ROT_MASK;
528 
529 	switch (degree) {
530 	case DRM_MODE_ROTATE_0:
531 		if (rotation & DRM_MODE_REFLECT_X)
532 			cfg |= GSC_IN_ROT_XFLIP;
533 		if (rotation & DRM_MODE_REFLECT_Y)
534 			cfg |= GSC_IN_ROT_YFLIP;
535 		break;
536 	case DRM_MODE_ROTATE_90:
537 		cfg |= GSC_IN_ROT_90;
538 		if (rotation & DRM_MODE_REFLECT_X)
539 			cfg |= GSC_IN_ROT_XFLIP;
540 		if (rotation & DRM_MODE_REFLECT_Y)
541 			cfg |= GSC_IN_ROT_YFLIP;
542 		break;
543 	case DRM_MODE_ROTATE_180:
544 		cfg |= GSC_IN_ROT_180;
545 		if (rotation & DRM_MODE_REFLECT_X)
546 			cfg &= ~GSC_IN_ROT_XFLIP;
547 		if (rotation & DRM_MODE_REFLECT_Y)
548 			cfg &= ~GSC_IN_ROT_YFLIP;
549 		break;
550 	case DRM_MODE_ROTATE_270:
551 		cfg |= GSC_IN_ROT_270;
552 		if (rotation & DRM_MODE_REFLECT_X)
553 			cfg &= ~GSC_IN_ROT_XFLIP;
554 		if (rotation & DRM_MODE_REFLECT_Y)
555 			cfg &= ~GSC_IN_ROT_YFLIP;
556 		break;
557 	}
558 
559 	gsc_write(cfg, GSC_IN_CON);
560 
561 	ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
562 }
563 
564 static void gsc_src_set_size(struct gsc_context *ctx,
565 			     struct exynos_drm_ipp_buffer *buf)
566 {
567 	struct gsc_scaler *sc = &ctx->sc;
568 	u32 cfg;
569 
570 	/* pixel offset */
571 	cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) |
572 		GSC_SRCIMG_OFFSET_Y(buf->rect.y));
573 	gsc_write(cfg, GSC_SRCIMG_OFFSET);
574 
575 	/* cropped size */
576 	cfg = (GSC_CROPPED_WIDTH(buf->rect.w) |
577 		GSC_CROPPED_HEIGHT(buf->rect.h));
578 	gsc_write(cfg, GSC_CROPPED_SIZE);
579 
580 	/* original size */
581 	cfg = gsc_read(GSC_SRCIMG_SIZE);
582 	cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
583 		GSC_SRCIMG_WIDTH_MASK);
584 
585 	cfg |= (GSC_SRCIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
586 		GSC_SRCIMG_HEIGHT(buf->buf.height));
587 
588 	gsc_write(cfg, GSC_SRCIMG_SIZE);
589 
590 	cfg = gsc_read(GSC_IN_CON);
591 	cfg &= ~GSC_IN_RGB_TYPE_MASK;
592 
593 	if (buf->rect.w >= GSC_WIDTH_ITU_709)
594 		if (sc->range)
595 			cfg |= GSC_IN_RGB_HD_WIDE;
596 		else
597 			cfg |= GSC_IN_RGB_HD_NARROW;
598 	else
599 		if (sc->range)
600 			cfg |= GSC_IN_RGB_SD_WIDE;
601 		else
602 			cfg |= GSC_IN_RGB_SD_NARROW;
603 
604 	gsc_write(cfg, GSC_IN_CON);
605 }
606 
607 static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
608 			       bool enqueue)
609 {
610 	bool masked = !enqueue;
611 	u32 cfg;
612 	u32 mask = 0x00000001 << buf_id;
613 
614 	/* mask register set */
615 	cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
616 
617 	/* sequence id */
618 	cfg &= ~mask;
619 	cfg |= masked << buf_id;
620 	gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
621 	gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
622 	gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
623 }
624 
625 static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
626 			    struct exynos_drm_ipp_buffer *buf)
627 {
628 	/* address register set */
629 	gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
630 	gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
631 	gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
632 
633 	gsc_src_set_buf_seq(ctx, buf_id, true);
634 }
635 
636 static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
637 {
638 	u32 cfg;
639 
640 	DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
641 
642 	cfg = gsc_read(GSC_OUT_CON);
643 	cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
644 		 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
645 		 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
646 		 GSC_OUT_GLOBAL_ALPHA_MASK);
647 
648 	switch (fmt) {
649 	case DRM_FORMAT_RGB565:
650 		cfg |= GSC_OUT_RGB565;
651 		break;
652 	case DRM_FORMAT_ARGB8888:
653 	case DRM_FORMAT_XRGB8888:
654 		cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
655 		break;
656 	case DRM_FORMAT_BGRX8888:
657 		cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
658 		break;
659 	case DRM_FORMAT_YUYV:
660 		cfg |= (GSC_OUT_YUV422_1P |
661 			GSC_OUT_YUV422_1P_ORDER_LSB_Y |
662 			GSC_OUT_CHROMA_ORDER_CBCR);
663 		break;
664 	case DRM_FORMAT_YVYU:
665 		cfg |= (GSC_OUT_YUV422_1P |
666 			GSC_OUT_YUV422_1P_ORDER_LSB_Y |
667 			GSC_OUT_CHROMA_ORDER_CRCB);
668 		break;
669 	case DRM_FORMAT_UYVY:
670 		cfg |= (GSC_OUT_YUV422_1P |
671 			GSC_OUT_YUV422_1P_OEDER_LSB_C |
672 			GSC_OUT_CHROMA_ORDER_CBCR);
673 		break;
674 	case DRM_FORMAT_VYUY:
675 		cfg |= (GSC_OUT_YUV422_1P |
676 			GSC_OUT_YUV422_1P_OEDER_LSB_C |
677 			GSC_OUT_CHROMA_ORDER_CRCB);
678 		break;
679 	case DRM_FORMAT_NV21:
680 		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
681 		break;
682 	case DRM_FORMAT_NV61:
683 		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
684 		break;
685 	case DRM_FORMAT_YUV422:
686 		cfg |= GSC_OUT_YUV422_3P;
687 		break;
688 	case DRM_FORMAT_YUV420:
689 		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
690 		break;
691 	case DRM_FORMAT_YVU420:
692 		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
693 		break;
694 	case DRM_FORMAT_NV12:
695 		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
696 		break;
697 	case DRM_FORMAT_NV16:
698 		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
699 		break;
700 	}
701 
702 	if (tiled)
703 		cfg |= (GSC_IN_TILE_C_16x8 | GSC_OUT_TILE_MODE);
704 
705 	gsc_write(cfg, GSC_OUT_CON);
706 }
707 
708 static int gsc_get_ratio_shift(struct gsc_context *ctx, u32 src, u32 dst,
709 			       u32 *ratio)
710 {
711 	DRM_DEV_DEBUG_KMS(ctx->dev, "src[%d]dst[%d]\n", src, dst);
712 
713 	if (src >= dst * 8) {
714 		DRM_DEV_ERROR(ctx->dev, "failed to make ratio and shift.\n");
715 		return -EINVAL;
716 	} else if (src >= dst * 4)
717 		*ratio = 4;
718 	else if (src >= dst * 2)
719 		*ratio = 2;
720 	else
721 		*ratio = 1;
722 
723 	return 0;
724 }
725 
726 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
727 {
728 	if (hratio == 4 && vratio == 4)
729 		*shfactor = 4;
730 	else if ((hratio == 4 && vratio == 2) ||
731 		 (hratio == 2 && vratio == 4))
732 		*shfactor = 3;
733 	else if ((hratio == 4 && vratio == 1) ||
734 		 (hratio == 1 && vratio == 4) ||
735 		 (hratio == 2 && vratio == 2))
736 		*shfactor = 2;
737 	else if (hratio == 1 && vratio == 1)
738 		*shfactor = 0;
739 	else
740 		*shfactor = 1;
741 }
742 
743 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
744 			     struct drm_exynos_ipp_task_rect *src,
745 			     struct drm_exynos_ipp_task_rect *dst)
746 {
747 	u32 cfg;
748 	u32 src_w, src_h, dst_w, dst_h;
749 	int ret = 0;
750 
751 	src_w = src->w;
752 	src_h = src->h;
753 
754 	if (ctx->rotation) {
755 		dst_w = dst->h;
756 		dst_h = dst->w;
757 	} else {
758 		dst_w = dst->w;
759 		dst_h = dst->h;
760 	}
761 
762 	ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio);
763 	if (ret) {
764 		DRM_DEV_ERROR(ctx->dev, "failed to get ratio horizontal.\n");
765 		return ret;
766 	}
767 
768 	ret = gsc_get_ratio_shift(ctx, src_h, dst_h, &sc->pre_vratio);
769 	if (ret) {
770 		DRM_DEV_ERROR(ctx->dev, "failed to get ratio vertical.\n");
771 		return ret;
772 	}
773 
774 	DRM_DEV_DEBUG_KMS(ctx->dev, "pre_hratio[%d]pre_vratio[%d]\n",
775 			  sc->pre_hratio, sc->pre_vratio);
776 
777 	sc->main_hratio = (src_w << 16) / dst_w;
778 	sc->main_vratio = (src_h << 16) / dst_h;
779 
780 	DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
781 			  sc->main_hratio, sc->main_vratio);
782 
783 	gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
784 		&sc->pre_shfactor);
785 
786 	DRM_DEV_DEBUG_KMS(ctx->dev, "pre_shfactor[%d]\n", sc->pre_shfactor);
787 
788 	cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
789 		GSC_PRESC_H_RATIO(sc->pre_hratio) |
790 		GSC_PRESC_V_RATIO(sc->pre_vratio));
791 	gsc_write(cfg, GSC_PRE_SCALE_RATIO);
792 
793 	return ret;
794 }
795 
796 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
797 {
798 	int i, j, k, sc_ratio;
799 
800 	if (main_hratio <= GSC_SC_UP_MAX_RATIO)
801 		sc_ratio = 0;
802 	else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
803 		sc_ratio = 1;
804 	else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
805 		sc_ratio = 2;
806 	else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
807 		sc_ratio = 3;
808 	else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
809 		sc_ratio = 4;
810 	else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
811 		sc_ratio = 5;
812 	else
813 		sc_ratio = 6;
814 
815 	for (i = 0; i < GSC_COEF_PHASE; i++)
816 		for (j = 0; j < GSC_COEF_H_8T; j++)
817 			for (k = 0; k < GSC_COEF_DEPTH; k++)
818 				gsc_write(h_coef_8t[sc_ratio][i][j],
819 					GSC_HCOEF(i, j, k));
820 }
821 
822 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
823 {
824 	int i, j, k, sc_ratio;
825 
826 	if (main_vratio <= GSC_SC_UP_MAX_RATIO)
827 		sc_ratio = 0;
828 	else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
829 		sc_ratio = 1;
830 	else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
831 		sc_ratio = 2;
832 	else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
833 		sc_ratio = 3;
834 	else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
835 		sc_ratio = 4;
836 	else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
837 		sc_ratio = 5;
838 	else
839 		sc_ratio = 6;
840 
841 	for (i = 0; i < GSC_COEF_PHASE; i++)
842 		for (j = 0; j < GSC_COEF_V_4T; j++)
843 			for (k = 0; k < GSC_COEF_DEPTH; k++)
844 				gsc_write(v_coef_4t[sc_ratio][i][j],
845 					GSC_VCOEF(i, j, k));
846 }
847 
848 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
849 {
850 	u32 cfg;
851 
852 	DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
853 			  sc->main_hratio, sc->main_vratio);
854 
855 	gsc_set_h_coef(ctx, sc->main_hratio);
856 	cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
857 	gsc_write(cfg, GSC_MAIN_H_RATIO);
858 
859 	gsc_set_v_coef(ctx, sc->main_vratio);
860 	cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
861 	gsc_write(cfg, GSC_MAIN_V_RATIO);
862 }
863 
864 static void gsc_dst_set_size(struct gsc_context *ctx,
865 			     struct exynos_drm_ipp_buffer *buf)
866 {
867 	struct gsc_scaler *sc = &ctx->sc;
868 	u32 cfg;
869 
870 	/* pixel offset */
871 	cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) |
872 		GSC_DSTIMG_OFFSET_Y(buf->rect.y));
873 	gsc_write(cfg, GSC_DSTIMG_OFFSET);
874 
875 	/* scaled size */
876 	if (ctx->rotation)
877 		cfg = (GSC_SCALED_WIDTH(buf->rect.h) |
878 		       GSC_SCALED_HEIGHT(buf->rect.w));
879 	else
880 		cfg = (GSC_SCALED_WIDTH(buf->rect.w) |
881 		       GSC_SCALED_HEIGHT(buf->rect.h));
882 	gsc_write(cfg, GSC_SCALED_SIZE);
883 
884 	/* original size */
885 	cfg = gsc_read(GSC_DSTIMG_SIZE);
886 	cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK);
887 	cfg |= GSC_DSTIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
888 	       GSC_DSTIMG_HEIGHT(buf->buf.height);
889 	gsc_write(cfg, GSC_DSTIMG_SIZE);
890 
891 	cfg = gsc_read(GSC_OUT_CON);
892 	cfg &= ~GSC_OUT_RGB_TYPE_MASK;
893 
894 	if (buf->rect.w >= GSC_WIDTH_ITU_709)
895 		if (sc->range)
896 			cfg |= GSC_OUT_RGB_HD_WIDE;
897 		else
898 			cfg |= GSC_OUT_RGB_HD_NARROW;
899 	else
900 		if (sc->range)
901 			cfg |= GSC_OUT_RGB_SD_WIDE;
902 		else
903 			cfg |= GSC_OUT_RGB_SD_NARROW;
904 
905 	gsc_write(cfg, GSC_OUT_CON);
906 }
907 
908 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
909 {
910 	u32 cfg, i, buf_num = GSC_REG_SZ;
911 	u32 mask = 0x00000001;
912 
913 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
914 
915 	for (i = 0; i < GSC_REG_SZ; i++)
916 		if (cfg & (mask << i))
917 			buf_num--;
918 
919 	DRM_DEV_DEBUG_KMS(ctx->dev, "buf_num[%d]\n", buf_num);
920 
921 	return buf_num;
922 }
923 
924 static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
925 				bool enqueue)
926 {
927 	bool masked = !enqueue;
928 	u32 cfg;
929 	u32 mask = 0x00000001 << buf_id;
930 
931 	/* mask register set */
932 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
933 
934 	/* sequence id */
935 	cfg &= ~mask;
936 	cfg |= masked << buf_id;
937 	gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
938 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
939 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
940 
941 	/* interrupt enable */
942 	if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
943 		gsc_handle_irq(ctx, true, false, true);
944 
945 	/* interrupt disable */
946 	if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
947 		gsc_handle_irq(ctx, false, false, true);
948 }
949 
950 static void gsc_dst_set_addr(struct gsc_context *ctx,
951 			     u32 buf_id, struct exynos_drm_ipp_buffer *buf)
952 {
953 	/* address register set */
954 	gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
955 	gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
956 	gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
957 
958 	gsc_dst_set_buf_seq(ctx, buf_id, true);
959 }
960 
961 static int gsc_get_src_buf_index(struct gsc_context *ctx)
962 {
963 	u32 cfg, curr_index, i;
964 	u32 buf_id = GSC_MAX_SRC;
965 
966 	DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
967 
968 	cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
969 	curr_index = GSC_IN_CURR_GET_INDEX(cfg);
970 
971 	for (i = curr_index; i < GSC_MAX_SRC; i++) {
972 		if (!((cfg >> i) & 0x1)) {
973 			buf_id = i;
974 			break;
975 		}
976 	}
977 
978 	DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
979 			  curr_index, buf_id);
980 
981 	if (buf_id == GSC_MAX_SRC) {
982 		DRM_DEV_ERROR(ctx->dev, "failed to get in buffer index.\n");
983 		return -EINVAL;
984 	}
985 
986 	gsc_src_set_buf_seq(ctx, buf_id, false);
987 
988 	return buf_id;
989 }
990 
991 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
992 {
993 	u32 cfg, curr_index, i;
994 	u32 buf_id = GSC_MAX_DST;
995 
996 	DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
997 
998 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
999 	curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1000 
1001 	for (i = curr_index; i < GSC_MAX_DST; i++) {
1002 		if (!((cfg >> i) & 0x1)) {
1003 			buf_id = i;
1004 			break;
1005 		}
1006 	}
1007 
1008 	if (buf_id == GSC_MAX_DST) {
1009 		DRM_DEV_ERROR(ctx->dev, "failed to get out buffer index.\n");
1010 		return -EINVAL;
1011 	}
1012 
1013 	gsc_dst_set_buf_seq(ctx, buf_id, false);
1014 
1015 	DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1016 			  curr_index, buf_id);
1017 
1018 	return buf_id;
1019 }
1020 
1021 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1022 {
1023 	struct gsc_context *ctx = dev_id;
1024 	u32 status;
1025 	int err = 0;
1026 
1027 	DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
1028 
1029 	status = gsc_read(GSC_IRQ);
1030 	if (status & GSC_IRQ_STATUS_OR_IRQ) {
1031 		dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n",
1032 			ctx->id, status);
1033 		err = -EINVAL;
1034 	}
1035 
1036 	if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1037 		int src_buf_id, dst_buf_id;
1038 
1039 		dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n",
1040 			ctx->id, status);
1041 
1042 		src_buf_id = gsc_get_src_buf_index(ctx);
1043 		dst_buf_id = gsc_get_dst_buf_index(ctx);
1044 
1045 		DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id_src[%d]buf_id_dst[%d]\n",
1046 				  src_buf_id, dst_buf_id);
1047 
1048 		if (src_buf_id < 0 || dst_buf_id < 0)
1049 			err = -EINVAL;
1050 	}
1051 
1052 	if (ctx->task) {
1053 		struct exynos_drm_ipp_task *task = ctx->task;
1054 
1055 		ctx->task = NULL;
1056 		pm_runtime_mark_last_busy(ctx->dev);
1057 		pm_runtime_put_autosuspend(ctx->dev);
1058 		exynos_drm_ipp_task_done(task, err);
1059 	}
1060 
1061 	return IRQ_HANDLED;
1062 }
1063 
1064 static int gsc_reset(struct gsc_context *ctx)
1065 {
1066 	struct gsc_scaler *sc = &ctx->sc;
1067 	int ret;
1068 
1069 	/* reset h/w block */
1070 	ret = gsc_sw_reset(ctx);
1071 	if (ret < 0) {
1072 		dev_err(ctx->dev, "failed to reset hardware.\n");
1073 		return ret;
1074 	}
1075 
1076 	/* scaler setting */
1077 	memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1078 	sc->range = true;
1079 
1080 	return 0;
1081 }
1082 
1083 static void gsc_start(struct gsc_context *ctx)
1084 {
1085 	u32 cfg;
1086 
1087 	gsc_handle_irq(ctx, true, false, true);
1088 
1089 	/* enable one shot */
1090 	cfg = gsc_read(GSC_ENABLE);
1091 	cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1092 		GSC_ENABLE_CLK_GATE_MODE_MASK);
1093 	cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1094 	gsc_write(cfg, GSC_ENABLE);
1095 
1096 	/* src dma memory */
1097 	cfg = gsc_read(GSC_IN_CON);
1098 	cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1099 	cfg |= GSC_IN_PATH_MEMORY;
1100 	gsc_write(cfg, GSC_IN_CON);
1101 
1102 	/* dst dma memory */
1103 	cfg = gsc_read(GSC_OUT_CON);
1104 	cfg |= GSC_OUT_PATH_MEMORY;
1105 	gsc_write(cfg, GSC_OUT_CON);
1106 
1107 	gsc_set_scaler(ctx, &ctx->sc);
1108 
1109 	cfg = gsc_read(GSC_ENABLE);
1110 	cfg |= GSC_ENABLE_ON;
1111 	gsc_write(cfg, GSC_ENABLE);
1112 }
1113 
1114 static int gsc_commit(struct exynos_drm_ipp *ipp,
1115 			  struct exynos_drm_ipp_task *task)
1116 {
1117 	struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp);
1118 	int ret;
1119 
1120 	pm_runtime_get_sync(ctx->dev);
1121 	ctx->task = task;
1122 
1123 	ret = gsc_reset(ctx);
1124 	if (ret) {
1125 		pm_runtime_put_autosuspend(ctx->dev);
1126 		ctx->task = NULL;
1127 		return ret;
1128 	}
1129 
1130 	gsc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier);
1131 	gsc_src_set_transf(ctx, task->transform.rotation);
1132 	gsc_src_set_size(ctx, &task->src);
1133 	gsc_src_set_addr(ctx, 0, &task->src);
1134 	gsc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier);
1135 	gsc_dst_set_size(ctx, &task->dst);
1136 	gsc_dst_set_addr(ctx, 0, &task->dst);
1137 	gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
1138 	gsc_start(ctx);
1139 
1140 	return 0;
1141 }
1142 
1143 static void gsc_abort(struct exynos_drm_ipp *ipp,
1144 			  struct exynos_drm_ipp_task *task)
1145 {
1146 	struct gsc_context *ctx =
1147 			container_of(ipp, struct gsc_context, ipp);
1148 
1149 	gsc_reset(ctx);
1150 	if (ctx->task) {
1151 		struct exynos_drm_ipp_task *task = ctx->task;
1152 
1153 		ctx->task = NULL;
1154 		pm_runtime_mark_last_busy(ctx->dev);
1155 		pm_runtime_put_autosuspend(ctx->dev);
1156 		exynos_drm_ipp_task_done(task, -EIO);
1157 	}
1158 }
1159 
1160 static struct exynos_drm_ipp_funcs ipp_funcs = {
1161 	.commit = gsc_commit,
1162 	.abort = gsc_abort,
1163 };
1164 
1165 static int gsc_bind(struct device *dev, struct device *master, void *data)
1166 {
1167 	struct gsc_context *ctx = dev_get_drvdata(dev);
1168 	struct drm_device *drm_dev = data;
1169 	struct exynos_drm_ipp *ipp = &ctx->ipp;
1170 
1171 	ctx->drm_dev = drm_dev;
1172 	ctx->drm_dev = drm_dev;
1173 	exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1174 
1175 	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
1176 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
1177 			DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
1178 			ctx->formats, ctx->num_formats, "gsc");
1179 
1180 	dev_info(dev, "The exynos gscaler has been probed successfully\n");
1181 
1182 	return 0;
1183 }
1184 
1185 static void gsc_unbind(struct device *dev, struct device *master,
1186 			void *data)
1187 {
1188 	struct gsc_context *ctx = dev_get_drvdata(dev);
1189 	struct drm_device *drm_dev = data;
1190 	struct exynos_drm_ipp *ipp = &ctx->ipp;
1191 
1192 	exynos_drm_ipp_unregister(dev, ipp);
1193 	exynos_drm_unregister_dma(drm_dev, dev, &ctx->dma_priv);
1194 }
1195 
1196 static const struct component_ops gsc_component_ops = {
1197 	.bind	= gsc_bind,
1198 	.unbind = gsc_unbind,
1199 };
1200 
1201 static const unsigned int gsc_formats[] = {
1202 	DRM_FORMAT_ARGB8888,
1203 	DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888,
1204 	DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
1205 	DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
1206 	DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
1207 };
1208 
1209 static const unsigned int gsc_tiled_formats[] = {
1210 	DRM_FORMAT_NV12, DRM_FORMAT_NV21,
1211 };
1212 
1213 static int gsc_probe(struct platform_device *pdev)
1214 {
1215 	struct device *dev = &pdev->dev;
1216 	struct gsc_driverdata *driver_data;
1217 	struct exynos_drm_ipp_formats *formats;
1218 	struct gsc_context *ctx;
1219 	struct resource *res;
1220 	int num_formats, ret, i, j;
1221 
1222 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1223 	if (!ctx)
1224 		return -ENOMEM;
1225 
1226 	driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev);
1227 	ctx->dev = dev;
1228 	ctx->num_clocks = driver_data->num_clocks;
1229 	ctx->clk_names = driver_data->clk_names;
1230 
1231 	/* construct formats/limits array */
1232 	num_formats = ARRAY_SIZE(gsc_formats) + ARRAY_SIZE(gsc_tiled_formats);
1233 	formats = devm_kcalloc(dev, num_formats, sizeof(*formats), GFP_KERNEL);
1234 	if (!formats)
1235 		return -ENOMEM;
1236 
1237 	/* linear formats */
1238 	for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) {
1239 		formats[i].fourcc = gsc_formats[i];
1240 		formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1241 				  DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1242 		formats[i].limits = driver_data->limits;
1243 		formats[i].num_limits = driver_data->num_limits;
1244 	}
1245 
1246 	/* tiled formats */
1247 	for (j = i, i = 0; i < ARRAY_SIZE(gsc_tiled_formats); j++, i++) {
1248 		formats[j].fourcc = gsc_tiled_formats[i];
1249 		formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_16_16_TILE;
1250 		formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1251 				  DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1252 		formats[j].limits = driver_data->limits;
1253 		formats[j].num_limits = driver_data->num_limits;
1254 	}
1255 
1256 	ctx->formats = formats;
1257 	ctx->num_formats = num_formats;
1258 
1259 	/* clock control */
1260 	for (i = 0; i < ctx->num_clocks; i++) {
1261 		ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
1262 		if (IS_ERR(ctx->clocks[i])) {
1263 			dev_err(dev, "failed to get clock: %s\n",
1264 				ctx->clk_names[i]);
1265 			return PTR_ERR(ctx->clocks[i]);
1266 		}
1267 	}
1268 
1269 	/* resource memory */
1270 	ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1271 	ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1272 	if (IS_ERR(ctx->regs))
1273 		return PTR_ERR(ctx->regs);
1274 
1275 	/* resource irq */
1276 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1277 	if (!res) {
1278 		dev_err(dev, "failed to request irq resource.\n");
1279 		return -ENOENT;
1280 	}
1281 
1282 	ctx->irq = res->start;
1283 	ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0,
1284 			       dev_name(dev), ctx);
1285 	if (ret < 0) {
1286 		dev_err(dev, "failed to request irq.\n");
1287 		return ret;
1288 	}
1289 
1290 	/* context initailization */
1291 	ctx->id = pdev->id;
1292 
1293 	platform_set_drvdata(pdev, ctx);
1294 
1295 	pm_runtime_use_autosuspend(dev);
1296 	pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY);
1297 	pm_runtime_enable(dev);
1298 
1299 	ret = component_add(dev, &gsc_component_ops);
1300 	if (ret)
1301 		goto err_pm_dis;
1302 
1303 	dev_info(dev, "drm gsc registered successfully.\n");
1304 
1305 	return 0;
1306 
1307 err_pm_dis:
1308 	pm_runtime_dont_use_autosuspend(dev);
1309 	pm_runtime_disable(dev);
1310 	return ret;
1311 }
1312 
1313 static int gsc_remove(struct platform_device *pdev)
1314 {
1315 	struct device *dev = &pdev->dev;
1316 
1317 	component_del(dev, &gsc_component_ops);
1318 	pm_runtime_dont_use_autosuspend(dev);
1319 	pm_runtime_disable(dev);
1320 
1321 	return 0;
1322 }
1323 
1324 static int __maybe_unused gsc_runtime_suspend(struct device *dev)
1325 {
1326 	struct gsc_context *ctx = get_gsc_context(dev);
1327 	int i;
1328 
1329 	DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1330 
1331 	for (i = ctx->num_clocks - 1; i >= 0; i--)
1332 		clk_disable_unprepare(ctx->clocks[i]);
1333 
1334 	return 0;
1335 }
1336 
1337 static int __maybe_unused gsc_runtime_resume(struct device *dev)
1338 {
1339 	struct gsc_context *ctx = get_gsc_context(dev);
1340 	int i, ret;
1341 
1342 	DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1343 
1344 	for (i = 0; i < ctx->num_clocks; i++) {
1345 		ret = clk_prepare_enable(ctx->clocks[i]);
1346 		if (ret) {
1347 			while (--i > 0)
1348 				clk_disable_unprepare(ctx->clocks[i]);
1349 			return ret;
1350 		}
1351 	}
1352 	return 0;
1353 }
1354 
1355 static const struct dev_pm_ops gsc_pm_ops = {
1356 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1357 				pm_runtime_force_resume)
1358 	SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1359 };
1360 
1361 static const struct drm_exynos_ipp_limit gsc_5250_limits[] = {
1362 	{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1363 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1364 	{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
1365 	{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1366 			  .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1367 };
1368 
1369 static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
1370 	{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1371 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1372 	{ IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
1373 	{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1374 			  .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1375 };
1376 
1377 static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
1378 	{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
1379 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
1380 	{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
1381 	{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1382 			  .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1383 };
1384 
1385 static struct gsc_driverdata gsc_exynos5250_drvdata = {
1386 	.clk_names = {"gscl"},
1387 	.num_clocks = 1,
1388 	.limits = gsc_5250_limits,
1389 	.num_limits = ARRAY_SIZE(gsc_5250_limits),
1390 };
1391 
1392 static struct gsc_driverdata gsc_exynos5420_drvdata = {
1393 	.clk_names = {"gscl"},
1394 	.num_clocks = 1,
1395 	.limits = gsc_5420_limits,
1396 	.num_limits = ARRAY_SIZE(gsc_5420_limits),
1397 };
1398 
1399 static struct gsc_driverdata gsc_exynos5433_drvdata = {
1400 	.clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
1401 	.num_clocks = 4,
1402 	.limits = gsc_5433_limits,
1403 	.num_limits = ARRAY_SIZE(gsc_5433_limits),
1404 };
1405 
1406 static const struct of_device_id exynos_drm_gsc_of_match[] = {
1407 	{
1408 		.compatible = "samsung,exynos5-gsc",
1409 		.data = &gsc_exynos5250_drvdata,
1410 	}, {
1411 		.compatible = "samsung,exynos5250-gsc",
1412 		.data = &gsc_exynos5250_drvdata,
1413 	}, {
1414 		.compatible = "samsung,exynos5420-gsc",
1415 		.data = &gsc_exynos5420_drvdata,
1416 	}, {
1417 		.compatible = "samsung,exynos5433-gsc",
1418 		.data = &gsc_exynos5433_drvdata,
1419 	}, {
1420 	},
1421 };
1422 MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
1423 
1424 struct platform_driver gsc_driver = {
1425 	.probe		= gsc_probe,
1426 	.remove		= gsc_remove,
1427 	.driver		= {
1428 		.name	= "exynos-drm-gsc",
1429 		.owner	= THIS_MODULE,
1430 		.pm	= &gsc_pm_ops,
1431 		.of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
1432 	},
1433 };
1434